JP2009094212A - Test circuit, semiconductor wafer device, and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test circuit capable of specifying a place generating a contact failure, and to provide a semiconductor wafer device and a test method. <P>SOLUTION: The test circuit includes: a contact chain 50 which contains a plurality of serially-connected contact resistances R; transistors TR in which a source region 17a is electrically connected to a connection point P of the adjacent contact resistances R; and a fuse 22 whose one end is electrically connected to a drain region 17b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a test circuit, a semiconductor wafer device, and a test method.

  In a manufacturing process of a semiconductor device such as an LSI, a test circuit may be formed on a substrate together with a product circuit in order to check whether the manufacturing process has a tendency to make the semiconductor device defective.

  A test chain disclosed in Patent Document 1 is used as a test circuit to test a contact resistance failure of a conductive plug.

  The contact chain is formed by forming a plurality of impurity diffusion regions on a semiconductor substrate, forming a predetermined number of conductive plugs on each impurity diffusion region, and connecting the conductive plugs on different impurity diffusion regions with wiring. (See FIG. 1B of Patent Document 1). This has a circuit structure in which a plurality of contact resistances between the conductive plug and the impurity diffusion region are connected in series between the diffusion layer and the wiring.

  If all the conductive plugs are connected to the underlying impurity diffusion region, a current flows through the contact chain by applying a voltage to both ends of the contact chain.

  On the other hand, if at least one of the plurality of conductive plugs is not connected to the impurity diffusion region, the contact chain in the conductive plug is opened in a circuit, and even if a voltage is applied, a current is applied to the contact chain. Does not flow.

  Therefore, the presence or absence of a conductive plug having a contact failure can be confirmed by the presence or absence of a current flowing through the contact chain. Furthermore, by forming a contact chain from a plurality of contact resistances formed in series, the current does not flow if even one of the contact resistances is abnormal, so the detection sensitivity of contact failure can be increased. .

  However, in this method, if any one of the plurality of conductive plugs has a contact failure, current does not flow. Therefore, it is not possible to specify which conductive plug has the contact failure. In order to identify, in a test device called EB (Electron Beam) tester, it is necessary to apply a probe to each conductive plug and investigate which conductive plug is defective. Is also inefficient.

  As a method for more efficiently identifying the location of a contact failure than this, in Patent Document 2, each conductive plug is selected by a transistor, and a current is passed through the selected conductive plug to check whether there is a contact failure. .

  However, in this method, the circuit for selecting the conductive plug is complicated and requires more transistors than the number of the conductive plugs. Therefore, the area occupied by the test circuit in the semiconductor substrate increases, and the fineness of the semiconductor device is increased. A new problem arises that hinders the transformation.

A technique related to the present invention is also disclosed in Patent Document 3.
JP 2000-21945 A JP-A-10-135212 JP 2002-26127 A

  An object of the present invention is to provide a test circuit, a semiconductor wafer device, and a test method that can specify a location where a contact failure occurs.

  According to one aspect of the present invention, a contact chain including a plurality of contact resistors connected in series, and a transistor in which one of a source region and a drain region is electrically connected to a connection point between adjacent contact resistors. A test circuit is provided that includes a fuse having one end electrically connected to the other of the source region and the drain region.

  According to another aspect of the present invention, one of the source region and the drain region is electrically connected to a contact chain including a plurality of contact resistors connected in series and a connection point between the adjacent contact resistors. There is provided a semiconductor wafer device having a transistor and a fuse having one end electrically connected to the other of the source region and the drain region as a test circuit on a semiconductor substrate.

  According to another aspect of the present invention, a predetermined potential difference is applied to both ends of a contact chain including a plurality of contact resistors connected in series, and a source region and a drain are connected to a connection point of the adjacent contact resistors. When a predetermined voltage is applied to the gate electrode of a transistor in which one of the regions is electrically connected and one of the contact resistors is open, one end is electrically connected to the other of the source region and the drain region. A current is passed through the transistor from the contact chain through the transistor to confirm the location of the contact resistance that is open by confirming that the fuse has been cut by the current. A test method is provided.

  According to the present invention, when there is an open contact resistance, current flows from the contact chain to the fuse through the transistor, and the fuse is cut. Therefore, by identifying the location of the blown fuse, it is possible not only to grasp the existence of the open contact resistance, but also to identify which of the multiple contact resistances is open. .

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(1) First Embodiment FIG. 1 is an enlarged plan view of a semiconductor wafer device according to the present embodiment.

  This semiconductor wafer device 5 has a plurality of chip regions 4 on a silicon substrate 1 in one shot region 2 of an exposure apparatus. The silicon substrate 1 is finally diced and becomes a semiconductor device such as an LSI separated into individual chip regions 4.

  The area between the chip areas 4 is called a scribe area. In the present embodiment, test circuits 3 to be described later are formed in the scribe areas at the four corners of the one-shot area 2.

  If there is an empty area inside the chip area 4, the test circuit 3 may be formed in the empty area. In that case, the test circuit 3 also remains in the semiconductor device after dicing.

  FIG. 2 is an enlarged cross-sectional view of a portion of the semiconductor wafer device 5 where the test circuit 3 is formed.

  As shown in FIG. 2, an element isolation insulating film 10 is formed on the silicon substrate 1 by a LOCOS (Local Oxidation of Silicon) method or the like, and the active region of the silicon substrate 1 is defined by the element isolation insulating film 10. Then, an n-well 11 is formed at a predetermined depth of the silicon substrate 1.

  On the active region, a gate electrode 15 is formed via a gate insulating film 13, and a p-type source region 17a and a p-type drain region 17b are formed on the silicon substrate 1 beside the gate electrode 15. These regions 17 a and 17 b constitute a p-type MOS transistor TR together with the gate insulating film 13 and the gate electrode 15.

  A p-type impurity diffusion region 17c for ground having a ground potential is formed in a portion of the silicon substrate 1 spaced from the p-type source / drain regions 17a and 17b. Each region 17a to 17c is reduced in resistance by a refractory metal layer 18 such as a cobalt silicide layer formed on the surface layer.

  A first interlayer insulating film 20 such as a silicon oxide film is formed on the entire upper surface of the silicon substrate 1, and a fuse 22 made of polysilicon is further formed thereon. A first contact hole 20a is formed in the first interlayer insulating film 20 on the drain region 17b and the ground p-type impurity diffusion region 17c, and both ends of the fuse 22 are connected to the regions 17b and 17c via the hole 20a. Is electrically connected.

  A second interlayer insulating film 24 made of silicon oxide, BPSG, or the like is formed on the fuse 22 and the first interlayer insulating film 20. Further, a second contact hole 26 is formed in the first and second interlayer insulating films 20 and 24 on the source region 17a, and the conductive layer is mainly composed of tungsten and is electrically connected to the source region 17a. A conductive plug 27 is formed in the second contact hole 26.

  On the second interlayer insulating film 24 and the conductive plug 27, a metal wiring 30 made of a metal laminated film including an aluminum film is formed.

  FIG. 3 is an enlarged plan view of a portion where the test circuit 3 is formed in the semiconductor wafer device 5. 2 corresponds to a cross-sectional view taken along line AA in FIG.

  As shown in FIG. 3, the element isolation insulating film 10 is provided with a plurality of first and second openings 10a, 10b. Then, the gate electrode 15 extends in a stripe shape on the silicon substrate 1 so as to be common to a plurality of active regions defined by the first openings 10a.

  A plurality of fuses 22 are provided so as to correspond to the respective drain regions 17b.

  On the other hand, the conductive plug 27, the metal wiring 30, and the source region 17a are alternately connected in series as shown in the figure, and constitute a contact chain 50.

  A cross-sectional structure of the contact chain 50 is shown in FIG. 4 corresponds to a cross-sectional view taken along line BB in FIG.

  FIG. 5 is an equivalent circuit diagram of this test circuit.

  In the figure, the resistance between the conductive plug 27 and the p-type source region 17a is represented as a contact resistance R.

  As shown in this figure, in this embodiment, two adjacent contact resistances R are defined as one group G, and a plurality of transistors TR are provided corresponding to each connection point P of each group. Are connected to the source region of each transistor TR.

  The contact chain 50 has a structure in which a plurality of contact resistors R are connected in series in terms of circuit.

  Next, a test method using this test circuit will be described with reference to FIGS.

  This test is performed at the wafer level in order to specify the location where the contact failure occurs, and a voltage required for the test is applied to the semiconductor wafer device 5 from a probe card of a test apparatus (not shown).

  FIG. 6 is a diagram illustrating a case where there is no contact failure.

In the test, one end X of the contact chain 50 is grounded, and the positive first voltage V ₁ is applied to the other end Y. As a result, the potential difference between both ends of the contact chain 50 becomes V ₁ . The first voltage V ₁ is selected according to the product, and is 5 V, for example, in the present embodiment.

A positive second voltage V ₂ is applied to the gate electrode 15 such that the transistor TR is turned on when the source-drain voltage of the transistor TR is the first voltage V ₁ . In the present embodiment, a voltage of about ₁ to 1.5 V is applied to the gate electrode 15 as the second voltage V2.

Here, when all the contact resistances R are not defective, a current I ₀ flows between both ends X and Y of the contact chain 50. Further, since the voltage drop occurs in each contact resistance R due to the current I _0, the potential of each connection point P becomes lower than the first voltage V ₁ . Accordingly, the potential difference between the source and drain of each transistor TR is also lower than the first voltage V ₁ , so that each transistor TR is turned off and the fuse 22 is not cut by current.

  On the other hand, FIG. 7 is a diagram illustrating a case where there is a contact failure.

In the example of FIG. 7, the contact resistance represented by R _f is open due to a failure. In this case, the current I ₀ does not flow between both ends X and Y of the contact chain 50. Therefore, since a voltage drop at each contact resistance R does not substantially occur, the potential at each connection point P between the other end Y and the defective contact resistance R _f is the first voltage V ₁ . Become.

As a result, the potential difference between the source and drain of the transistor TR connected to these connection points P is also the first voltage V ₁ , so that these transistors TR are turned on and connected to the transistor TR. A current I ₁ is supplied from the contact chain 50 to the fuse 22, and the fuse 22 is cut by this current I ₁ .

  Whether or not the fuse 22 is cut can be visually confirmed using a metal microscope having a magnification of 100 to 200 times. If it is confirmed that the fuse 22 has been disconnected, it is determined that a contact failure has occurred in the group G connected to the fuse 22 in the portion closest to the one end X among the disconnected fuses 22. be able to.

  As described above, according to the present embodiment, since the transistor TR and the fuse 22 are provided at the connection point P of the contact chain 50, by checking the position of the fuse 22 that has been cut due to the contact failure, It is possible to grasp at which part of the contact chain 50 the contact failure has occurred.

  In addition, in this circuit configuration, only one transistor TR is required for the two contact resistances R. Therefore, the position of the contact failure can be specified very easily without increasing the scale of the circuit.

(2) Second Embodiment In this embodiment, a method for manufacturing the semiconductor wafer device described in the first embodiment will be described.

  8 to 13 are cross-sectional views of the semiconductor wafer device according to the present embodiment during manufacture. In these sectional views, the first region I in which the test circuit 3 described in the first embodiment is formed and the second region II in which a logic circuit and the like are formed are shown together.

  First, steps required until a sectional structure shown in FIG.

  First, an element isolation insulating film 10 is formed on the surface of the silicon substrate 1 by the LOCOS method, and then n-type impurities are ion-implanted into the silicon substrate 1 to form n wells 8 and 11.

  Next, a threshold adjustment impurity diffusion region (not shown) for adjusting the threshold voltage of the transistor is formed in the surface layer of each well 8 and 11, and then the surface of the silicon substrate 1 is thermally oxidized to form the gate insulating film 13. To do. Further, a polysilicon film is formed on the gate insulating film 13, and the polysilicon film is patterned to form gate electrodes 14 and 15.

  Next, as shown in FIG. 9, p-type source / drain extensions 16 are formed by ion-implanting p-type impurities into the silicon substrate using the gate electrodes 14 and 15 as a mask.

  Thereafter, an insulating film such as a silicon oxide film is formed on the entire upper surface of the silicon substrate 1, and the insulating film is etched back to be left as an insulating sidewall 19 next to the gate electrodes 14 and 15.

  Then, the p-type impurity is ion-implanted again into the silicon substrate 1 using the insulating sidewall 19 and the gate electrodes 14 and 15 as a mask. As a result, in the first region I, the p-type source region 17a and the p-type drain region 17b are formed on the silicon substrate 1 beside the gate electrode 15, and a portion of the silicon away from these regions 17a and 17b. A p-type impurity diffusion region 17c for ground is formed on the substrate 1.

  On the other hand, in the second region II, a p-type source region 17d and a p-type drain region 17e are formed as shown in the silicon substrate 1 beside the gate electrode.

  Thereafter, a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the silicon substrate 1 by a sputtering method, and the refractory metal layer is annealed and reacted with silicon to form a high layer on the surface layer portion of each region 17a to 17e. A melting point metal silicide layer 18 is formed. The refractory metal layer that has not reacted on the element isolation insulating film 10 and the like is removed by wet etching.

  In addition, annealing for activating the impurities in the regions 17a to 17e may be performed in this state.

  Through the steps so far, the basic structure of the p-type MOS transistor TR is obtained in each of the first region I and the second region II. Among these MOS transistors TR, those formed in the first region I constitute the above-described test circuit 3 (see FIG. 2). On the other hand, the MOS transistor TR formed in the second region II constitutes a logic circuit, for example.

  Next, as shown in FIG. 10, a silicon oxide film is formed to a thickness of about 600 nm on the entire upper surface of the silicon substrate 1 by CVD, and the silicon oxide film is used as a first interlayer insulating film 20.

  Further, the upper surface of the first interlayer insulating film 20 is polished and planarized by a CMP (Chemical Mechanical Polishing) method, and then the first interlayer insulating film 20 is patterned by photolithography, whereby the p-type drain region 17b and the ground are formed. A first contact hole 20a is formed in the first interlayer insulating film 20 on the p-type impurity diffusion region 17c.

  Next, steps required until a sectional structure shown in FIG.

  First, a polysilicon film is formed to a thickness of about 200 nm on the first interlayer insulating film 20 and in the first contact hole 20a by the CVD method. Next, the polysilicon film is patterned by photolithography to form the fuse 22 having both ends electrically connected to the regions 17b and 17c.

  Although it is conceivable that the fuse 22 is made of a metal such as aluminum, since the metal has a higher electric resistance than polysilicon, the fuse 22 may be difficult to be cut during a test. Therefore, from the viewpoint of facilitating cutting of the fuse 22, it is preferable that the fuse 22 is made of polysilicon or amorphous silicon as in the present embodiment.

  Next, as shown in FIG. 12, a second interlayer insulating film 24 made of silicon oxide or BPSG is formed on the first interlayer insulating film 20 and the fuse 22 by a CVD method to a thickness of about 1000 nm. Thereafter, the upper surface of the second interlayer insulating film 24 is polished and planarized by the CMP method.

  Then, by selectively etching the first and second interlayer insulating films 20 and 24 using a resist pattern (not shown) as a mask, a second contact hole 26 is formed in these insulating films on the p-type source region 17a. Form.

  Next, steps required until a sectional structure shown in FIG.

  First, a titanium film and a titanium nitride film are formed in this order as a glue film in the second interlayer insulating film 24 and the second contact hole 26 by a sputtering method. Then, a tungsten film is formed on the glue film by the CVD method, and the second contact hole 26 is completely filled with this tungsten film. Thereafter, excess glue film and tungsten film on the second interlayer insulating film 24 are removed by polishing by the CMP method, and these films are left as the conductive plugs 27 only in the second contact holes 26.

  Further, a metal laminated film including an aluminum film is formed on each of the second interlayer insulating film 24 and the second conductive plug 27 by sputtering, and then the metal laminated film is patterned to form a metal wiring 30. .

  Thus, the basic structure of the semiconductor wafer device according to this embodiment is completed.

  After that, dicing is performed along the scribe region to move to a step of obtaining an individualized semiconductor device, but details thereof are omitted.

  For this semiconductor wafer device, the test described in the first embodiment is performed at the wafer level in order to specify the position of contact failure. If the test reveals that there is a contact failure, review the process conditions according to the cause of the contact failure.

  For example, in the etching process of FIG. 12, the second contact hole 26 is not opened, so that the second conductive plug 27 (see FIG. 13) and the source region 17a are not electrically connected, resulting in a contact failure. If so, the etching time is increased so that the second contact hole 26 is completely opened.

  Further, when a contact failure occurs due to the natural oxide film formed on the refractory metal layer 18, the process of forming the first interlayer insulating film 20 from the process of forming the refractory metal layer 18. By shortening the time until the refractory metal layer 18 is exposed to the atmosphere, the time required for exposure to the atmosphere can be shortened to prevent the occurrence of contact failure associated with the natural oxide film.

  Since the contact defect detection sensitivity in the contact chain 50 is very high, there are many cases where no contact defect occurs in the logic circuit in the second region II even if a contact defect is detected. However, by reviewing the process conditions as described above, the risk of contact failure occurring in the logic circuit can be reduced, which can contribute to an improvement in the yield of the semiconductor device.

  As mentioned above, although embodiment of this invention was described in detail, this invention is not limited to said each embodiment.

  For example, although the p-type MOS transistor TR is formed in the above, an n-type MOS transistor may be formed instead.

FIG. 1 is an enlarged plan view of the semiconductor wafer device according to the present embodiment. FIG. 2 is an enlarged cross-sectional view of a portion where a test circuit is formed in the semiconductor wafer device according to the present embodiment. FIG. 3 is an enlarged plan view of a portion where a test circuit is formed in the semiconductor wafer device according to the present embodiment. FIG. 4 is an enlarged cross-sectional view of the contact chain according to the present embodiment. FIG. 5 is an equivalent circuit diagram of the test circuit according to the present embodiment. FIG. 6 is a diagram illustrating a test method according to the present embodiment when there is no contact failure. FIG. 7 is a diagram for explaining a test method according to the present embodiment when there is a contact failure. FIG. 8 is a cross-sectional view (part 1) of the semiconductor wafer device according to this embodiment in the middle of manufacture. FIG. 9 is a cross-sectional view (part 2) of the semiconductor wafer device according to the present embodiment during manufacture. FIG. 10 is a cross-sectional view (part 3) of the semiconductor wafer device according to this embodiment in the middle of manufacture. FIG. 11 is a cross-sectional view (part 4) of the semiconductor wafer device according to the present embodiment in the middle of manufacture. FIG. 12 is a sectional view (No. 5) of the semiconductor wafer device according to the present embodiment in the middle of manufacture. FIG. 13 is a cross-sectional view (No. 6) of the semiconductor wafer device according to the present embodiment during manufacture.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... 1 shot area | region, 3 ... Test circuit, 4 ... Chip area | region, 5 ... Semiconductor wafer apparatus, 8, 11 ... N well, 10 ... Element isolation insulating film, 10a, 10b ... 1st, 2nd Opening, 13 ... Gate insulating film, 14, 15 ... Gate electrode, 16 ... p-type source / drain extension, 17a, 17d ... p-type source region, 17b, 17e ... p-type drain region, 17c ... p-type impurity diffusion for ground Region 18 Refractory metal silicide layer 19 Insulating sidewall 20 20 First interlayer insulating film 20 a First contact hole 22 Fuse 24 Second interlayer insulating film 26 Second contact hole , 27 ... conductive plug, 30 ... metal wiring, R ... contact resistance, TR ... p-type MOS transistor, I ₀ , I ₁ ... current, V ₁ , V ₂ ... first and second voltages.

Claims (7)

A contact chain including a plurality of contact resistors connected in series;
A transistor in which one of a source region and a drain region is electrically connected to a connection point of adjacent contact resistors;
A fuse having one end electrically connected to the other of the source region and the drain region;
A test circuit comprising:   A predetermined number of adjacent contact resistors are grouped together, and the transistor is provided corresponding to each connection point of each group, and one of the source region and drain region of the transistor is provided at the connection point. The test circuit according to claim 1, wherein the test circuit is connected.   3. The contact resistance according to claim 1, wherein the contact resistance is a resistance between one of the source region and the drain region and a conductive plug formed on the one region. Test circuit.   When a predetermined potential difference is applied to both ends of the contact chain and a predetermined voltage is applied to the gate electrode of the transistor, the transistor is removed from the contact chain when one of the contact resistors is open. 4. The test circuit according to claim 1, wherein a current is passed through the fuse to cut the fuse. 5.   The test circuit according to claim 4, wherein the predetermined voltage applied to the gate electrode is a voltage that turns on the transistor when a voltage between a source and a drain of the transistor is the potential difference. A contact chain including a plurality of contact resistors connected in series;
A transistor in which one of a source region and a drain region is electrically connected to a connection point of adjacent contact resistors;
A fuse having one end electrically connected to the other of the source region and the drain region;
As a test circuit on a semiconductor substrate. In addition to applying a predetermined potential difference to both ends of a contact chain including a plurality of contact resistors connected in series,
Applying a predetermined voltage to the gate electrode of the transistor in which one of the source region and the drain region is electrically connected to the connection point of the adjacent contact resistance,
When one of the contact resistors is open, a current is passed through the transistor from the contact chain to a fuse having one end electrically connected to the other of the source region and the drain region,
A test method characterized in that the location of the contact resistance that is open is determined by confirming that the fuse has been blown by the current.

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