JP2008060213A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device that can reduce an occupation area and can shorten an inspection period. <P>SOLUTION: The method for manufacturing a semiconductor device comprises steps of forming a resistance pattern 18a for a first inspection on a semiconductor substrate 1 located at a scribe line, by conducting a first impurity introducing process to dope an impurity into the semiconductor substrate 1 located at a first channel region 8a; forming a resistance pattern 18b for a second inspection on the semiconductor substrate 1 located at the scribe line by conducting a second impurity introducing process, in the impurity concentration different from that of the first impurity introducing process to dope an impurity to the semiconductor substrate 1 located at a second channel region 8b; and forming a wiring pattern 12c for connecting in parallel the resistance pattern 18a for the first inspection and the resistance pattern 18b for the second inspection. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having an inspection element for inspecting whether or not impurities are normally introduced into a channel region. In particular, the present invention relates to a method for manufacturing a semiconductor device that can reduce the area occupied by a testing element and a pad on a semiconductor substrate and can shorten the testing time.

  FIG. 7 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device. In this method of manufacturing a semiconductor device, a TEG (Test Element Group) is used to form two transistors having different threshold voltages on a silicon wafer 101 and inspect whether impurities are normally introduced into the channel regions of the two transistors. This is a method of forming in the TEG formation region 101c.

  In this method, the introduction of impurities into the channel region 108a of the first transistor is performed, for example, after the gate oxide film 3a is formed. In this impurity introduction step, a resistance element 118a is formed on the silicon wafer 101 located in the TEG formation region 101c. Resistive element 118a has the same impurity concentration as channel region 108a.

  Further, the introduction of impurities into the channel region 108b of the second transistor is performed after the gate oxide film 3b is formed, for example. The impurity concentration of the channel region 108b is different from the impurity concentration of the channel region 108a. In this impurity introduction step, a resistance element 118b is formed on the silicon wafer 101 located in the TEG formation region 101c. Resistive element 118b has the same impurity concentration as channel region 108b.

  After the resistance elements 118a and 118b are formed, the resistance elements 118a and 118b are respectively formed of tungsten plugs 109a and 109b embedded in the interlayer insulating film 109, Al alloy patterns 111a and 111b formed on the interlayer insulating film 109, and They are connected to different Al alloy pads 112a and 112b through a wiring layer (not shown). Then, by connecting a test terminal to the Al alloy pad 112a, the resistance of the resistance element 118a is measured, and it is inspected whether or not the impurity is normally introduced into the channel region 108a. Further, by connecting a test terminal to the Al alloy pad 112b, the resistance of the resistance element 118b is measured, and it is inspected whether or not the impurity is normally introduced into the channel region 108b.

  Patent Document 1 discloses a method for inspecting whether or not impurities are normally introduced into a channel stop region by using a threshold voltage of a transistor.

Japanese Patent Laid-Open No. 9-036189 (FIG. 1, paragraphs 12 to 18)

  In the method shown in FIG. 7 and the method disclosed in Patent Document 1, it is necessary to form an inspection element and a pad connected to the inspection element for each impurity implantation step to be measured. For this reason, the area which a test element and a pad occupy in a semiconductor substrate has become large. Further, since it is necessary to inspect each element for inspection formed for each of a plurality of implantation steps, it takes time for the inspection.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the occupied area and shorten the inspection time. is there.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention introduces an impurity into a first channel region of a semiconductor substrate by performing a first impurity introduction process, and scribe lines of the semiconductor substrate. Forming a first resistance pattern for inspection in
Impurities are introduced into the second channel region of the semiconductor substrate by performing a second impurity introduction process at an impurity concentration different from that of the first impurity introduction process, and a second inspection resistor is applied to the scribe line. Forming a pattern;
Forming a wiring pattern for connecting the first inspection resistance pattern and the second inspection resistance pattern in parallel.

The method for manufacturing a semiconductor device according to the present invention introduces an impurity into a first channel region of a semiconductor substrate by performing a first impurity introduction process, and performs a first inspection for a TEG formation region of the semiconductor substrate. Forming a resistance pattern;
Impurities are introduced into the second channel region of the semiconductor substrate by performing the second impurity introduction treatment with an impurity concentration different from that of the first impurity introduction treatment, and a second inspection is performed in the TEG formation region. Forming a resistance pattern;
Forming a wiring pattern for connecting the first inspection resistance pattern and the second inspection resistance pattern in parallel.

  According to these semiconductor device manufacturing methods, after forming the wiring pattern, a test terminal is electrically connected to the wiring pattern, and a combined resistance of the first and second inspection resistance patterns is measured. By investigating whether the value of this combined resistance indicates the designed combined resistance value, the resistance value of the first test resistor pattern alone, or the resistance value of the second test resistor pattern alone, It can be checked whether or not the first and second impurity introduction steps are normally performed. Therefore, the inspection time can be shortened.

  Further, since it is sufficient to form a pad connected to the wiring pattern, it is not necessary to form a pad for each inspection resistance pattern. Therefore, the occupation area can be reduced.

The impurity introduced into the first channel region is, for example, a threshold voltage adjusting impurity of the first transistor, and the impurity introduced into the second channel region is, for example, the threshold voltage adjusting of the second transistor. Impurities. In this case, the first and second transistors have different threshold voltages.
The first and second inspection resistance patterns are preferably located next to each other.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 to 4 are views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. In each figure, (A) is a cross-sectional view, and (B) is a plan view of a TEG formation region 1c. In this method, a first transistor located in the first element region 1a, a second transistor located in the second element region 1b, and a TEG located in the TEG formation region 1c are formed on the silicon wafer 1. The first and second transistors have different threshold voltages. Thereafter, using TEG, it is inspected whether or not impurities are normally introduced into the channel regions of the first and second transistors.

The TEG formation region 1c may be located on the scribe line as shown in FIG. 5A, or located in a region located between the scribe lines as shown in FIG. 5B. May be.
Details will be described below.

  First, as shown in FIGS. 1A and 1B, a first conductivity type (for example, P type) well 20a located in the first element region 1a and a first conductivity type located in the second element region 1b are formed on the silicon wafer 1. A well 20b and a first conductivity type well 20c located in the TEG formation region 1c are formed. Next, the element isolation film 2 is embedded in the silicon wafer 1, and the first element region 1a, the second element region 1b, and the TEG formation region 1c are separated from other regions.

  Next, the silicon wafer 1 is thermally oxidized. Thus, the gate oxide film 3a of the first transistor is formed on the silicon wafer 1 located in the first element region 1a, and the gate oxide film of the second transistor is formed on the silicon wafer 1 located in the second element region 1b. 3b is formed. By this step, a thermal oxide film 3c having substantially the same thickness as the gate oxide films 3a and 3b is also formed on the silicon wafer 1 located in the TEG formation region 1c.

  Next, as shown in each drawing of FIG. 2, a photoresist film 50 is formed on the entire surface including the element isolation film 2, the gate oxide films 3a and 3b, and the thermal oxide film 3c. Next, the photoresist film 50 is exposed and developed. As a result, the photoresist film 50 located on and around the gate oxide film 3a and the photoresist film 50 located on a part of the TEG formation region 1c are removed. Next, a first conductivity type impurity is introduced into the silicon wafer 1 using the photoresist film 50 as a mask. As a result, a channel impurity introduction region 8a for adjusting a threshold voltage is formed in the silicon wafer 1 located in the first element region 1a, and a resistance element 18a is formed in the silicon wafer 1 located in the TEG formation region 1c. . The planar shape of the resistive element 18a is a rectangle as shown in FIG.

  Thereafter, as shown in each drawing of FIG. 3, the photoresist film 50 is removed. Next, a photoresist film 51 is formed on the entire surface including the element isolation film 2, the gate oxide films 3a and 3b, and the thermal oxide film 3c. Next, the photoresist film 51 is exposed and developed. As a result, the photoresist film 51 located on and around the gate oxide film 3b and the photoresist film 51 located on a part of the TEG formation region 1c are removed. Next, a first conductivity type impurity is introduced into the silicon wafer 1 using the photoresist film 51 as a mask. Thereby, the channel impurity introduction region 8b for adjusting the threshold voltage is formed in the silicon wafer 1 located in the second element region 1b, and the resistance element 18b is formed in the silicon wafer 1 located in the TEG formation region 1c. . As shown in FIG. 3B, the resistive element 18b has a substantially rectangular planar shape, and is arranged next to the resistive element 18a and substantially parallel to the resistive element 18a.

  Thereafter, as shown in each drawing of FIG. 4, the photoresist film 51 is removed. Next, a polysilicon film is formed on the entire surface including the gate oxide films 3a and 3b, and the polysilicon film is selectively removed. Thereby, gate electrodes 4a and 4b are formed on the gate oxide films 3a and 3b.

  Next, the TEG formation region 1c is covered with a photoresist film (not shown), and impurities of the second conductivity type are introduced into the silicon wafer 1 using the photoresist film, the element isolation film 2, and the gate electrodes 4a and 4b as a mask. . Thereby, a low concentration impurity region (LDD) 6a is formed in the silicon wafer 1 located in the first element region 1a, and a low concentration impurity region 6b is formed in the silicon wafer 1 located in the second element region 1b. . Thereafter, the resist pattern is removed.

  Next, an insulating film is formed on the entire surface including on the gate electrodes 4a and 4b, and this insulating film is etched back. Thereby, the side walls of the gate electrodes 4a and 4b are covered with the side walls 5a and 5b. In this step, the thermal oxide film 3c is removed.

Next, the TEG formation region 1c is covered with a photoresist film (not shown), and the second conductivity is applied to the silicon wafer 1 using the photoresist film, the element isolation film 2, the gate electrodes 4a and 4b, and the sidewalls 5a and 5b as a mask. Introduce type impurities. As a result, the impurity region 7a serving as the source and drain of the first transistor is formed in the silicon wafer 1 located in the first element region 1a, and the second region in the silicon wafer 1 located in the second element region 1b. Second conductivity type impurity regions 7b to be the source and drain of the transistor are formed. Thereafter, the resist pattern is removed.
In this way, the first transistor and the second transistor are formed.

  Next, an interlayer insulating film 9 is formed on the entire surface including the first transistor, the second transistor, and the silicon wafer 1 located in the TEG formation region 1c. Next, by selectively removing the interlayer insulating film 9, a connection hole 9a located on the impurity region 7a, a connection hole 9b located on the impurity region 7b, a connection hole 9c located on the resistance element 18a, and a resistor A connection hole 9d located on the element 18b is formed. As shown in FIG. 4B, the connection holes 9c are formed on both ends of the resistance element 18a, and the connection holes 9d are formed on both ends of the resistance element 18b. Although not shown, connection holes located on the gate electrodes 4a and 4b are also formed.

  Next, a tungsten film is formed on the interlayer insulating film 9 and in each connection hole by the CVD method, and the tungsten film located on the interlayer insulating film 9 is removed by the CMP method. Thereby, tungsten plugs 10a, 10b, 10c, and 10d are embedded in the connection holes 9a, 9b, 9c, and 9d, respectively. A tungsten plug (not shown) is also embedded in the connection hole located on each of the gate electrodes 4a and 4b.

  Next, an Al alloy film is formed on the interlayer insulating film 9 by sputtering, and this Al alloy film is selectively removed. As a result, two Al alloy wirings 11a, 11b, and 11c are formed on the interlayer insulating film 9. The Al alloy wiring 11a is connected to the tungsten plug 10a, and the Al alloy wiring 11b is connected to the tungsten plug 10b. The Al alloy wiring 11c connects the tungsten plugs 10c and 10d to each other. Thereby, the resistance elements 18a and 18b are connected in parallel. In addition, by this step, Al alloy wiring (not shown) connected to the tungsten plug located on each of the gate electrodes 4a and 4b is also formed on the interlayer insulating film 9.

  In subsequent steps, the Al alloy wiring 11c is connected to the Al alloy pad 12 formed in the uppermost wiring layer. Then, an inspection terminal is connected to the Al alloy pad 12 and the combined resistance of the resistance elements 18a and 18b is measured, thereby inspecting whether or not the channel impurity introduction regions 8a and 8b are formed normally.

  That is, when the design resistance values of the resistance elements 18a and 18b are R1 and R2, the design resistance value R3 of the combined resistance of the resistance elements 18a and 18b is R1 · R2 / (R1 + R2). On the other hand, for example, when the impurity introduction into the channel impurity introduction region 8a is not performed due to the exposure failure of the photoresist film 50 or the impurity introduction process, the impurity is not introduced into the resistance element 18a. The resistance value of becomes very high. For this reason, the combined resistance of the resistive elements 18a and 18b is approximately R2. When the impurity introduction into the channel impurity introduction region 8b is not performed due to the exposure failure of the photoresist film 51 or the impurity introduction process, the combined resistance of the resistance elements 18a and 18b becomes approximately R1. Therefore, it is possible to inspect whether or not the channel impurity introduction regions 8a and 8b are formed normally by measuring the combined resistance of the resistance elements 18a and 18b.

  As described above, according to the first embodiment of the present invention, the resistance elements 18a and 18b are formed in the TEG formation region 1c when the channel impurity introduction regions 8a and 8b for adjusting the threshold voltage are formed. The resistance elements 18a and 18b are connected in parallel by tungsten plugs 10c and 10d and an Al alloy wiring 11c. For this reason, it is possible to determine whether or not the channel impurity introduction regions 8a and 8b are formed normally by connecting a test terminal to the Al alloy pad 12 and measuring the combined resistance of the resistance elements 18a and 18b. . Therefore, since it is not necessary to form an Al alloy pad for each resistance element 18a, the TEG can be reduced in size. Further, the two channel impurity introduction regions 8a and 8b can be inspected in one inspection process.

  FIG. 6 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. In the present embodiment, the first transistor and the second transistor are of opposite conductivity types.

  First, a first conductivity type (for example, P type) well 20a located in the first element region 1a and a first conductivity type well 20d located in the TEG formation region 1c are formed. Next, a second conductivity type (for example, N type) well 20b located in the second element region 1b and a second conductivity type well 20e located in the TEG formation region 1c are formed. The wells 20d and 20e are adjacent to each other.

  Next, the element isolation film 2, the gate oxide films 3a and 3b, and the thermal oxide film 3c are formed. Next, channel impurity introduction regions 8a and 8b and resistance elements 18a and 18b are formed. The resistance element 18a is located in the well 20d, and the resistance element 18b is located in the well 20e. In this embodiment, the impurity introduced into the channel impurity introduction region 8a and the resistance element 18a is the first conductivity type, and the impurity introduced into the channel impurity introduction region 8b and the resistance element 18b is the second conductivity type.

  Thereafter, gate electrodes 4a and 4b are formed. This step is the same as in the first embodiment. Next, the TEG formation region 1c and the second element region 1b are covered with a photoresist film (not shown), and the second conductivity type is applied to the silicon wafer 1 using the photoresist film, the element isolation film 2, and the gate electrode 4a as a mask. Impurities are introduced. Thereby, the low concentration impurity region 6a is formed. Thereafter, the resist pattern is removed.

  Next, the TEG formation region 1c and the first element region 1a are covered with a photoresist film (not shown), and the first conductivity type is applied to the silicon wafer 1 using the photoresist film, the element isolation film 2, and the gate electrode 4b as a mask. Impurities are introduced. Thereby, the low concentration impurity region 6b is formed. Thereafter, the resist pattern is removed.

  Next, sidewalls 5a and 5b are formed. This step is the same as in the first embodiment. Next, the TEG formation region 1c and the second element region 1b are covered with a photoresist film (not shown), and the photoresist film, the element isolation film 2, the gate electrode 4a, and the sidewalls 5a are used as masks on the silicon wafer 1. Two conductivity type impurities are introduced. Thereby, impurity region 7a is formed. Thereafter, the resist pattern is removed.

  Next, the TEG formation region 1c and the first element region 1a are covered with a photoresist film (not shown), and the photoresist film, the element isolation film 2, the gate electrode 4b, and the sidewalls 5b are used as masks on the silicon wafer 1. An impurity of one conductivity type is introduced. Thereby, impurity region 7b is formed. Thereafter, the resist pattern is removed.

Thereafter, an interlayer insulating film 9, connection holes 9a to 9d, tungsten plugs 10a to 10d, Al alloy wirings 11a to 11c, and an Al alloy pad 12 (not shown in the drawing) are formed. These forming methods are the same as those in the first embodiment.
In this embodiment, the same effect as that of the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the first and second embodiments, even when the number of types of transistors formed on the silicon wafer 1 is three or more, the resistance element is used as the TEG formation region 1c when forming the channel impurity introduction region of each transistor. The above-described effects can be obtained by forming the plurality of resistance elements in parallel.

  Further, the channel impurity introduction regions 8a and 8b may be formed before the gate oxide films 3a and 3b are formed. Further, the resistance elements 18a and 18b may be connected in parallel in the second and subsequent wiring layers.

4A and 4B are views for explaining a method for manufacturing a semiconductor device according to the first embodiment, in which FIG. 5A is a cross-sectional view and FIG. FIGS. 2A and 2B are views for explaining the next step of FIG. 1, in which FIG. 1A is a cross-sectional view and FIG. 2B is a plan view of a TEG formation region 1 c. FIGS. 3A and 3B are diagrams for explaining the next step of FIG. 2, in which FIG. 3A is a cross-sectional view, and FIG. 3B is a plan view of a TEG formation region 1c. 4A and 4B are diagrams for explaining the next step of FIG. 3, where FIG. 4A is a cross-sectional view, and FIG. 4B is a plan view of a TEG formation region 1 c. The top view of the silicon wafer 1 for demonstrating the position of the TEG formation area | region 1c. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon wafer, 1a ... 1st element area | region, 1b ... 2nd element area | region, 1c, 101c ... TEG formation area, 3a, 3b ... Gate oxide film, 3c ... Thermal oxide film, 4a, 4b ... Gate electrode, 5a, 5b ... sidewalls, 6a, 6b ... low-concentration impurity regions, 7a, 7b ... impurity regions, 8a, 8b ... channel impurity introduction regions, 9, 109 ... interlayer insulating films, 9a, 9b, 9c, 9d ... connection holes 10a, 10b, 10c, 10d, 109a, 109b ... tungsten plug, 11a, 11b, 11c, 111a, 111b ... Al alloy wiring, 12, 112a, 112b ... Al alloy pad, 18a, 18b, 118a, 118b ... resistance element 20a, 20b, 20c, 20d, 20e ... well, 50, 51 ... resist pattern, 108a, 108b ... channel region

Claims (5)

Performing a first impurity introduction process to introduce impurities into the first channel region of the semiconductor substrate and forming a first inspection resistance pattern on a scribe line of the semiconductor substrate;
Impurities are introduced into the second channel region of the semiconductor substrate by performing a second impurity introduction process at an impurity concentration different from that of the first impurity introduction process, and a second inspection resistor is applied to the scribe line. Forming a pattern;
Forming a wiring pattern for connecting the first inspection resistance pattern and the second inspection resistance pattern in parallel;
A method for manufacturing a semiconductor device comprising: Performing a first impurity introduction process to introduce an impurity into the first channel region of the semiconductor substrate and forming a first inspection resistance pattern in the TEG formation region of the semiconductor substrate;
Impurities are introduced into the second channel region of the semiconductor substrate by performing the second impurity introduction treatment with an impurity concentration different from that of the first impurity introduction treatment, and a second inspection is performed in the TEG formation region. Forming a resistance pattern;
Forming a wiring pattern for connecting the first inspection resistance pattern and the second inspection resistance pattern in parallel;
A method for manufacturing a semiconductor device comprising: The impurity introduced into the first channel region is an impurity for adjusting a threshold voltage of the first transistor,
The impurity introduced into the second channel region is an impurity for adjusting a threshold voltage of the second transistor,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second transistors have different threshold voltages.   The method of manufacturing a semiconductor device according to claim 1, wherein the first and second inspection resistance patterns are located next to each other. 2. The method of measuring a combined resistance of the first and second inspection resistance patterns by electrically connecting a test terminal to the wiring pattern after the step of forming the wiring pattern. The manufacturing method of the semiconductor device as described in any one of -4.

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