JP3779307B2 - Resistance failure evaluation device, resistance failure evaluation method, and resistance failure evaluation device manufacturing method - Google Patents

Description

  The present invention relates to a resistance failure evaluation apparatus, a resistance failure evaluation method, and a method of manufacturing a resistance failure evaluation apparatus, and in particular, detects a resistance increase failure of a resistance element or a contact mounted in the semiconductor integrated circuit device during the manufacturing process. The present invention relates to a monitoring device for the above, a method for evaluating resistance rise failure using the same, and a method for manufacturing the monitoring device.

  In recent years, in manufacturing a semiconductor integrated circuit device, miniaturization, high integration, high speed, and a large diameter of a used wafer have been advanced.

  As the semiconductor integrated circuit device to be manufactured is miniaturized and highly integrated, an impurity layer (hereinafter referred to as a source / drain impurity layer) used as a gate electrode wiring, a metal wiring, a source region and a drain region, or A disconnection failure in a contact or the like connecting a lower wiring layer and an upper wiring layer, or a short-circuit failure between wirings has become a major cause of a decrease in manufacturing yield. In addition, due to high integration or high speed, variations in characteristics of mounted transistors and resistor elements (eg, gate electrode wiring, metal wiring, source / drain impurity layers, etc.) are also a major factor in lowering the manufacturing yield. That is, in order to improve the manufacturing yield of a semiconductor integrated circuit device and realize a high-speed operation of the device, it is necessary to suppress variations in resistors (resistance elements) including variations in transistor characteristics.

  Conventionally, as a defect such as a gate electrode wiring constituting a transistor or a metal wiring on the transistor, a complete disconnection defect or a short defect between wirings has been mainly handled. Further, yield prediction of semiconductor integrated circuit devices has been performed by measuring and evaluating the amount of disconnection failure and short-circuit failure (number of defects).

  As an evaluation method for disconnection failure and short-circuit failure, the yield of a layer (wiring layer) to be evaluated is evaluated by drawing a long wiring of about several tens of centimeters to several meters to create comb-like and snake-like patterns. There exists a method (for example, refer nonpatent literature 1).

  FIG. 25 shows an example of a conventional comb-shaped (Comb) and snake-shaped (Serp) wiring pattern. In the yield evaluation method of Non-Patent Document 1, a disconnection failure is detected by measuring the resistance between the Comb pads shown in FIG. 25, and the leakage current between the Comb pad and the Serp pad shown in FIG. 25 is measured. This detects a short circuit failure. Especially for disconnection defects, very long wires are virtually routed so that the yield can be evaluated. Therefore, detection of complete disconnection failures is the target, and resistance increases (partially in certain locations) of the wires. Fluctuation) is not a detection target.

  On the other hand, as a method for evaluating resistance variation of a resistor, a method for evaluating the influence of size variation of a gate electrode wiring or the like by electrically measuring the size of a pattern to be formed has been proposed (see, for example, Non-Patent Document 2). ). Since such dimensional variations cause variations in resistors and transistor characteristics and cause a reduction in yield, it is also important to evaluate the influence of dimensional variations.

  By the way, even if the gate electrode wiring, the metal wiring, or the contact connecting the impurity layer and the wiring layer is not completely disconnected, in other words, the electrical connection within these components is maintained. Even if the sag is partially increased in resistance (that is, the resistance at a specific location in the component is increased), a failure also occurs. Such defects also cause a decrease in yield and reliability. In the present application, these components (resistive elements, contacts, etc.) are not disconnected, and the internal electrical connection is maintained, but the resistance is partially increased (as a whole, the resistive element as a whole) (The resistance also increases in resistance) is called resistance rise failure (resistance variation failure) or soft open failure. On the other hand, a failure in which the resistance element or the contact is completely disconnected is referred to as a disconnection failure or a hard open failure.

  With the recent miniaturization, higher integration, and higher speed of semiconductor integrated circuit devices, the margin of delay time has been reduced, so that the resistance rise failure that has occurred in some parts of the resistance elements such as wiring is yielded. It becomes a factor of a fall and reliability fall.

  For example, in forming a gate electrode wiring, a silicide layer is generally formed on a polysilicon electrode using a salicide process. When the silicide layer on this polysilicon electrode is disconnected, the entire gate electrode wiring is electrically connected by the underlying polysilicon electrode, so that a resistance increase failure occurs at the location where the silicide layer is disconnected, resulting in a decrease in yield. And cause a decrease in reliability.

  Similarly, a resistance increase defect (soft open defect) may occur at a part of the contact connecting the lower metal wiring or the source / drain impurity layer of the transistor and the upper wiring layer. That is, a variation in contact resistance, which is one of variation variations of resistors, that is, an increase in contact resistance, is a major factor in yield reduction and poor reliability.

On the other hand, the number of contacts used in recent semiconductor integrated circuit devices is enormous. For example, in the case of a chip having an area of about 40 mm ^{2 with} a 0.13 μm rule, the number of contacts connecting the transistor and the wiring layer is about 20 million. Therefore, even when the contact yield is evaluated using the monitor device (evaluation device), it is necessary to evaluate about 10 million contacts.

  Conventionally, in contact yield evaluation, yield evaluation has been carried out with a complete disconnection failure (hard open failure) as a detection target. Specifically, for such a yield evaluation, a resistance pattern consisting of a large-scale contact chain (the number of contacts is about 100,000) has been created, and the disconnection failure (hard open failure) of the contact chain has been evaluated. .

  FIGS. 26A and 26B show an example of a conventional contact chain resistance pattern, where FIG. 26A is a plan view, and FIG. 26B is a cross-sectional view taken along the line aa ′ in FIG. is there.

  As shown in FIGS. 26A and 26B, a plurality of lower layer wirings 3 made of a polysilicon layer or an amorphous silicon layer are formed on a silicon substrate 1 with an insulating film 2 interposed therebetween. An interlayer insulating film 4 is formed on the insulating film 2 and each lower wiring 3, and a plurality of contact electrodes (contact holes) 5 connected to each lower wiring 3 are formed on the interlayer insulating film 4. ing. On the interlayer insulating film 4, a plurality of upper metal wirings 6 connected to the contact electrodes 5 are formed. A plurality of lower layer wirings 3 and a plurality of upper layer metal wirings 6 are connected by a plurality of contact electrodes 5, thereby forming a contact chain resistance pattern as shown in FIG. In FIG. 26A, illustration of the silicon substrate 1, the insulating film 2, and the interlayer insulating film 4 is omitted. Further, instead of the insulating film 2 and the lower layer wiring 3, a transistor source / drain impurity layer is formed on the surface portion of the silicon substrate 1, and a contact electrode for connecting the source / drain impurity layer and the upper layer wiring is formed. Also good.

  The number of contacts in the contact chain resistance pattern shown in FIGS. 26A and 26B is about 100,000. If the contact failure to be evaluated is a complete disconnection (hard open), the failure can be detected when the contact chain resistance becomes infinite.

  However, even if the resistance of only one contact becomes defective and, for example, the magnitude of the resistance becomes 10 times the normal value, the magnitude of the fluctuation that the resistance increase fault has on the resistance of the entire contact chain resistance pattern. Since the (ratio) is only about 1/10000, it is difficult to detect (determine) a resistance increase failure that has occurred in one contact in the contact chain by normal measurement.

In order to solve this problem, a method of measuring and evaluating the resistance of each contact by creating a cross contact array of 256 columns and 16 rows (total number of contacts 4096) and using an 8-bit binary counter and a 256-bit decoder is proposed. (For example, see Non-Patent Document 3). When this method is used, it is possible to detect a resistance abnormality with a small resistance fluctuation, and thus it is possible to perform a yield evaluation.
Charles Weber, "Standard Defect Monitor", 1988 IEEE Proceedings on Microelectronic Test Structures, Vol.1, No.1, February 1988, p.114-119 Andrew Grenville et al., "Electrical Critical Dimension Metrology for 100-nm Linewidths and Below", In Optical Microlithography XIII, Proceedings of SPIE, Vol. 4000, 2000, p. 452-459 Takeshi Hamamoto et.al, "Measurement of Contact Resistance Distribution Using a 4k-Contacts Array", IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 1, February 1996, p.9-14

  However, the above-described evaluation of resistance increase failure (soft open failure) is more difficult than evaluation of complete disconnection failure (hard open failure). For example, in the case of disconnection failure, the electrical resistance becomes very high or the electrical resistance becomes infinite. It becomes possible to perform defect density evaluation. However, it is difficult to detect a resistance rise failure (soft open failure) even if a failure evaluation is performed by virtually routing a very long wiring. This is because the resistance increase at the soft-open portion is buried in the resistance value of the entire wiring, so that the resistance increase cannot be detected.

  In addition, the methods described in Non-Patent Document 2 and Non-Patent Document 3 have a drawback that a process TAT (turn around time) for forming a contact array or the like becomes very long. That is, in these conventional techniques, the process TAT for forming the evaluation device is almost the same as that for forming the semiconductor integrated circuit device, and therefore it takes a long time to feed back the evaluation result for process improvement. There's a problem.

  In view of the above, the present invention provides a resistance increase defect (soft) generated at a part of a gate electrode wiring or a metal wiring or at least one of a large number of contacts connecting the impurity layer and the wiring layer. An object of the present invention is to provide a resistance failure evaluation device (monitor device) that can easily detect (open failure), and to provide a method for evaluating a soft open failure using the monitor device and a method for manufacturing the monitor device.

  In order to achieve the above-mentioned object, the inventors of the present application set the length of the resistance defect evaluation pattern and the number of contacts of the contact chain resistance pattern to the resistance fluctuation component (resistance increase) generated at one position of the resistance element or one of the contacts. Component) can be detected and the number of contacts can be reduced to detect soft open defects of resistive elements and contacts, and the number of resistance defect evaluation patterns and contact chain resistance patterns that can evaluate the yield of integrated circuit devices can be A method has been conceived in which a large number of electrodes are formed on the substrate and resistance measurement and yield evaluation are performed.

  Specifically, a first resistance defect evaluation apparatus according to the present invention is an evaluation apparatus provided on a wafer for evaluating a resistance fluctuation defect of a component of an integrated circuit device, and each chip region of the wafer. For each shot area or each shot area, an evaluation pattern that can measure a resistance fluctuation component that causes a resistance fluctuation failure is provided, and the number of evaluation patterns included in one of the chip areas or one of the shot areas is It is set so that the yield can be predicted.

  A second resistance defect evaluation apparatus according to the present invention is an evaluation apparatus provided on a wafer for evaluating a resistance variation defect of a resistance element mounted on a semiconductor integrated circuit device. Each region or each shot region has a resistance failure evaluation pattern having a length that can measure a resistance variation component that causes a resistance variation failure, and the length of the resistance failure evaluation pattern is A, and is mounted on a semiconductor integrated circuit device. Assuming that the total length of the resistive elements is B, the number of resistance failure evaluation patterns included in one of the chip regions or one of the shot regions is 1/100 times or more and 10 times or less of B / A. is there.

  A third resistance defect evaluation apparatus according to the present invention is an evaluation apparatus provided on a wafer for evaluating a resistance variation defect of a resistance element mounted on a semiconductor integrated circuit device. A resistance defect evaluation pattern having a length capable of measuring a resistance variation component that causes a resistance variation defect, and a dimension and a film thickness for determining a resistance value of the resistance defect evaluation pattern in each of a plurality of blocks that divide the region or each shot region And a calibration pattern used to calibrate at least one of the resistivities, and each block is uniformly arranged in the wafer surface and in each chip area or each shot area. In each block, the calibration pattern is preferably arranged in the vicinity of the resistance defect evaluation pattern, specifically, within a range of 500 μm or less from the resistance defect evaluation pattern.

  In the third resistance defect evaluation apparatus, assuming that the length of the resistance defect evaluation pattern is A and the total length of the resistance elements mounted on the semiconductor integrated circuit device is B, one of the chip areas or one of the shot areas It is preferable that the number of resistance failure evaluation patterns included in is 1/100 times or more and 10 times or less of B / A.

  In the third resistance failure evaluation apparatus, it is preferable that an independent probing pad is provided for each of the resistance failure evaluation pattern and the calibration pattern.

  In the second or third resistance failure evaluation apparatus, the length A of the resistance failure evaluation pattern is such that there is no resistance variation failure and the first resistance value of the resistance failure evaluation pattern in which the resistance variation failure occurs in at least one location. It is preferable that the resistance variation component, which is a difference from the second resistance value of the resistance defect evaluation pattern, is set to be 2% or more with respect to the second resistance value. In the second or third resistance defect evaluation apparatus, the size (ratio) of the resistance fluctuation component is preferably 1 time (100%) or less. That is, generally, if the resistance variation of the evaluation pattern is a variation within about ± 10% of the target value, the evaluation pattern is evaluated as a non-defective product. It only has to be detected. In addition, when a complete disconnection occurs, the magnitude of the resistance variation component detected is infinitely large (∞%), so that the conventional long wiring patterns, comb-like (Comb) and snake-like (Serp) It is possible to evaluate resistance failure using the wiring pattern. Therefore, in order to distinguish from the conventional resistance failure evaluation by the long wiring pattern, in the second or third resistance failure evaluation apparatus, the magnitude (ratio) of the resistance variation component is 100 times (10000%). ) It may be the following.

  In the second or third resistance defect evaluation apparatus, the resistance element includes a MOS transistor body, a bipolar transistor body, a pn junction diode, a gate electrode wiring or source / drain impurity layer of the MOS transistor, a metal wiring, an impurity layer and a wiring layer. May be a contact for connecting the wiring layers or a via for connecting the wiring layers.

  A fourth resistance defect evaluation device according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon An evaluation apparatus provided on a wafer for evaluating a resistance variation defect of a resistance element including a formed silicide layer, and each of a plurality of blocks that divide each chip area or each shot area of the wafer, A resistance defect evaluation pattern composed of a silicon-containing layer and a silicide layer having a length capable of measuring a resistance variation component that causes a resistance variation defect due to disconnection of the silicide layer and having the same width as the resistance element, and the resistance defect evaluation pattern And a first calibration pattern comprising a silicon-containing layer having the same width as that of the resistive element, and within the wafer surface Beauty each of the blocks in the interior of each chip area or each shot area is uniformly arranged.

  A fifth resistance defect evaluation apparatus according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon An evaluation apparatus provided on a wafer for evaluating a resistance fluctuation defect of a resistance element formed of a silicide layer formed, and each of a plurality of blocks partitioning each chip area or each shot area of the wafer, A resistance defect evaluation pattern composed of a silicon-containing layer and a silicide layer having a length capable of measuring a resistance variation component that causes a resistance variation defect due to disconnection of the silicide layer and having the same width as the resistance element, and the resistance defect evaluation pattern And a second calibration pattern comprising a silicon-containing layer having a length of 5 mm and a width of at least five times the resistance element, and a wafer Each block is uniformly arranged in each of the inside of the and each chip area or each shot area.

  A sixth resistance defect evaluation device according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon An evaluation apparatus provided on a wafer for evaluating a resistance fluctuation defect of a resistance element formed of a silicide layer formed, and each of a plurality of blocks partitioning each chip area or each shot area of the wafer, A resistance defect evaluation pattern composed of a silicon-containing layer and a silicide layer having a length capable of measuring a resistance variation component that causes a resistance variation defect due to disconnection of the silicide layer and having the same width as the resistance element, and the resistance defect evaluation pattern A third calibration pattern comprising a silicon-containing layer and a silicide layer having a length of 5 mm and a width of at least five times the resistance element Have, each block in each of the internal wafer surface and each chip area or each shot area is uniformly arranged.

  A seventh resistance defect evaluation device according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon An evaluation apparatus provided on a wafer for evaluating a resistance fluctuation defect of a resistance element formed of a silicide layer formed, and each of a plurality of blocks partitioning each chip area or each shot area of the wafer, A resistance defect evaluation pattern composed of a silicon-containing layer and a silicide layer having a length capable of measuring a resistance variation component that causes a resistance variation defect due to disconnection of the silicide layer and having the same width as the resistance element, and the resistance defect evaluation pattern A first calibration pattern comprising a silicon-containing layer having the same length as the resistance element and a resistance defect evaluation pattern And a second calibration pattern comprising a silicon-containing layer having the same length as that of the resistor and having a width of at least five times that of the resistance element, and in each of the chip area or each shot area within the wafer surface. The blocks are arranged uniformly.

  In the seventh resistance failure evaluation apparatus, each block has a plurality of other resistances including a silicon-containing layer and a silicide layer having the same length as the resistance failure evaluation pattern and different widths from the resistance failure evaluation pattern. A defect evaluation pattern, and a plurality of other first calibration patterns each having a length equal to that of the first calibration pattern and including a silicon-containing layer having two or more different widths from the first calibration pattern. May be.

  In the seventh resistance failure evaluation apparatus, each block further includes a third calibration pattern having a silicon-containing layer and a silicide layer having the same length as the resistance failure evaluation pattern and a width five times or more that of the resistance element. You may do it.

  An eighth resistance defect evaluation apparatus according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon An evaluation apparatus provided on a wafer for evaluating a resistance fluctuation defect of a resistance element formed of a silicide layer formed, and each of a plurality of blocks partitioning each chip area or each shot area of the wafer, A resistance defect evaluation pattern composed of a silicon-containing layer and a silicide layer having a length capable of measuring a resistance variation component that causes a resistance variation defect due to disconnection of the silicide layer and having the same width as the resistance element, and the resistance defect evaluation pattern A first calibration pattern comprising a silicon-containing layer having the same length as that of the resistance element and a resistance defect evaluation pattern A third calibration pattern comprising a silicon-containing layer and a silicide layer having the same length as that of the semiconductor element and a width of 5 times or more of the resistance element, and each of the chip area or each shot area in the wafer plane Each block is uniformly arranged inside.

  In any one of the fourth to eighth resistance defect evaluation apparatuses, the length A of the resistance defect evaluation pattern is equal to the first resistance value and the resistance of the resistance defect evaluation pattern in which the resistance variation defect occurs in at least one place. The resistance variation component, which is the difference from the second resistance value of the resistance defect evaluation pattern in which no variation defect exists, is set to be 2% or more with respect to the second resistance value, and is mounted on the semiconductor integrated circuit device. When the total length of the resistance elements is B, the number of resistance defect evaluation patterns included in one of the chip regions or one of the shot regions is 1/10 times or more and 10 times or less of B / A. Is preferred. In any one of the fourth to eighth resistance defect evaluation apparatuses, it is preferable that the magnitude (ratio) of the resistance fluctuation component is 1 time (100%) or less. That is, generally, if the resistance variation of the evaluation pattern is a variation within about ± 10% of the target value, the evaluation pattern is evaluated as a non-defective product. It only has to be detected. In addition, when a complete disconnection occurs, the magnitude of the resistance variation component detected is infinitely large (∞%), so that the conventional long wiring patterns, comb-like (Comb) and snake-like (Serp) It is possible to evaluate resistance failure using the wiring pattern. Therefore, in order to distinguish from the conventional resistance failure evaluation by the long wiring pattern, in any one of the fourth to eighth resistance failure evaluation apparatuses, the magnitude (ratio) of the resistance fluctuation component is It may be 100 times (10000%) or less.

  In the fourth to eighth resistance defect evaluation apparatuses, each calibration pattern in each block may be arranged in the vicinity of the resistance defect evaluation pattern, specifically within a range of 500 μm or less from the resistance defect evaluation pattern. preferable.

A first resistance defect evaluation method according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, a silicon-containing layer, and a silicon-containing layer thereon An evaluation method for evaluating a resistance fluctuation failure of a resistance element including a formed silicide layer, using a seventh resistance failure evaluation apparatus according to the present invention, a resistance failure evaluation pattern in each block, a first A first step of measuring respective resistance values of the calibration pattern and the second calibration pattern at a plurality of locations in the wafer surface and in each chip region or each shot region, and the width of the second calibration pattern The design value is DR, and the resistance values of the first calibration pattern and the second calibration pattern measured in the first step are R1 and R2, respectively. Electrical conversion dimensions ECD of kicking resistance defect test pattern, ECD = DR × R2 / R1
Plotting on the X-axis and Y-axis the second step calculated according to the above, the electrical conversion dimension ECD calculated in the second step, and the resistance value R of the resistance failure evaluation pattern measured in the first step, respectively. Or the sheet resistance value Rs of the resistance failure evaluation pattern in each block, where A is the length of the resistance failure evaluation pattern,
Rs = R × ECD / A
A third step of creating a graph by plotting the calculated sheet resistance value Rs and the electrical conversion dimension ECD calculated in the second step on the Y axis and the X axis, respectively, Based on the graph created in the process, the resistance fluctuation R of the resistance defect evaluation pattern is detected by extracting the points where the resistance value R or the sheet resistance value Rs of the resistance defect evaluation pattern is discretely increased. The process is provided.

  In the first resistance failure evaluation method, each block has a plurality of other layers including a silicon-containing layer and a silicide layer having the same length as the resistance failure evaluation pattern and different widths from the resistance failure evaluation pattern. There are further provided a resistance failure evaluation pattern and a plurality of other first calibration patterns made of a silicon-containing layer having two or more different widths having the same length as the first calibration pattern and different from the first calibration pattern. In the first step, each resistance value of each other resistance failure evaluation pattern and each other first calibration pattern in each block is set in the wafer surface and each chip area or each shot area. The process of measuring in the several location in may be included.

A second resistance failure evaluation method according to the present invention includes at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, a silicon-containing layer, and a silicon-containing layer thereon. An evaluation method for evaluating a resistance fluctuation failure of a resistance element including a formed silicide layer, using a fourth resistance failure evaluation apparatus according to the present invention, and a resistance failure evaluation pattern in each block and a first A first step of measuring each resistance value of the calibration pattern at a plurality of locations in the wafer surface and each chip region or each shot region, and resistance failure evaluation in each block measured in the first step The resistance values of the pattern and the first calibration pattern are RR and r1, respectively, and all of the first calibration values in the wafer surface measured in the first step are used. The average value of the resistance value of the turn as r1 (Ave), the correction value RR of the resistance value RR of the resistance defect test pattern 'a (1),
RR ′ (1) = RR × r1 (Ave) / r1
And a third step of creating a distribution map of the correction value RR ′ (1) calculated in the second step in the wafer surface, in each chip region, or in each shot region, Based on the distribution map created in the third step, a point where the correction value RR ′ (1) is discretely extracted is extracted to detect a resistance fluctuation failure in the resistance failure evaluation pattern. And.

A third resistance failure evaluation method according to the present invention includes at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon. An evaluation method for evaluating a resistance variation failure of a resistance element including a formed silicide layer, using a sixth resistance failure evaluation apparatus according to the present invention, and a resistance failure evaluation pattern in each block and a third A first step of measuring each resistance value of the calibration pattern at a plurality of locations in the wafer surface and each chip region or each shot region, and resistance failure evaluation in each block measured in the first step The resistance values of the pattern and the third calibration pattern are RR and r3, and all the third calibration values in the wafer plane measured in the first step are used. The average value of the resistance value of the turn as r3 (Ave), the correction value RR of the resistance value RR of the resistance defect test pattern '(2),
RR ′ (2) = RR × r3 (Ave) / r3
And a third step of creating a distribution map of the correction value RR ′ (2) calculated in the second step in the wafer surface, in each chip region or in each shot region, Based on the distribution map created in the third step, a point in which the correction value RR ′ (2) is discretely increased is extracted, thereby detecting a resistance fluctuation failure in the resistance failure evaluation pattern. And.

A fourth resistance defect evaluation method according to the present invention is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and a silicon-containing layer and a silicon-containing layer thereon An evaluation method for evaluating a resistance fluctuation failure of a resistance element including a formed silicide layer, using the eighth resistance failure evaluation apparatus according to the present invention, a resistance failure evaluation pattern in each block, a first The first step of measuring the resistance values of the calibration pattern and the third calibration pattern at a plurality of locations in the wafer surface and each chip region or each shot region, and the first step were measured. The resistance values of the resistance failure evaluation pattern, the first calibration pattern, and the third calibration pattern in each block are RR, r1, and r3, respectively, and the first step The average value of the measured resistance values of all the first calibration patterns and the resistance values of all the third calibration patterns in the wafer surface is defined as r1 (Ave) and r3 (Ave), and the resistance defect evaluation pattern The correction value RR ′ (1), the correction value RR ′ (2) and the correction value RR ′ (3) of the resistance value RR are respectively
RR ′ (1) = RR × r1 (Ave) / r1
RR ′ (2) = RR × r3 (Ave) / r3
RR ′ (3) = RR × r1 (Ave) × r3 (Ave) / (r1 × r3)
In the wafer surface or each chip area of the correction value RR ′ (1), correction value RR ′ (2) and correction value RR ′ (3) calculated in the second step And a correction value RR ′ (1), a correction value RR ′ (2), and a correction based on the third step of creating a distribution map in each shot area and each distribution map created in the third step And a fourth step of detecting a resistance fluctuation defect of the resistance defect evaluation pattern by extracting a point where the value RR ′ (3) is discretely increased.

  In the second or fourth resistance failure evaluation method, in the second step, instead of the average value r1 (Ave), all of the chip regions measured in the first step or one of the shot regions are all measured. Using the average value r1shot (Ave) of the resistance values of the first calibration pattern or the average value r1block (Ave) of the resistance values of all the first calibration patterns in one of the blocks measured in the first step Also good.

  In the third or fourth resistance failure evaluation method, in the second step, instead of the average value r3 (Ave), all the chip regions or one of the shot regions measured in the first step are measured. Using the average value r3shot (Ave) of the resistance values of the third calibration pattern or the average value r3block (Ave) of the resistance values of all the third calibration patterns in one of the blocks measured in the first step Also good.

  The manufacturing method of the first resistance defect evaluation apparatus according to the present invention is any one of the third to eighth resistance defect evaluation apparatuses, and the resistance element to be evaluated is included in the semiconductor integrated circuit device. A gate electrode wiring constituting a MOS transistor to be mounted; a step of forming a first insulating film on a substrate made of a wafer; a step of depositing a silicon-containing layer on the first insulating film; Etching the silicon-containing layer using the mask pattern of the step, patterning the silicon-containing layer into the respective shapes of the resistance defect evaluation pattern and the calibration pattern, and the side surface of the patterned silicon-containing layer After forming the sidewall, a step of depositing a second insulating film for preventing silicidation, and a second mask pattern is used to form the second insulating film. Etching is performed to set a silicidation region from which the second insulating film is removed and a silicidation prevention region from which the second insulating film is left, and silicon in the silicidation region using a salicide process. Forming a gate electrode wiring by forming a silicide layer on the containing layer.

  The manufacturing method of the second resistance defect evaluation apparatus according to the present invention is any one of the third to eighth resistance defect evaluation apparatuses, and the resistance element to be evaluated is included in the semiconductor integrated circuit device. A source / drain impurity layer constituting a MOS transistor to be mounted, the step of forming a first insulating film on a semiconductor substrate made of a wafer, and the first insulating film using the first mask pattern Etching the semiconductor substrate using the patterned first insulating film as a mask, and a step of patterning the first insulating film into the respective shapes of the resistance defect evaluation pattern and the calibration pattern. Forming a trench, embedding a second insulating film in the trench, planarizing the surface of the second insulating film by CMP, and then forming a first insulating film. Forming a trench isolation by removing the film, and forming an impurity layer by introducing an impurity into the exposed surface portion of the semiconductor substrate where the trench isolation is not formed, and then siliciding the semiconductor substrate. A step of depositing a third insulating film for preventing, and a silicidation region where the third insulating film is removed by etching the third insulating film using the second mask pattern; A step of setting a silicidation prevention region in which the third insulating film remains, and a step of forming a source / drain impurity layer by forming a silicide layer on the impurity layer of the silicidation region using a salicide process And has.

  A contact defect evaluation apparatus according to the present invention is an evaluation apparatus provided on a wafer for evaluating a resistance variation defect of a contact mounted on a semiconductor integrated circuit device, and is provided for each chip region or each shot of a wafer. Each region has a contact chain resistance pattern with the number of contacts that can measure the resistance variation component that causes resistance variation failure, where n is the number of contacts in the contact chain resistance pattern, and the total number of contacts mounted on the semiconductor integrated circuit device is Assuming N, the number of contact chain resistance patterns included in one of the chip regions or one of the shot regions is not less than 1/10 times N / n and not more than 10 times.

  In the contact failure evaluation apparatus of the present invention, the contact chain resistance pattern is arranged in each of a plurality of blocks that divide each chip region or each shot region of the wafer, and the contact chain resistance pattern is located near the contact chain resistance pattern in each block. The inter-contact pattern length L1, which is used to calibrate the resistance value of the base pattern that determines the resistance value of the chain resistance pattern and is equal to the inter-contact pattern length L to be evaluated, and the inter-contact pattern length longer than the inter-contact pattern length L1 Each block has a plurality of first calibration patterns each having a length L2 and an inter-contact pattern length L3 longer than the inter-contact pattern length L2, and each block is within the wafer surface and inside each chip area or each shot area. Evenly arranged It is preferred.

  In the contact failure evaluation apparatus of the present invention, the contact chain resistance pattern is arranged in each of a plurality of blocks that divide each chip area or each shot area of the wafer, and is evaluated in the vicinity of the contact chain resistance pattern in each block. A plurality of second calibration patterns each having a contact diameter d1 smaller than the target contact diameter d, a contact diameter d2 equivalent to the contact diameter d, and a contact diameter d3 larger than the contact diameter d; It is preferable that the blocks are arranged uniformly in each chip area or each shot area.

  In the contact failure evaluation apparatus of the present invention, it is preferable that each calibration pattern in each block is disposed in the vicinity of the contact chain resistance pattern, specifically within a range of 500 μm or less from the contact chain resistance pattern.

  In the contact failure evaluation apparatus according to the present invention, the number n of contacts of the contact chain resistance pattern includes the first resistance value of the contact chain resistance pattern in which the resistance variation failure occurs in at least one place and the contact chain resistance in which the resistance variation failure does not exist. It is preferable that the resistance fluctuation component, which is a difference from the second resistance value of the pattern, is set to be 1% or more with respect to the first resistance value. In the contact failure evaluation apparatus of the present invention, it is preferable that the magnitude (ratio) of the resistance variation component is 1 time (100%) or less. That is, generally, if the resistance variation of the evaluation pattern is a variation within about ± 10% of the target value, the evaluation pattern is evaluated as a non-defective product. It only has to be detected. In addition, when a complete disconnection occurs, the magnitude of the resistance fluctuation component detected is infinitely large (∞%). Therefore, resistance failure evaluation should be performed using a conventional large-scale contact chain resistance pattern. Can do. Therefore, in order to distinguish from the conventional resistance failure evaluation by a large-scale contact chain resistance pattern, in the contact failure evaluation apparatus of the present invention, the magnitude (ratio) of the resistance variation component is 100 times (10000). %) Or less.

  In the contact failure evaluation apparatus of the present invention, the contact may be a contact electrode formed by embedding a refractory metal film or a metal film in the contact hole.

  In the contact failure evaluation apparatus of the present invention, the base pattern of the contact may be a gate electrode wiring layer, a source / drain impurity layer, or a lower metal wiring layer.

A first contact failure evaluation method according to the present invention is an evaluation method for evaluating a resistance variation failure of a contact mounted on a semiconductor integrated circuit device, and is a contact failure evaluation device according to the present invention having a calibration pattern. Using the contact failure evaluation device, measure the resistance values of the contact chain resistance pattern and the first calibration pattern in each block at a plurality of locations in the wafer surface and in each chip area or each shot area. And the resistance value of each first calibration pattern in each block measured in the first step as r1, r2, and r3 for the inter-contact pattern lengths L1, L2, and L3, respectively. The lengths L1, L2, and L3 and the resistance values r1, r2, and r3 of the first calibration patterns are respectively represented by the X axis and the Y axis. A second step of calculating a resistance value rc per contact constituting the contact chain resistance pattern in the block from the value of the Y intercept of the generated graph; The resistance value rc of each contact and the resistance value Rc of the contact chain resistance calculated in the second step are set to Rc, where Rc is the resistance value of the contact chain resistance pattern in each block measured in the above step. And plotting on the Y-axis, or using the resistance value rc per contact and the contact resistance value ρc per unit area calculated in the second step, Equivalent contact diameter d,
d = (ρc / (π × rc)) ^1/2
And the calculated electrical converted contact diameter d or its reciprocal and the resistance value Rc of the contact chain resistance pattern, respectively, using the resistance value of the contact chain resistance pattern in each block measured in the first step as Rc. Based on the third step of creating a graph by plotting on the X-axis and the Y-axis and the graph created in the third step, the points where the resistance value Rc of the contact chain resistance pattern rose discretely are extracted. By doing so, there is provided a fourth step of detecting a resistance variation defect of the contact chain resistance pattern.

A second contact failure evaluation method according to the present invention is an evaluation method for evaluating a resistance variation failure of a contact mounted on a semiconductor integrated circuit device, and is a contact failure evaluation device according to the present invention. The contact chain resistance pattern in each block and each resistance value of each first calibration pattern at a plurality of locations in the wafer surface and in each chip area or in each shot area. The first process to be measured and the resistance value of each first calibration pattern in each block measured in the first process as r1, r2, and r3 for the inter-contact pattern lengths L1, L2, and L3, respectively, between the contacts The pattern lengths L1, L2, and L3 and the resistance values r1, r2, and r3 of the first calibration patterns are respectively set to the X axis and A second step of creating a graph by plotting on the Y-axis, and calculating a resistance value Ru per unit length of the base pattern of the contact chain resistance pattern in the block from the slope value of the created graph, The resistance value Ru of the contact chain resistance pattern in each block measured in the step is Rc, and the resistance value Ru per unit length of the ground pattern of all the contact chain resistance patterns in the wafer surface calculated in the second step The average value is Ru (Ave), and the correction value Rc ′ of the resistance value Rc of the contact chain resistance pattern is
Rc ′ = Rc × Ru (Ave) / Ru
A fourth step of creating a distribution map of the correction value Rc ′ calculated in the third step in the wafer surface or in each chip region or in each shot region; And a fifth step of detecting a resistance variation defect of the contact chain resistance pattern by extracting a point where the correction value Rc ′ is discretely increased based on the distribution diagram created in the step.

  In the second contact failure evaluation method, in the third step, all contact chain resistances in one of the chip regions or one of the shot regions calculated in the second step are substituted for the average value Ru (Ave). The average value Rushot (Ave) of the resistance value Ru per unit length of the pattern base pattern, or the resistance value per unit length of the base pattern of all contact chain resistance patterns in one of the blocks calculated in the second step An average value Rublock (Ave) of Ru may be used.

  The manufacturing method of the 1st contact defect evaluation apparatus which concerns on this invention is a contact defect evaluation apparatus of this invention, Comprising: It is a manufacturing method of the contact defect evaluation apparatus which has a pattern for a calibration. Specifically, a step of forming respective base patterns of a contact chain resistance pattern and a calibration pattern on a substrate made of a wafer, a step of forming an insulating film on the substrate on which the base pattern is formed, and an insulating film In addition, a step of forming a plurality of holes reaching each base pattern, a step of embedding a conductor film in each hole to form a plurality of contacts, and a step of forming an upper layer wiring on each contact and on the insulating film And has.

  The manufacturing method of the 2nd contact failure evaluation apparatus concerning the present invention is a manufacturing method of the contact failure evaluation apparatus of the present invention which has a calibration pattern. Specifically, the step of forming an insulating film on a substrate made of a wafer, the step of forming a first conductive film on the insulating film, and the first conductor using a first mask pattern Etching the film to form a base pattern of each of the contact chain resistance pattern and the calibration pattern; and forming an interlayer insulating film on the substrate on which the base pattern is formed; Etching the interlayer insulating film using a second mask pattern to form a plurality of holes reaching the underlying patterns; and embedding a second conductor film in each of the holes; Removing the second conductor film outside each hole by CMP while leaving the second conductor film in each hole, and forming a plurality of contacts; Forming a third conductor film on each of the contacts and on the interlayer insulating film; and etching the third conductor film using a third mask pattern to form an upper layer wiring Forming a step.

  According to the present invention, for each chip area or each shot area of the wafer serving as an evaluation apparatus, an evaluation pattern capable of measuring a resistance variation component that causes a resistance variation failure of a component of the integrated circuit device is provided, The number of evaluation patterns included in one of the chip areas or one of the shot areas is set so that the yield of the integrated circuit device can be predicted. Therefore, it is possible to accurately evaluate the resistance rise failure (soft open failure) in the components of the integrated circuit device, and to measure the resistance for each evaluation pattern in each chip area or each shot area, By detecting the number of soft open defects based on this, it is possible to evaluate the yield of the integrated circuit device. That is, the influence of soft open defects on the yield of integrated circuit devices to be manufactured can be evaluated.

  Specifically, according to the resistance defect evaluation apparatus, the resistance defect evaluation method using the evaluation apparatus, and the manufacturing method of the evaluation apparatus according to the present invention, a resistance variation component that causes a resistance variation defect is measured. Since it has a possible length, it is possible to accurately evaluate a resistance rise failure (soft open failure) in a part of the resistance element. In addition, since the resistance defect evaluation patterns that can evaluate the yield of the resistance elements are arranged in each chip area or each shot area, resistance measurement for each resistance defect evaluation pattern in each chip area or each shot area is performed. Then, by detecting the number of soft open defects based on the measurement result, the yield of the resistance element can be evaluated. Therefore, it is possible to evaluate the influence of the soft open defect on the yield of the manufactured semiconductor integrated circuit device.

  In particular, with regard to disconnection of a silicide layer formed by a salicide process on a polysilicon film or a source / drain impurity layer which is a gate electrode wiring in a MOS (metal oxide semiconductor) transistor, impurities are doped below the silicide layer. In addition, since the polysilicon film or the impurity layer exists, even if the silicide layer is disconnected, it is not completely disconnected (hard open). That is, since the polysilicon film or the impurity layer has a predetermined resistance value, if the silicide layer is disconnected, the entire gate electrode wiring or the entire source / drain impurity layer has a partial resistance increase failure (soft open failure) ) Is generated. Since such a soft open defect is accurately detected by the resistance defect evaluation apparatus and the resistance defect evaluation method using the evaluation apparatus according to the present invention, the yield evaluation considering the soft open defect is performed based on the detection result. Is possible.

  Similarly, according to the contact failure evaluation apparatus, the contact failure evaluation method using the evaluation apparatus, and the manufacturing method of the evaluation apparatus according to the present invention, the contact chain resistance pattern can measure the resistance variation component that causes the resistance variation failure. Since it has the number of contacts, it is possible to accurately evaluate a soft open defect in a part of the contact, for example, one contact among many contacts. In addition, each contact area in each chip area or each shot area has a number of contact chain resistance patterns arranged in each chip area or each shot area so that the yield of all contacts mounted on the integrated circuit device can be evaluated. By measuring the resistance of the chain resistance pattern and detecting the number of soft open defects based on the measurement result, the contact yield can be evaluated. Therefore, it is possible to evaluate the influence of the soft open defect on the yield of the manufactured semiconductor integrated circuit device.

  Further, according to the manufacturing method of the resistance failure evaluation device or the contact failure evaluation device according to the present invention, since the evaluation device for soft open failure can be manufactured with a very short process TAT, the evaluation result can be immediately fed back. A very large effect is obtained that the time required for process improvement can be shortened.

  By the way, in the resistance failure evaluation apparatus according to the present invention, the number of resistance failure evaluation patterns corresponding to the total length of all the resistance elements mounted on the semiconductor integrated circuit device is provided, and each resistance failure evaluation pattern is provided. However, it has a length capable of measuring a resistance variation component that causes a soft open failure. Here, in the resistance failure evaluation method according to the present invention, since the measurement evaluation is performed for each of these resistance failure evaluation patterns, the number of measurement points becomes enormous. For example, in the embodiment described later, 91800 points are measured per wafer. In the future, as the density of semiconductor integrated circuit devices subject to yield evaluation continues to increase, the number of resistance defect evaluation patterns that need to be measured further increases due to the need to capture weak resistance fluctuations in resistive elements. I think that. On the other hand, it is expected that the measurement evaluation time will be further shortened by the advancement of the measurement technique in the future, and therefore, it is considered that an increase in the number of measurement points does not cause an excessive increase in the measurement evaluation time. Therefore, the resistance failure evaluation method using the resistance failure evaluation apparatus according to the present invention is considered to be the simplest and most effective method in the future.

  Similarly, in the contact failure evaluation apparatus according to the present invention, the number of contact chain resistance patterns corresponding to the total number of contacts of the semiconductor integrated circuit device is provided, and each contact chain resistance pattern is a soft open failure. Has the number of contacts that can measure resistance fluctuation components. Here, in the contact failure evaluation method according to the present invention, since the measurement evaluation is performed for each of these contact chain resistance patterns, the number of measurement points becomes enormous. In the future, in the situation where the density of semiconductor integrated circuit devices subject to yield evaluation is increasing, it will be necessary to measure in order to capture weak resistance fluctuations at some contacts among a very large number of contacts. It is considered that the number of resistance defect evaluation patterns further increases. On the other hand, it is expected that the measurement evaluation time will be further shortened by the advancement of the measurement technique in the future, and therefore, it is considered that an increase in the number of measurement points does not cause an excessive increase in the measurement evaluation time. Therefore, the contact failure evaluation method using the contact failure evaluation apparatus according to the present invention is considered to be the simplest and most effective method in the future.

  As described above, the effect of the present invention has been described by taking the case of the disconnection of the silicide layer on the polysilicon film serving as the gate electrode wiring or the silicon layer serving as the source / drain impurity layer as an example. However, the soft open defect detection method or the yield evaluation method using the detection result of the present invention is based on the soft open defect evaluation of metal wiring made of aluminum or copper, the contact connecting the impurity layer of the transistor and the wiring layer. The present invention can also be applied to the soft open defect evaluation of the above, or the soft open defect evaluation of via portions connecting metal wirings, and the effect obtained thereby is also very large.

(First embodiment)
Hereinafter, a resistance defect evaluation apparatus (resistance resistance monitor apparatus) according to the first embodiment of the present invention, specifically, a wafer (evaluation) for evaluating resistance variation defects of resistance elements mounted on a semiconductor integrated circuit device. An evaluation apparatus provided on a wafer for use will be described with reference to the drawings.

  FIG. 1A is a plan view of one chip area (or one shot area described later) of the resistance defect monitoring device of this embodiment. As shown in FIG. 1A, a resistor having a size (length or width) in a chip region 101 (hereinafter simply referred to as a chip 101) capable of detecting a resistance variation component that causes a soft open defect. A certain number of resistance defect evaluation patterns 102 are uniformly arranged as many as the yield evaluation of the semiconductor integrated circuit device is possible. In other words, the length of the resistance defect evaluation pattern 102 of this embodiment is set to be smaller than a predetermined length determined by the resistance value measurement accuracy, as will be described later. Here, the resistance defect evaluation pattern 102 is substantially the same structure as the resistance element mounted on the semiconductor integrated circuit device (in the first to tenth embodiments, it means the material configuration, film thickness, etc. Unless otherwise specified, width and length shall not be included in the structure). Specifically, in this embodiment, 1800 resistors having a length of 280 μm and a width of 0.1 μm, which are silicided gate electrode wirings, are arranged in the chip 101 as the resistance defect evaluation pattern 102.

  FIG. 1B shows a state in which the resistance defect monitoring device (provided in one chip region) of the present embodiment shown in FIG. 1A is uniformly arranged in the wafer surface. As shown in FIG. 1B, in this embodiment, chips 101 are arranged at 51 locations on the main surface of the wafer 100. Therefore, 1800 × 51 = 91800 resistance defect evaluation patterns 102 are arranged per wafer.

  FIG. 1C and FIG. 1D each show an example of the resistance failure evaluation pattern 102. As shown in FIG. 1C, the resistance defect evaluation pattern 102 includes, for example, a line portion 102a having a length A that is substantially a resistor, and two pieces connected to both ends of the line portion 102a. You may comprise from the terminal 102b. Further, as shown in FIG. 1D, the resistance failure evaluation pattern 102 is connected to, for example, a line portion 102a having a length A that is substantially a resistor and two ends of the line portion 102a. You may be comprised from the four terminals 102b. In the following description, the length A of the line portion 102a that substantially becomes a resistor is the length of the resistance defect evaluation pattern 102 unless otherwise specified.

  In the present embodiment, a two-terminal resistor shown in FIG. 1C is used as the resistance defect evaluation pattern 102. However, instead of this, a four-terminal resistor shown in FIG. 1D may be used, or a contact resistor, a via resistor, or the like may be used as another resistor. Further, a MOS transistor or the like may be used as the resistance failure evaluation pattern 102.

Here, a method for setting the length A of the resistance defect evaluation pattern 102 shown in FIG. 1C will be described with reference to FIGS. 1E and 1F. As shown in FIG. 1E, the resistance value of the resistance failure evaluation pattern 102 of length A in which no resistance failure has occurred (normal) is RA, and as shown in FIG. When the resistance value of the resistance defect evaluation pattern 102 of length A occurring at least at one location is RB, the length A of the resistance defect evaluation pattern 102 is
(RB-RA) / RA × 100 ≧ 2%
It is set to satisfy. Specifically, in this embodiment, A = 280 μm. The reason for this will be described later with reference to FIGS.

  Next, the number of resistance defect evaluation patterns 102 that need to be provided in the chip 101 shown in FIG. 1A will be described with reference to FIG. FIG. 1G is a schematic plan view of the semiconductor integrated circuit device 110 on which the resistance element 111 to be evaluated is mounted. Here, the semiconductor integrated circuit device 110 is provided in each chip region or each shot region of a product wafer, for example. In addition, for example, when a gate electrode wiring of a MOS transistor is selected as the resistance element 111 to be evaluated, the number of resistance defect evaluation patterns 102 on the chip 101 is set to all the gates mounted on the semiconductor integrated circuit device 110. It is necessary to set the number corresponding to the total length of the electrode wiring pattern.

  In the present embodiment, the gate electrode wiring used in the semiconductor integrated circuit device includes all of a part that functions substantially as a gate electrode of a MOS transistor, a part that functions as a wiring that connects the transistors, and the like. Shall be. In addition, in the gate electrode wiring used in an actual semiconductor integrated circuit device, a part having the smallest design rule wiring width and a part having a larger wiring width are mixed. In the embodiment, only the gate electrode wiring having the minimum design rule wiring width which is used in most areas in the integrated circuit and is most likely to cause defects is evaluated, and the total length (total distance) is B. And

  One of the features of this embodiment is that the resistance defect evaluation pattern 102 must be inserted into the chip 101 when the length of the resistance defect evaluation pattern 102 is A and the total distance of the resistance elements to be evaluated in the integrated circuit device is B. The number of resistance defect evaluation patterns 102 is set to a range of 1/100 times or more and 10 times or less the value calculated by B / A. Specifically, in this embodiment, 1800 resistance defect evaluation patterns 102 within the above-described range are arranged inside one chip 101. However, in yield evaluation considering soft open defects, the number of resistance defect evaluation patterns 102 that need to be inserted into the chip 101 is 1/10 times or more and 10 times or less the value calculated by B / A. It is more preferable to set in the range. The reason for this will be described later with reference to FIG.

  Next, with reference to FIGS. 2A to 2F, with respect to how to set the length A of the resistance defect evaluation pattern 102 in this embodiment, the soft open caused by the disconnection defect of the silicide layer on the gate electrode wiring The case where a defect is evaluated will be described in detail as an example.

  FIG. 2A is a plan view of a normal resistance failure evaluation pattern in which the silicide layer is not disconnected. FIG. 2B is a plan view of a resistance failure evaluation pattern in which the silicide layer is disconnected at one location. 2C is a cross-sectional view taken along the line aa ′ in FIG. 2A, and FIG. 2D is a cross-sectional view taken along the line bb ′ in FIG. 2B. .

  As shown in FIG. 2B, the resistance defect evaluation pattern 102 is composed of a lower polysilicon layer 104 and an upper silicide layer 105. Further, as shown in FIGS. 2C and 2D, even if the disconnection 103 occurs in the silicide layer 105, the electrical connection is maintained by the lower polysilicon layer 104, so that the resistance defect evaluation pattern 102 as a whole is maintained. As a result, a partial resistance increase occurs without disconnection.

Here, whether or not the above-described 280 μm set as the value of the length A of the resistance defect evaluation pattern 102 is appropriate is determined as follows. The resistance element to be evaluated is a gate electrode wiring having a width of 0.1 μm. Also, the resistance increase value (measured value) r due to the disconnection of the silicide layer on the 0.1 μm wide polysilicon electrode is 2 kΩ. On the other hand, the resistance value RA of a normal gate electrode wiring (with no silicide layer breakage) having a pattern length A of 280 μm and a width of 0.1 μm is 16 kΩ. Therefore, the resistance value RB of the gate electrode wiring in which the pattern length A is 280 μm, the width is 0.1 μm, and one silicide layer breakage occurs is 18 kΩ. Therefore, the magnitude (ratio) of the resistance fluctuation component is
(RB-RA) /RA×100=12.5%
Since this is a value equal to or greater than the aforementioned threshold value (2%), it can be seen that it is appropriate to set the length A of the resistance defect evaluation pattern to 280 μm.

  FIG. 2E is a table showing the relationship between the length A of the resistance defect evaluation pattern, the normal gate electrode wiring resistance value RA, and the gate electrode wiring resistance value RB where one defect occurs. FIG. 2F is a graph showing the dependence of (RB−RA) / RA × 100 on the length A of the resistance defect evaluation pattern.

  As shown in FIGS. 2 (e) and 2 (f), as the length A of the resistance failure evaluation pattern increases, a failure occurring at one location in the pattern can be detected using the measurement result of the resistance value. It becomes difficult. Here, (RB−RA) / RA × 100 ≧ 2%, which is set as a measurable range of the resistance variation component that becomes a defect in the present embodiment, is satisfied because the length A of the resistance defect evaluation pattern is 1750 μm or less. This is the case. That is, when A = 1750 μm, as shown in FIG. 2E, RA = 100Ω and RB = 102Ω, so the difference between these resistance measurement values (more precisely, the ratio of the difference to RA, that is, the resistance It is necessary to accurately detect 2% which is a fluctuation component. Therefore, when the measurement accuracy of the resistance value is about 2%, the soft open defect cannot be accurately detected unless the resistance fluctuation component is 2% or more. On the other hand, in this embodiment, since the length A of the resistance defect evaluation pattern is set to 280 μm, the resistance variation component has values of 12.5% and 10% or more. It becomes easy.

  Next, a method for setting the required number of resistance defect evaluation patterns within one chip in this embodiment will be described in detail with reference to FIG. 3 by taking as an example the disconnection defect of the silicide layer on the gate electrode wiring.

  For example, in the semiconductor integrated circuit device 110 as shown in FIG. 1G, it is assumed that a gate electrode wiring is mounted as the resistance element 111 to be evaluated. In recent semiconductor integrated circuit devices (ULSI), the total length (total distance) of gate electrode wirings used for MOS transistors is on the order of meters (m). Here, it is assumed that the total wiring length B of the gate electrode wiring (gate electrode wiring manufactured by the minimum rule) of the semiconductor integrated circuit device 110 evaluated in this embodiment is 1 m. In this case, the required number of resistance defect evaluation patterns in one chip is set as follows. First, by dividing the total wiring length B of the semiconductor integrated circuit device by the resistance failure evaluation pattern length A (= 280 μm), a value of 3571 is calculated as the value of B / A. As described above, in the present embodiment, the number of resistance defect evaluation patterns in the range of 1/100 times (36) or more and 10 times (35710) or less of 3571 which is the value of B / A is included in one chip. Insert into. Specifically, in the present embodiment, about 1571 resistance defect evaluation patterns, which are approximately half of 3571, are inserted into one chip.

FIG. 3 shows the total wiring length L (total distance of gate electrode wiring mounted on a semiconductor integrated circuit device or total distance of resistance failure evaluation pattern in a resistance failure monitoring device) and the total pattern yield (semiconductor integrated circuit device or resistance). It is a figure which shows the relationship with the yield (unit:%) of 1 chip area | region of a defect monitoring apparatus. In FIG. 3, the total wiring length L is represented on the horizontal axis, and the total pattern yield Y is represented on the vertical axis. Here, if the total wiring length in one chip is L, the number of resistance defect evaluation patterns in one chip is N, and the length of the resistance defect evaluation pattern is A, N = L / A is established. Further, assuming that the defect occurrence rate of the resistance defect evaluation pattern having a length of 280 μm is λ, the yield Y of the total pattern in the resistance defect monitoring device in one chip region is
Y = EXP (−λ × N)
Holds. Using this formula for calculating the total pattern yield Y, the total pattern yield Y was calculated for various total wiring lengths L when the defect occurrence rate λ of the resistance defect evaluation pattern having a length of 280 μm was 100 ppm. This is shown in FIG.

As shown in FIG. 3, when the total wiring length L of the semiconductor integrated circuit device as a product is 1 m (1.0 × 10 ⁶ μm), it can be seen that the yield of the product is about 70%. Therefore, when the total wiring length L of the resistance defect monitoring device is 1 m as in the product, the same yield can be obtained, and the product yield can be evaluated using the result. In this case, as described above, the number N of resistance defect evaluation patterns needs to be 3571. On the other hand, in this embodiment, N = 1800 is set. In this case, as shown in FIG. 3, the total wiring length L of the resistance defect monitoring device is 280 μm × 1800 = 0.504 m. The pattern yield Y is about 84%. This value is sufficient to perform product yield evaluation (yield prediction) using a yield conversion formula.

  That is, when the length of the resistance defect evaluation pattern is A and the total distance of the resistance elements to be evaluated in the integrated circuit device is B, the number of resistance defect evaluation patterns that need to be inserted in one chip is represented by B When the value is set to a range of 1/100 times or more and 10 times or less of the value calculated by / A, the product yield can be evaluated based on the yield obtained for the resistance defect monitoring device.

  Further, when the number of resistance defect evaluation patterns that need to be inserted in one chip is set to a range of 1/10 times or more and 10 times or less the value calculated by B / A, the resistance failure monitor device can be obtained. Therefore, the product yield can be more accurately evaluated based on the yield obtained. In other words, when the number of resistance defect evaluation patterns that need to be inserted in one chip is smaller than 1/10 times the value calculated by B / A, the estimation accuracy of product yield is slightly Deteriorate.

  As described above, according to the resistance failure monitoring apparatus according to the first embodiment, the resistance failure evaluation pattern 102 has a length that can measure a resistance variation component that causes a soft open failure. It is possible to accurately evaluate a resistance increase defect (soft open defect) in the resistance element to be evaluated. In addition, since each of the chips 101 on the wafer 100 has the number of resistance defect evaluation patterns 102 that can evaluate the yield of the resistance elements, resistance measurement is performed on each resistance defect evaluation pattern 102 in each chip 101. By detecting the number of soft open defects based on the measurement result, it is possible to evaluate the yield of the resistance element. Therefore, it is possible to evaluate the yield of a product (semiconductor integrated circuit device) in consideration of the soft open defect, that is, the influence evaluation of the soft open defect on the product yield.

  In the first embodiment, the resistance failure monitoring device is provided on the wafer in units of one chip region (chip 101) corresponding to the semiconductor integrated circuit device. However, instead of this, a resistance defect monitoring device may be provided on the wafer in units of one shot area, which is an exposure area in one lithography process. Here, as shown in FIG. 4, the one-shot area 101 </ b> A may include a plurality of chips 101. In this case, the one-shot region 101A may have a region where no resistance defect evaluation pattern is provided. Similarly, also in this embodiment, the chip 101 may have a region where no resistance failure evaluation pattern is provided.

In the first embodiment, the measurable range of the resistance variation component that becomes defective is
(RB-RA) /RA.times.100.gtoreq.2% (RA: normal gate electrode wiring resistance value, RB: gate electrode wiring resistance value where one defect occurs) This range is not particularly limited. Needless to say. Further, (RB-RA) / RA × 100 is preferably 100% or less. That is, generally, if the resistance variation of the evaluation pattern varies within about ± 10% with respect to the target value, the evaluation pattern is evaluated as a non-defective product. It only has to be detected. In addition, when a complete disconnection occurs, the magnitude of the resistance variation component detected is infinitely large (∞%), so that the conventional long wiring pattern comb-like (Comb) and snake-like (Serp) Resistance failure evaluation can be performed using the wiring pattern. Therefore, (RB-RA) / RA × 100 may be 10000% or less in order to distinguish from the conventional resistance defect evaluation by the long wiring pattern.

  Further, in the first embodiment, it is assumed that a resistance variation defect occurs in one place in the resistance defect evaluation pattern, but this embodiment is also applied to a case where resistance variation defects occur in two or more places in the resistance defect evaluation pattern. Needless to say, it can be applied.

  Further, in the first embodiment, the case where the resistance element to be evaluated is a gate electrode wiring of a MOS transistor is targeted. However, the present embodiment is not limited to this, and other resistive elements, for example, a MOS transistor body (meaning the whole transistor structure: the same applies hereinafter), a bipolar transistor body, a pn junction diode, a source / source of a MOS transistor The target may be a drain impurity layer, a metal wiring, a contact connecting the impurity layer and the wiring layer, a via connecting the wiring layers, or the like.

(Second Embodiment)
Hereinafter, a resistance defect evaluation apparatus (resistance resistance monitor apparatus) according to the second embodiment of the present invention, specifically, a wafer (evaluation) for evaluating resistance fluctuation defects of resistance elements mounted on a semiconductor integrated circuit device. An evaluation apparatus provided on a wafer for use will be described with reference to the drawings.

  FIG. 5A is a plan view of one chip area (or one shot area) of the resistance defect monitoring device of this embodiment. As shown in FIG. 5A, the chip area 101 (hereinafter simply referred to as the chip 101) is partitioned into a plurality of blocks 120.

  FIG. 5B shows a state where the resistance defect monitoring device (one chip region) of the present embodiment shown in FIG. 5A is uniformly arranged in the wafer surface. As shown in FIG. 5B, in this embodiment, chips 101 are arranged at 51 locations on the main surface of the wafer 100.

  FIG. 5C shows an internal state of one block of the resistance defect monitoring apparatus of the present embodiment shown in FIG. As shown in FIG. 5C, the feature of this embodiment is that each block 120 on the chip 101 has a size (length or width) that can detect a resistance variation component that causes a soft open defect and is evaluated. A resistance defect evaluation pattern 102 (see the first embodiment in detail) having a structure substantially the same as that of the target resistance element, and dimensions, film thickness, resistivity, etc. for determining the resistance value of the resistance defect evaluation pattern 102 A calibration pattern 121 (specifically, a calibration pattern group consisting of two types of calibration patterns having substantially different widths of line portions serving as resistors) used to calibrate at least one of them. It is provided. That is, the variation in resistance value of the resistance defect evaluation pattern 102 can be corrected by the calibration pattern 121. Here, in each block 120, the calibration pattern 121 is preferably arranged in the vicinity of the resistance failure evaluation pattern 102, specifically, within a range of 500 μm or less from the resistance failure evaluation pattern 102.

  As described above, in the resistance defect monitoring apparatus of this embodiment, one block 120 is configured from the resistance defect evaluation pattern 102 and the calibration pattern 121, and the block 120 is in one chip area (or one shot area). The chip regions (chips 101) are uniformly arranged in the main surface of the wafer 100.

  According to the resistance defect monitoring apparatus according to the second embodiment, the following effects can be obtained in addition to the same effects as those of the first embodiment. That is, the measurement result of the resistance value of the resistance defect evaluation pattern 102 to be evaluated can be corrected using the calibration pattern 121 in the wafer surface or in the chip area (or shot area). Specifically, the variation in the size, film thickness, or resistivity of the resistance defect evaluation pattern 102 in the wafer surface or chip region (or shot region) is changed to the respective values in the wafer surface or chip region (or shot region). Since correction can be made with points, resistance evaluation of the resistance defect evaluation pattern 102 can be performed with higher accuracy. Therefore, the soft open defect can be detected with higher accuracy.

  In the second embodiment, as shown in FIG. 5C, independent probing pads (terminals) are provided for the resistance defect evaluation pattern 102 and the calibration pattern 121, respectively. Thereby, the effect that the measurement accuracy of each resistance value of the resistance defect evaluation pattern 102 and the calibration pattern 121 is improved is obtained. However, it goes without saying that a common probing pad may be provided in the resistance failure evaluation pattern 102 and the calibration pattern 121 as shown in FIG. 6A or 6B instead.

(Third embodiment)
Hereinafter, a resistance defect evaluation apparatus (resistance resistance monitor apparatus) according to a third embodiment of the present invention, specifically, a wafer (evaluation) for evaluating resistance fluctuation defects of resistance elements mounted on a semiconductor integrated circuit device. An evaluation apparatus provided on a wafer for use will be described with reference to the drawings.

  As in the first embodiment, the first feature of the resistance defect monitoring apparatus according to the present embodiment is that the resistance variation component that causes a soft open defect can be detected in one chip area (or one shot area). The number of resistance defect evaluation patterns having a length (length or width) and substantially the same structure as the resistance element to be evaluated is arranged in such a number that the yield evaluation of the semiconductor integrated circuit device can be performed.

  The second feature of the resistance failure monitoring apparatus according to the present embodiment is that, similarly to the second embodiment, the chip region (or shot region) is divided into a plurality of blocks, and each block has a resistance failure. A calibration pattern (calibration pattern group) is arranged together with the evaluation pattern. Thereby, the resistance value of the measured resistance defect evaluation pattern can be calibrated with high accuracy.

  As described above, the resistance defect monitoring apparatus according to this embodiment is a resistance defect monitoring apparatus that combines the first embodiment and the second embodiment.

  Therefore, when the length of the resistance failure evaluation pattern is A and the total length (total distance) of the resistance elements to be evaluated mounted on the semiconductor integrated circuit device is B, 1 in the resistance failure monitoring device according to this embodiment. The number of resistance defect evaluation patterns that need to be inserted into one chip region (or shot region) is a number in the range of 1/100 times or more and 10 times or less of B / A.

Also, let RA be the resistance value of a resistance defect evaluation pattern of length A where no resistance variation defect has occurred (normal), and resistance of the resistance defect evaluation pattern of length A where resistance variation defect has occurred at least at one location. When the value is RB, the length A of the resistance failure evaluation pattern is, for example, (RB−RA) / RA × 100 ≧ 2%
In other words, the magnitude (ratio) of the resistance fluctuation component that causes the resistance fluctuation failure is set to be 2% or more.

  Here, when inserting a necessary quantity of resistance defect evaluation patterns into the chip area (or shot area), as shown in FIG. The number of blocks 120 corresponding to the above-described required quantity may be uniformly arranged in one chip area (or one shot area). At this time, “required quantity of resistance defect evaluation pattern in one chip area (or one shot area)” = “number of blocks arranged in one chip area (or one shot area)”.

  Alternatively, when inserting a necessary quantity of resistance defect evaluation patterns into the chip area (or shot area), as shown in FIG. 7B, the number of resistance defect evaluation patterns 102 arranged in each block 120 is increased. Also good. In this case, “required quantity of resistance defect evaluation pattern in one chip area (or one shot area)” = “number of blocks arranged in one chip area (or one shot area)” × “arranged in one block The number of resistance defect evaluation patterns ”.

  According to the resistance defect monitoring apparatus according to the third embodiment, in addition to the same effects as those of the first embodiment, the same effects as those of the second embodiment can be obtained. That is, the measurement result of the resistance value of the resistance defect evaluation pattern 102 to be evaluated can be corrected in the wafer surface or the chip area (or shot area) using the calibration pattern 121. For this reason, resistance evaluation of the resistance failure evaluation pattern can be performed with high accuracy, so that soft open failure can be detected with higher accuracy.

  Further, according to the resistance defect monitoring apparatus according to the third embodiment, the number of resistance defect evaluation patterns 102 corresponding to the total length (total distance) of the resistance elements in the semiconductor integrated circuit device is one chip region (or one shot). Therefore, the influence of the soft open defect on the product (semiconductor integrated circuit device) yield can be evaluated.

  In the second or third embodiment, the type of resistance element to be evaluated is not particularly limited. For example, a MOS transistor body, a bipolar transistor body, a pn junction diode, a gate electrode wiring or a source of a MOS transistor / A drain impurity layer, metal wiring, a contact connecting the impurity layer and the wiring layer, a via connecting the wiring layers, or the like may be used.

(Fourth embodiment)
Hereinafter, a resistance defect evaluation apparatus (resistance resistance monitor apparatus) according to the fourth embodiment of the present invention, specifically, a wafer (evaluation) for evaluating resistance fluctuation defects of resistance elements mounted on a semiconductor integrated circuit device. An evaluation apparatus provided on a wafer for use will be described with reference to the drawings. Note that the resistance failure monitoring apparatus according to the fourth embodiment includes a silicide layer in a stacked structure of a polysilicon electrode and a silicide layer formed thereon used for gate electrode wiring of a semiconductor integrated circuit device. This is a resistance defect monitoring device that evaluates soft open defects caused by disconnection.

  FIG. 8A is a plan view of one chip region (or one shot region) of the resistance defect monitoring device of this embodiment. As shown in FIG. 8A, the chip region 101 (hereinafter simply referred to as the chip 101) is partitioned into a plurality of blocks 120.

  FIG. 8B shows a state in which the resistance defect monitoring device (one chip region) of the present embodiment shown in FIG. 8A is uniformly arranged in the wafer surface. As shown in FIG. 8B, in this embodiment, chips 101 are arranged at 51 locations on the main surface of the wafer 100.

  FIG. 8C shows an internal state of one block of the resistance defect monitoring apparatus of this embodiment shown in FIG. As shown in FIG. 8C, the feature of this embodiment is that each block 120 on the chip 101 has a size (length or width) that can detect a resistance variation component that causes a soft open failure and is evaluated. A resistance defect evaluation pattern 102 (see the first embodiment in detail) having a structure substantially the same as the target resistance element, and dimensions, film thickness, resistivity, etc. for determining the resistance value of the resistance defect evaluation pattern 102 The first calibration pattern 121A and the second calibration pattern 121B used for calibrating at least one of them are provided. That is, the variation in resistance value of the resistance defect evaluation pattern 102 can be corrected by the calibration patterns 121A and 121B. Here, in each block 120, each calibration pattern 121A and 121B is preferably arranged in the vicinity of the resistance defect evaluation pattern 102, specifically, within a range of 500 μm or less from the resistance defect evaluation pattern 102.

  In the resistance defect monitoring apparatus according to the present embodiment, assuming that the length of the resistance defect evaluation pattern 102 is A and the total length (total distance) of resistance elements to be evaluated mounted on the semiconductor integrated circuit device is B. The number of resistance defect evaluation patterns 102 that need to be inserted into one chip region (or shot region) is a number in the range of 1/100 times and 10 times or less of B / A (more preferably B / A The number in the range of 1/10 times or more and 10 times or less.

Also, let RA be the resistance value of a resistance defect evaluation pattern of length A where no resistance variation defect has occurred (normal), and resistance of the resistance defect evaluation pattern of length A where resistance variation defect has occurred at least at one location. When the value is RB, the length A of the resistance failure evaluation pattern is, for example, (RB−RA) / RA × 100 ≧ 2%
In other words, the resistance variation component magnitude (RB-RA) that causes resistance variation failure is set to be 2% or more with respect to the resistance value RA of the normal resistance failure evaluation pattern.

  Hereinafter, the details of the resistance defect evaluation pattern 102, the first calibration pattern 121A, and the second calibration pattern 121B will be described with reference to the drawings. 8D and 8E are a plan view and a cross-sectional view of the resistance defect evaluation pattern 102, and FIGS. 8F and 8G are a plan view and a cross-sectional view of the first calibration pattern 121A. FIGS. 8H and 8I are a plan view and a cross-sectional view of the second calibration pattern 121B.

  As shown in FIG. 8D, the resistance failure evaluation pattern 102 is a pattern corresponding to a resistance element to be evaluated for failure, and its gate width is 0.1 μm, which is the same as the resistance element, and its length ( The length (A) of the line portion substantially serving as the resistor is set to 280 μm. Here, in order to perform resistance measurement by two-terminal measurement, 80 μm × 80 μm sized pads are provided as probing pads at both ends of the resistance defect evaluation pattern 102. Although not shown in FIG. 8D, the resistance defect evaluation pattern 102 is formed on the insulating film 132 on the silicon substrate 131 made of a wafer, as shown in FIG. 8E. And a stacked structure of a polysilicon electrode 133 and a silicide layer 134 formed thereon. A sidewall insulating film 135 is formed on the side surface of the polysilicon electrode 133. The silicide layer 134 is formed by siliciding the upper part of the silicon layer constituting the polysilicon electrode 133 by a salicide process. The resistance failure evaluation pattern 102 is used to detect disconnection of the silicide layer 134 on the polysilicon electrode 133 and a resistance increase failure (soft open failure) resulting therefrom.

  Next, as shown in FIG. 8F, the first calibration pattern 121A is a pattern for calibrating the resistance value of the resistance defect evaluation pattern 102, and its gate width and length are resistance defect evaluation. It is set to be the same as the pattern 102 (in this embodiment, 0.1 μm and 280 μm, respectively). Here, similarly to the resistance defect evaluation pattern 102, in order to perform resistance measurement by two-terminal measurement, pads of 80 μm × 80 μm size are provided as probing pads at both ends of the first calibration pattern 121A. Yes. Although not shown in FIG. 8F, as in the resistance defect evaluation pattern 102, the first calibration pattern 121A is also a silicon substrate made of a wafer as shown in FIG. It is formed on an insulating film 132 on 131. However, unlike the resistance failure evaluation pattern 102, the first calibration pattern 121 A has a single layer structure of the polysilicon electrode 133. In other words, the upper part of the polysilicon electrode 133 is not silicided. Specifically, in the first calibration pattern 121A, as shown in FIG. 8G, silicidation is prevented by providing a silicidation preventing insulating film 136 on the polysilicon electrode 133. However, the surface of the probing pad is silicided.

  Next, as shown in FIG. 8H, the second calibration pattern 121B is a pattern for calibrating the resistance value of the resistance defect evaluation pattern 102, and its length is the same as the resistance defect evaluation pattern 102. The same (in this embodiment, 280 μm) is set. However, the second calibration pattern 121B has a thick gate width of 1.0 μm, whereas the gate width of the first calibration pattern 121A is 0.1 μm. Here, similarly to the resistance defect evaluation pattern 102, in order to perform resistance measurement by two-terminal measurement, pads of 80 μm × 80 μm size are provided as probing pads at both ends of the second calibration pattern 121B. Yes. Although not shown in FIG. 8H, the second calibration pattern 121B is also a silicon substrate made of a wafer as shown in FIG. It is formed on an insulating film 132 on 131. However, unlike the resistance failure evaluation pattern 102, the second calibration pattern 121B has a single layer structure of the polysilicon electrode 133. In other words, like the first calibration pattern 121A, the upper portion of the polysilicon electrode 133 is not silicided. Specifically, in the second calibration pattern 121B, silicidation is prevented by providing a silicidation preventing insulating film 136 on the polysilicon electrode 133 as shown in FIG. 8 (i). However, the surface of the probing pad is silicided. Since the second calibration pattern 121B has a thick gate width of 1.0 μm, it is hardly affected by dimensional variations in the wafer surface and each chip area (or each shot area) in the lithography process.

  According to the resistance failure monitoring apparatus according to the fourth embodiment configured as described above, the measurement resistance value of the first calibration pattern 121A and the measurement resistance value of the second calibration pattern 121B are compared and evaluated. Accordingly, it is possible to evaluate the dimensional variation of the resistance defect evaluation pattern 102 in the wafer surface and in each chip region (or shot region). In other words, by using the first calibration pattern 121A and the second calibration pattern 121B, based on the resistance value measured for each calibration pattern, the wafer surface and each chip area (or shot area) Electrically converted dimensions (ECD: see the seventh embodiment for details) of the resistance failure evaluation pattern 102 at various points can be extracted. As a result, the measured resistance value of the resistance failure evaluation pattern 102 at each point can be corrected using the ECD at each point, so that the resistance rise failure (soft open failure) of the resistance failure evaluation pattern 102 is increased. It becomes possible to detect with accuracy.

  In the fourth embodiment, instead of the polysilicon electrodes constituting each of the resistance element to be evaluated and the resistance failure evaluation pattern 102, the first calibration pattern 121A and the second calibration pattern 121B, other An electrode made of a silicon-containing layer may be used.

  In the fourth embodiment, in order to improve the detection accuracy of the resistance rise failure of the resistance failure evaluation pattern 102, the second calibration pattern 121B has a gate width that is at least five times the resistance element to be evaluated. It is preferable to have.

  In the fourth embodiment, the resistance element to be evaluated is a silicided gate electrode wiring in a MOS transistor. Instead, a silicided source / drain impurity layer in a MOS transistor is used. It may be a target.

(Fifth embodiment)
Hereinafter, a resistance failure monitoring apparatus according to a fifth embodiment of the present invention will be described with reference to the drawings.

  The resistance failure monitoring apparatus according to the fifth embodiment is different from the fourth embodiment as follows.

  FIG. 9 shows the inside of one block of the resistance defect monitoring apparatus of this embodiment. As shown in FIG. 9, the first difference between the present embodiment and the fourth embodiment is that each block 120 on the chip 101 has the same gate width as that of the resistance element to be evaluated for defects (this embodiment). In addition to the resistance defect evaluation pattern 102 having 0.1 μm in the embodiment, other resistance defect evaluation patterns 102 having at least two types of gate widths (0.09 μm and 0.11 μm in the present embodiment) different from the gate width. Is provided. The other resistance failure evaluation patterns 102 have the same length and the same structure as the resistance failure evaluation pattern 102. The second difference between the present embodiment and the fourth embodiment is that each block 120 on the chip 101 has the same gate width (0.1 μm in this embodiment) as the resistance element to be evaluated for defects. ) Having at least two different gate widths (0.09 μm and 0.11 μm in this embodiment) different from the gate width, that is, the same gate as the other resistance defect evaluation pattern 102 This is that another first calibration pattern 121A having a width is provided. The length and the structure of the other first calibration pattern 121A are the same as those of the first calibration pattern 121A.

  According to the fifth embodiment, the following effects can be obtained in addition to the effects of the fourth embodiment. That is, by using the resistance failure evaluation pattern 102 having a plurality of types of widths and the first calibration pattern 121A, the dimensional dependence of the resistance increase failure (soft open failure) in the resistance element to be evaluated is evaluated with higher accuracy. It becomes possible. In other words, the dimensional variation in the measured resistance value of the resistance defect evaluation pattern 102 can be corrected and the dimensional dependency in the measured resistance value of the resistance defect evaluation pattern 102 can be evaluated, so that the soft open defect can be evaluated with high accuracy. .

(Sixth embodiment)
Hereinafter, a resistance failure monitoring apparatus according to a sixth embodiment of the present invention will be described with reference to the drawings.

  The resistance defect monitoring apparatus according to the sixth embodiment is different from that of the fourth embodiment as follows.

  FIG. 10 shows the inside of one block of the resistance defect monitoring apparatus of this embodiment. As shown in FIG. 10, the difference between the present embodiment and the fourth embodiment is that each block 120 on the chip 101 has a resistance defect evaluation pattern 102 similar to that of the fourth embodiment, the first In addition to the calibration pattern 121A and the second calibration pattern 121B, a third calibration pattern 121C is provided. Specifically, the third calibration pattern 121C is a pattern for calibrating the resistance value of the resistance failure evaluation pattern 102, and the length thereof is the same as that of the resistance failure evaluation pattern 102 (280 μm in this embodiment). Is set to However, the third calibration pattern 121C has a thick gate width of 1.0 μm, whereas the gate width of the first calibration pattern 121A is 0.1 μm. Here, similarly to the resistance defect evaluation pattern 102, in order to perform resistance measurement by two-terminal measurement, pads of 80 μm × 80 μm size are provided as probing pads at both ends of the third calibration pattern 121C. Yes. Although not shown, like the resistance defect evaluation pattern 102, the third calibration pattern 121C is also formed on an insulating film on a silicon substrate made of a wafer. However, unlike the first and second calibration patterns 121A and 121B, the third calibration pattern 121C is a laminate of a polysilicon electrode and a silicide layer formed thereon, like the resistance defect evaluation pattern 102. With structure. In other words, in the third calibration pattern 121C, the upper part of the polysilicon electrode including the surface of the probing pad is silicided.

  According to the sixth embodiment, by measuring and evaluating the resistance of the third calibration pattern 121C as described above, that is, the silicided thick gate electrode wiring having a width of 1.0 μm, it is affected by the dimensional variation. Therefore, the resistance value of the silicide layer can be evaluated. That is, since the silicide layer on the polysilicon layer is generally manufactured using a salicide process, the resistance of the silicide layer varies depending on the film thickness of the refractory metal film for forming a silicide layer sputtered in the salicide process. Accordingly, by using the third calibration pattern 121C, variation in the sheet resistance of the silicide layer of the resistance failure evaluation pattern 102 in the wafer surface and the chip region (or shot region) (variation in the sputtering film thickness of the refractory metal film). ) Can be evaluated. In other words, it is possible to correct the resistance variation component of the silicide layer of the resistance defect evaluation pattern 102 in the wafer surface and in the chip region (or shot region).

  In the sixth embodiment, in the same manner as in the fifth embodiment, each block 120 on the chip 101 has a resistance defect evaluation pattern 102 having the same gate width as the resistance element to be evaluated, Another resistance defect evaluation pattern 102 having at least two types of gate widths different from the gate width may be provided. Further, in addition to the first calibration pattern 121A having the same gate width as the resistance element to be evaluated for failure, each block 120 on the chip 101 has at least two types of gate widths different from the gate width, that is, other resistances. Another first calibration pattern 121A having the same gate width as the defect evaluation pattern 102 may be provided.

(Seventh embodiment)
The resistance failure evaluation method (resistance failure monitoring method) according to the seventh embodiment of the present invention, specifically, mounted on a semiconductor integrated circuit device using the resistance failure monitoring device according to the fourth embodiment. A method for evaluating a resistance variation defect of a resistive element will be described with reference to the drawings. Note that the resistance defect monitoring method according to the present embodiment is applied to the disconnection of the silicide layer in the stacked structure of the polysilicon electrode and the silicide layer formed thereon used for the gate electrode wiring of the semiconductor integrated circuit device. This is a resistance defect monitoring method for evaluating the resulting soft open defect.

  First, in the first step, the resistance defect evaluation pattern 102 in each block 120 and the first calibration are used by using the resistance defect monitoring device according to the fourth embodiment shown in FIGS. The resistance values of the pattern 121A and the second calibration pattern 121B are measured at a plurality of locations in the wafer surface and in each chip area (or in each shot area). Here, as in the fourth embodiment, the resistance defect evaluation pattern 102 has a silicide layer, and the width and length thereof are 0.1 μm and 280 μm. The first calibration pattern 121A does not include a silicide layer. The width and length are 0.1 μm and 280 μm, the second calibration pattern 121B does not include a silicide layer, and the width and length are 1.0 μm and 280 μm.

Next, in the second step, the design value of the width of the second calibration pattern 121B is set to DR (1.0 μm in this embodiment), and the first calibration is performed in the same block 120 measured in the first step. Assuming that the resistance values of the pattern 121A and the second calibration pattern 121B are R1 and R2, the electrical conversion dimension ECD of the resistance defect evaluation pattern 102 in the block 120 is
ECD = DR × R2 / R1 (Formula 1)
Calculate according to

  FIG. 11A shows the in-wafer distribution of the electrical conversion dimension ECD calculated in the second step, and FIGS. 11B and 11C show the wafer center chip (FIG. 11A) of the ECD. ) In R1) and the wafer notch side chip (R2 in FIG. 11A). As shown in FIGS. 11A to 11C, the electrical conversion dimension (ECD) varies from 0.082 μm to 0.097 μm in the wafer surface or in the chip region (or shot region). Further, as shown in FIGS. 11B and 11C, even within the chip region, there is a variation of about 3σ = 6% or a variation of (Max−Min) /2Ave=4.5%. You can see that

  Next, in the third step, the electrical conversion dimension ECD calculated in the second step and the resistance value R of the resistance defect evaluation pattern 102 measured in the first step are plotted on the X axis and the Y axis, respectively. .

  FIG. 12A is a graph obtained by plotting in the third step. As shown in FIG. 12A, the resistance value R of the resistance defect evaluation pattern 102 is strongly dependent on the pattern dimension. That is, when the dimension extraction (dimension correction) using the first calibration pattern 121A and the second calibration pattern 121B as in the present embodiment is not performed, the resistance value R of the resistance defect evaluation pattern 102 is measured. The resistance increase component due to the resistance fluctuation failure (soft open failure) is buried in the variation of the above, and the soft open failure cannot be accurately evaluated.

  On the other hand, in the present embodiment, in the third step, as shown in FIG. 12A, the resistance value of the resistance defect evaluation pattern 102 with respect to the electrical conversion dimension (ECD) is considered in consideration of the influence of the dimensional variation. Plot (R). Subsequently, in the fourth process, by extracting points where the resistance value R of the resistance defect evaluation pattern 102 is discretely increased based on the graph obtained in the third process, the resistance defect evaluation pattern 102 It becomes possible to detect a soft open defect. Specifically, in the present embodiment, the value of the resistance variation component due to the resistance variation failure (soft open failure) is about 2 kΩ.

  As described above, according to the seventh embodiment, the resistance value R of the resistance defect evaluation pattern 102 is based on the result of plotting the resistance value (R) of the resistance defect evaluation pattern against the electrical conversion dimension (ECD). Therefore, it is possible to accurately detect a defect in the resistance defect evaluation pattern 102, specifically, a disconnection defect (soft open defect) in the silicide layer. The resistance value R of the resistance defect evaluation pattern 102 measured in the first step is also subjected to wafer mapping or chip mapping (or shot mapping) as shown in FIGS. It is also possible to evaluate where the soft open defect occurs in the wafer surface or in the chip area (or in the shot area) based on the map. That is, it is possible to evaluate the yield of the integrated circuit device by detecting the number of soft open defects. In other words, the influence of soft open defects on the yield of the integrated circuit device to be manufactured can be evaluated.

In the seventh embodiment, instead of plotting the resistance value (R) of the resistance defect evaluation pattern against the electrical conversion dimension (ECD) in the third step, the following processing may be performed. Good. That is, assuming that the length of the resistance failure evaluation pattern 102 is A, the resistance value (R) of the resistance failure evaluation pattern 102 measured for each block 120 in the first step and the calculation for each block 120 in the second step. The sheet resistance value Rs of the resistance defect evaluation pattern 102 in each block 120 is calculated using the converted electrical dimensions (ECD).
Rs = R × ECD / A (Formula 2)
Calculate according to Subsequently, the electrical conversion dimension ECD and the calculated sheet resistance value Rs of the resistance defect evaluation pattern 102 are plotted on the X axis and the Y axis, respectively. FIG. 12B is a graph obtained by the plot. As shown in FIG. 12B, by converting the resistance value (R) of the resistance defect evaluation pattern 102 into the sheet resistance value (Rs), the soft open defect can be more easily separated. Specifically, after plotting the sheet resistance value (Rs) of the resistance failure evaluation pattern 102 against the electrical conversion dimension (ECD), the sheet resistance value of the resistance failure evaluation pattern 102 based on the graph obtained by the plotting. By extracting the points at which (Rs) increases discretely, it becomes possible to detect a soft open defect in the resistance defect evaluation pattern 102. Thus, based on the result of plotting the sheet resistance value (Rs) of the resistance failure evaluation pattern against the electrical conversion dimension (ECD), the points where the sheet resistance value (Rs) of the resistance failure evaluation pattern increases discretely are determined. Also by extracting, it is possible to accurately detect a failure of the resistance failure evaluation pattern 102, specifically, a disconnection failure (soft open failure) of the silicide layer. Note that the sheet resistance value (Rs) of the resistance defect evaluation pattern 102 can also be converted into a wafer map or a chip map (or shot map) as shown in FIGS. Based on the map, it is possible to evaluate where the soft open defect occurs in the wafer surface or in the chip area (or in the shot area).

  In the seventh embodiment, in the first step, the resistance defect monitoring apparatus according to the fifth embodiment may be used instead of the resistance defect monitoring apparatus according to the fourth embodiment. Specifically, in addition to the resistance defect evaluation pattern 102 having the same gate width (0.1 μm in this embodiment) as that of the resistance element to be evaluated for failure in each block 120, at least two types different from the gate width are provided. Another resistance defect evaluation pattern having a gate width may be provided. The length and structure of the other resistance failure evaluation patterns are the same as the resistance failure evaluation pattern 102. Further, in addition to the first calibration pattern 121A having the same gate width as the resistance element to be evaluated for failure in each block 120, at least two different gate widths different from the gate width, that is, other resistance failure evaluation patterns Another first calibration pattern having the same gate width may be provided. The length and the structure of the other first calibration patterns are the same as those of the first calibration pattern 121A. In the present embodiment, when the resistance defect monitoring apparatus according to the fifth embodiment as described above is used, in the first step, the resistance defect evaluation pattern 102, the first calibration pattern 121A and the second calibration pattern in each block 120 are used. In addition to the respective resistance values of the calibration pattern 121B, the other resistance failure evaluation patterns in each block 120 and the respective resistance values of the other first calibration patterns are changed in the wafer surface and in each chip area (or each Measure at multiple points in the shot area. In this way, the resistance dependency evaluation pattern (soft open defect) in the resistance element to be evaluated is evaluated with higher accuracy by using the resistance defect evaluation pattern having a plurality of types of widths and the first calibration pattern. It becomes possible. In other words, the dimensional variation in the measured resistance value of the resistance failure evaluation pattern can be corrected and the dimensional dependency in the measured resistance value of the resistance failure evaluation pattern can be evaluated, so that the soft open failure can be evaluated with high accuracy.

(Eighth embodiment)
The resistance failure evaluation method (resistance failure monitoring method) according to the eighth embodiment of the present invention, specifically, mounted in a semiconductor integrated circuit device using the resistance failure monitoring device according to the sixth embodiment. A method for evaluating a resistance variation defect of a resistive element will be described with reference to the drawings. Note that the resistance defect monitoring method according to the present embodiment is applied to the disconnection of the silicide layer in the stacked structure of the polysilicon electrode and the silicide layer formed thereon used for the gate electrode wiring of the semiconductor integrated circuit device. This is a resistance defect monitoring method for evaluating the resulting soft open defect.

  First, in the first step, the resistance defect evaluation pattern 102, the first calibration pattern 121A, and the third calibration pattern in each block 120 using the resistance defect monitoring apparatus according to the sixth embodiment shown in FIG. Each resistance value of the pattern 121C is measured at a plurality of locations in the wafer surface and in each chip area (or in each shot area). Here, similarly to the sixth embodiment, the resistance defect evaluation pattern 102 has a silicide layer and the width and length thereof are 0.1 μm and 280 μm, and the first calibration pattern 121A does not include a silicide layer. The width and length are 0.1 μm and 280 μm, the third calibration pattern 121C has a silicide layer, and the width and length are 1.0 μm and 280 μm.

Next, in the second step, the resistance values of the resistance defect evaluation pattern 102, the first calibration pattern 121A, and the third calibration pattern 121C in each block 120 measured in the first step are set to RR, r1, and Let r3 be the average values of the resistance values of all the first calibration patterns 121A and the resistance values of all the third calibration patterns 121C in the wafer plane measured in the first step, r1 (Ave) and r3. (Ave) is a correction value RR ′ (1), a correction value RR ′ (2), and a correction value RR ′ (3) of the resistance value RR of the resistance defect evaluation pattern 102, respectively.
RR ′ (1) = RR × r1 (Ave) / r1 (Formula 3)
RR ′ (2) = RR × r3 (Ave) / r3 (Formula 4)
RR ′ (3) = RR × r1 (Ave) × r3 (Ave) / (r1 × r3) (Formula 5)
Calculate according to

  The correction value RR ′ (1) is a value obtained by dimension-correcting the resistance value RR of the resistance defect evaluation pattern 102, and the correction value RR ′ (2) is a sheet resistance correction (silicide value) of the resistance value RR of the resistance defect evaluation pattern 102. A correction value RR ′ (3) obtained by correcting the sheet resistance variation component of the layer is a value obtained by correcting the dimension of the resistance value RR of the resistance defect evaluation pattern 102 and correcting the sheet resistance.

  FIGS. 13A to 13E are diagrams for explaining the concept of correction for the resistance value RR of the resistance defect evaluation pattern 102 and the difference in resistance value before and after the correction. Specifically, FIGS. 13A to 13D show the resistance value RR (actual data), the correction value RR ′ (1) (dimension correction value), and the correction value RR ′ (2) of the resistance defect evaluation pattern 102. FIG. 13 is a diagram schematically showing variation (resistance value variation) in cumulative frequency distribution of each of (sheet resistance correction value) and correction value RR ′ (3) (value subjected to dimension correction and sheet resistance correction); (E) is a diagram in which variations of the cumulative frequency distribution of the resistance value RR, the correction value RR ′ (1), the correction value RR ′ (2), and the correction value RR ′ (3) are superimposed.

  In this embodiment, the dimensional variation in the wafer surface and in the chip region (or in the shot region) is larger than the variation in the sheet resistance of the silicide layer. 13 (a) to (a), where a is a variation before correction, b is a variation after dimension correction, c is a variation after sheet resistance correction, and d is a variation after both corrections (dimension correction + sheet resistance correction). As shown in d), the magnitude relationship of each variation is a> c> b> d. That is, by performing each correction, it was confirmed that the cumulative frequency distribution became a sharp shape as shown in FIG. 13E, that is, the effect of the correction was obtained.

  Next, in the third step, distribution diagrams in the wafer plane of the correction value RR ′ (1), the correction value RR ′ (2) and the correction value RR ′ (3) calculated in the second step are shown. create. At this time, instead of the distribution map in the wafer surface, a distribution map in each chip area or each shot area may be created. Subsequently, in the fourth step, the correction value RR ′ (1), the correction value RR ′ (2), and the correction value RR ′ (3) are discrete based on the respective distribution diagrams created in the third step. By extracting the points that have risen to the first, the resistance fluctuation defect of the resistance defect evaluation pattern 102 is detected.

  FIG. 14A shows the in-wafer distribution of the resistance value RR (before correction) of the resistance defect evaluation pattern 102 measured in the first step, and FIG. 14B is calculated in the second step. 2 shows a distribution in the wafer surface of the correction value RR ′ (1) (dimension correction value) of the resistance value RR of the resistance defect evaluation pattern 102. Comparing FIG. 14 (a) and FIG. 14 (b), the resistance variation in the chip region (or shot region) seen in FIG. 14 (a) (before dimensional correction) is shown in FIG. 14 (b) (dimensional correction). It is not seen in (after). Thereby, by performing the dimension correction shown in (Equation 3), it is possible to more accurately evaluate the resistance fluctuation defect of the resistance defect evaluation pattern 102 in the wafer surface and in each chip area (or in each shot area). I understand. Incidentally, from the wafer in-plane distribution of the correction value RR ′ (1) (dimension correction value) shown in FIG. 14B, it can be detected that a resistance increase failure (soft open failure) has occurred at 12 locations.

  FIG. 15A shows the in-wafer distribution of the correction value RR ′ (2) (sheet resistance correction value) of the resistance value RR of the resistance defect evaluation pattern 102 calculated in the second step. (B) shows the in-wafer distribution of the correction value RR ′ (3) (value subjected to dimension correction and sheet resistance correction) of the resistance value RR of the resistance defect evaluation pattern 102 calculated in the second step. . Comparing FIG. 14A with FIGS. 15A and 15B, the resistance variation in the chip region (or shot region) seen in FIG. 14A (before dimensional correction) is shown in FIG. ) (After sheet resistance correction) and FIG. 15B (after dimensional correction and sheet resistance correction) are not seen. Thus, by performing the sheet resistance correction shown in (Equation 4) or the dimension correction and the sheet resistance correction shown in (Equation 5), a resistance failure evaluation pattern in the wafer surface and in each chip area (or in each shot area). It can be seen that the resistance fluctuation failure 102 can be more accurately evaluated. Further, the in-wafer distribution of the correction value RR ′ (2) (sheet resistance correction value) shown in FIG. 15A and the correction value RR ′ (3) (size correction and sheet resistance correction shown in FIG. From the distribution in the wafer surface, the resistance increase failure (soft open failure) occurs at 12 locations, similar to the distribution in the wafer surface of the correction value RR ′ (1) shown in FIG. Can be detected.

  As described above, according to the eighth embodiment, the measurement resistance of the resistance defect evaluation pattern 102 is obtained by using the first calibration (dimension correction) pattern 121A and the third calibration (sheet resistance correction) pattern 121C. Since the value RR can be accurately corrected, it is possible to accurately evaluate a failure of the resistance failure evaluation pattern 102, specifically, a disconnection failure (soft open failure) of the silicide layer.

  In the second step (especially (Expression 3) and (Expression 5)) of the eighth embodiment, instead of the average value r1 (Ave), one of the chip regions measured in the first step or The average value r1shot (Ave) of the resistance values of all the first calibration patterns 121A in one shot area, or one of the blocks measured in the first step (a plurality of first calibration patterns are included in the block). The average value r1block (Ave) of the resistance values of all the first calibration patterns 121A in the pattern 121A) may be used. Similarly, in the second step (especially (Expression 4) and (Expression 5)) of the eighth embodiment, one of the chip regions measured in the first step is used instead of the average value r3 (Ave). Alternatively, the average value r3shot (Ave) of the resistance values of all the third calibration patterns 121C in one of the shot areas, or one of the blocks measured in the first step (a plurality of third calibrations in the block). The average value r3block (Ave) of the resistance values of all the third calibration patterns 121C in the pattern 121C for use) may be used.

  In the eighth embodiment, the resistance value RR of the resistance defect evaluation pattern 102 is corrected using both the first calibration pattern 121A and the third calibration pattern 121C. Instead, the first calibration pattern is used. It goes without saying that the resistance value RR of the resistance defect evaluation pattern 102 may be corrected using only one of the pattern 121A and the third calibration pattern 121C. That is, measurement of the resistance values of the resistance failure evaluation pattern 102 and the first calibration pattern 121A or the third calibration pattern 121C, calculation of the correction value RR ′ (1) or correction value RR ′ (2), Creation of a distribution map based on the calculation result and detection of a resistance fluctuation defect based on the distribution map may be performed.

  In the eighth embodiment, the resistance value RR of the resistance defect evaluation pattern 102 is obtained by using the second calibration pattern 121B in the resistance defect monitoring device (for one block) according to the sixth embodiment shown in FIG. In contrast, the sheet resistance variation of the polysilicon electrode may be corrected.

(Ninth embodiment)
Hereinafter, a method for manufacturing a resistance defect evaluation apparatus (resistance defect monitoring apparatus) according to a ninth embodiment of the present invention, specifically, a resistance defect evaluation pattern in the resistance defect monitoring apparatus according to the second to sixth embodiments. A method of forming 102 and a calibration pattern 121 (at least one calibration pattern when there are a plurality of types) will be described with reference to the drawings. The present embodiment is directed to the manufacture of a resistance failure monitoring device for evaluating a soft open failure occurring in a silicided gate electrode wiring in a MOS transistor mounted on a semiconductor integrated circuit device.

  16 (a) to 16 (g) are cross-sectional views illustrating respective steps of the method of manufacturing the resistance defect monitoring device according to the ninth embodiment.

  First, as shown in FIG. 16A, a first insulating film 152 is formed on a semiconductor substrate 151 made of an evaluation wafer, and then, on the first insulating film 152, as shown in FIG. Then, a silicon film 153 such as a polysilicon film or an amorphous silicon film is deposited.

  Subsequently, as shown in FIG. 16C, after forming a resist pattern (not shown) covering the resistance defect evaluation pattern formation region and the calibration pattern formation region using a lithography process, the resist pattern is used as a mask. By etching the silicon film 153, the silicon film 153 is patterned into respective shapes of a resistance defect evaluation pattern and a calibration pattern.

  Next, as shown in FIG. 16D, a sidewall insulating film 154 is formed on the side surface of the patterned silicon film 153A, and then, as shown in FIG. The second insulating film 155 is deposited, and then a resist pattern (not shown) that covers the silicidation prevention region is formed using a lithography process, and then the second insulating film 155 is etched using the resist pattern as a mask. To do. Thereby, a silicidation region where the second insulating film 155 is removed by etching and a silicidation prevention region where the second insulating film 155 remains can be set.

  Next, as shown in FIG. 16F, a silicide layer 156 is formed on the silicon film 153A in the silicidation region by using a salicide process, thereby completing the gate electrode wiring structure. At this time, the second insulating film 155 prevents the silicide layer 156 from being formed on the silicon film 153A in the silicidation prevention region.

  Although not shown, after the formation of the silicide layer 156, in order to prevent the influence of the surface leakage current in each resistance measurement of the resistance defect evaluation pattern and the calibration pattern performed after the manufacture of the resistance defect monitoring device. Furthermore, a new insulating film may be deposited and only the upper part of the measurement pad (probing pad) in the insulating film may be removed. In addition, in order to prevent a leak current from being generated in the measurement pad portion due to contact with the prober needle, an interlayer film is formed on the measurement pad and a contact hole is formed in the interlayer film, and then a new metal is formed in the contact hole. A pad may be provided.

  As described above, the resistance failure monitoring device for detecting the resistance failure of the gate electrode wiring (specifically, the soft open failure caused by the disconnection of the silicide layer) by the process according to the ninth embodiment, for example, FIG. 16 (g), a resistance defect evaluation pattern having a silicide layer 156 and having a width and length of 0.1 μm and 280 μm, and a width and length not including the silicide layer 156 and having a width and length of 0.1 μm, as shown in FIG. A resistance defect monitoring device having a first calibration pattern of 280 μm and a second calibration pattern not including the silicide layer 156 and having widths and lengths of 1.0 μm and 280 μm can be manufactured.

  Thus, according to the ninth embodiment, compared to the manufacture of a semiconductor integrated circuit device (including MOS transistor formation, contact formation or multilayer wiring formation), the resistance failure according to the second to sixth embodiments The monitoring device can be manufactured with a very short process TAT. That is, it becomes possible to manufacture a resistance defect monitoring device only by a minimum of two lithography steps of patterning the silicon film 153 and patterning the second insulating film 155 for preventing silicidation. . As a result, each of the resistance defect monitoring devices of the present invention can be manufactured in a very short process TAT, so that it is possible to evaluate the resistance variation defect of the gate electrode wiring (soft open defect due to the disconnection of the silicide layer) at an early stage. The result can be fed back to the process measures at an early stage.

  In the present embodiment, the semiconductor substrate 151 which is an evaluation wafer is used, but it goes without saying that the evaluation wafer is not limited to the semiconductor substrate.

  In this embodiment, the polysilicon film or the amorphous silicon film is used as the constituent material of the gate electrode wiring, but it goes without saying that other silicon-containing films may be used.

(Tenth embodiment)
Hereinafter, a method for manufacturing a resistance defect evaluation apparatus (resistance defect monitoring apparatus) according to the tenth embodiment of the present invention, specifically, a resistance defect evaluation pattern in the resistance defect monitoring apparatus according to the second to sixth embodiments. A method of forming 102 and a calibration pattern 121 (at least one calibration pattern when there are a plurality of types) will be described with reference to the drawings. The present embodiment is directed to the manufacture of a resistance failure monitoring device for evaluating a soft open failure occurring in a silicided source / drain impurity layer in a MOS transistor mounted on a semiconductor integrated circuit device.

  FIGS. 17A to 17H are cross-sectional views showing respective steps of the method of manufacturing the resistance defect monitoring device according to the tenth embodiment.

  First, as shown in FIG. 17A, after a first insulating film 162 is formed on a semiconductor substrate 161 made of an evaluation wafer, a resistance defect evaluation pattern formation region and a calibration pattern formation region are formed using a lithography process. A resist pattern (not shown) is formed to cover the first insulating film 162, and then the first insulating film 162 is etched using the resist pattern as a mask, so that the first insulating film is formed as shown in FIG. The film 162 is patterned into a resistance defect evaluation pattern and a calibration pattern. Subsequently, the semiconductor substrate 161 is etched using the patterned first insulating film 162A as a mask to form a trench 161a.

  Next, as shown in FIG. 17C, after the second insulating film 163 is buried in the trench 161a, as shown in FIG. 17D, the second insulating film is formed by CMP (chemical mechanical polishing). The film 163 is planarized, and then the first insulating film 162A is removed to form a trench isolation 163A. Subsequently, as shown in FIG. 17E, after impurities are introduced into the exposed surface portion of the semiconductor substrate 161 where the trench isolation 163A is not formed (portion where the trench isolation 163A is not formed) by ion implantation. By performing heat treatment, an impurity layer 164 is formed on the exposed surface portion of the semiconductor substrate 161.

  Subsequently, as shown in FIG. 17F, after a third insulating film 165 for preventing silicidation is deposited on the semiconductor substrate 161, a resist pattern that covers the silicidation prevention region using a lithography process is deposited. After forming (not shown), the third insulating film 165 is etched using the resist pattern as a mask. Thereby, a silicidation region where the third insulating film 165 is removed by etching and a silicidation prevention region where the third insulating film 165 is left can be set.

  Next, as shown in FIG. 17G, a source / drain impurity layer structure is completed by forming a silicide layer 166 on the impurity layer (silicon layer) 164 in the silicidation region using a salicide process. At this time, the third insulating film 165 prevents the silicide layer 166 from being formed on the impurity layer 164 in the silicidation prevention region.

  Although not shown, after the silicide layer 166 is formed, in order to prevent the influence of the surface leakage current in each resistance measurement of the resistance defect evaluation pattern and the calibration pattern performed after the manufacture of the resistance defect monitoring device. Furthermore, a new insulating film may be deposited and only the upper part of the measurement pad (probing pad) in the insulating film may be removed. In addition, in order to prevent a leak current from being generated in the measurement pad portion due to contact with the prober needle, an interlayer film is formed on the measurement pad and a contact hole is formed in the interlayer film, and then a new metal is formed in the contact hole. A pad may be provided.

  As described above, the process according to the tenth embodiment detects a resistance variation defect (specifically, a soft open defect due to a disconnection of the silicide layer) of the source / drain impurity layer silicided by the salicide process. The intended resistance defect monitoring apparatus, for example, a first defect calibration pattern having a silicide layer 166 and a first calibration not including the silicide layer 166 and having the same width as that shown in FIG. Thus, it is possible to manufacture a resistance defect monitoring device having a pattern for use and a second calibration pattern that does not include the silicide layer 166 and has a width of at least five times the resistance defect evaluation pattern.

  Thus, according to the tenth embodiment, compared to the manufacture of a semiconductor integrated circuit device (including MOS transistor formation, contact formation or multilayer wiring formation), the resistance failure according to the second to sixth embodiments The monitoring device can be manufactured with a very short process TAT. That is, only a lithography process of at least two times, a patterning process of the first insulating film 162 for forming the trench isolation 163A and a patterning process of the third insulating film 165 for preventing silicidation. This makes it possible to manufacture a resistance defect monitoring device. As a result, each of the resistance defect monitoring devices of the present invention can be manufactured in a very short process TAT, so that it is possible to evaluate the resistance variation defect of the gate electrode wiring (soft open defect due to the disconnection of the silicide layer) at an early stage. The result can be fed back to the process measures at an early stage.

  In the present embodiment, the semiconductor substrate 161 which is an evaluation wafer is preferably a silicon-containing substrate such as a silicon substrate (including a substrate having a silicon-containing layer formed on the surface).

  In the above description of the first to tenth embodiments, the disconnection of the silicide layer mainly in the gate electrode wiring or the source / drain impurity layer has been described as the soft open defect. However, the soft open defect detection method or yield evaluation method according to the present invention is not limited to the soft open defect evaluation due to the disconnection of the silicide layer, but the soft open defect evaluation of a metal wiring made of aluminum or copper. Is also useful. Further, the present invention can be applied to evaluation of soft open defects such as a contact portion connecting an impurity layer such as a transistor and an upper wiring layer, or soft open defects of a via portion connecting metal wirings. Furthermore, if the current value abnormality of the MOS transistor body, the bipolar transistor body, or the pn junction diode is also considered as a resistance increase failure (soft open failure) of the resistor element in a broad sense, the above-described soft open failure detection method or yield according to the present invention. The evaluation method can be used to detect abnormality of the transistor or the diode, and the effect is very large.

(Eleventh embodiment)
Hereinafter, a contact resistance defect evaluation apparatus (contact resistance defect monitor apparatus) according to an eleventh embodiment of the present invention, specifically, a wafer (in order to evaluate a resistance variation defect of a contact mounted on a semiconductor integrated circuit device) An evaluation apparatus provided on an evaluation wafer will be described with reference to the drawings.

  FIG. 18A is a plan view of one chip region (or one shot region) of the contact resistance defect monitoring device of this embodiment. As shown in FIG. 18A, the chip region 201 (hereinafter simply referred to as the chip 201) is partitioned into a plurality of (for example, 25,000 in this embodiment) blocks 202, and inside each block 202, One contact chain resistance pattern is provided as an evaluation pattern for contact failure. Note that each of the contact chain resistance patterns of the present embodiment has a number of contacts that can measure a resistance variation component that causes a resistance variation failure occurring in the contact to be evaluated. In other words, as will be described later, each contact chain resistance pattern of the present embodiment has a predetermined number of contacts or less (eg, 198 in the present embodiment) determined by the measurement accuracy of the resistance value. Further, each contact chain resistance pattern of the present embodiment is composed of contacts having substantially the same structure as the contact to be evaluated.

  FIG. 18B shows a state in which the contact resistance failure monitoring device (provided in one chip region) of this embodiment shown in FIG. 18A is uniformly arranged in the wafer surface. As shown in FIG. 18B, in this embodiment, chips 201 are arranged at 51 locations on the main surface of the wafer 200. Therefore, 25000 × 51 = 1275000 contact chain resistance patterns are arranged per wafer. Note that the blocks 202 are uniformly arranged within the surface of the wafer 200 and inside each chip 201 (or each shot area).

  FIG. 18C is a plan view showing an example of the contact chain resistance pattern of this embodiment, and FIG. 18D is a cross-sectional view taken along the line c-c ′ in FIG.

  As shown in FIGS. 18C and 18D, a plurality of lower layer wirings 213 made of, for example, a polysilicon layer or an amorphous silicon layer are formed on the insulating film 212 on the substrate 211 made of, for example, silicon. . An interlayer insulating film 214 is formed on the insulating film 212 and on each lower layer wiring 213, and a plurality of contact electrodes (contact holes) 215 connected to each lower layer wiring 213 are formed on the interlayer insulating film 214. ing. In addition, a plurality of upper metal wirings 216 connected to the contact electrodes 215 are formed on the interlayer insulating film 214. A plurality of lower layer wirings 213 and a plurality of upper layer metal wirings 216 are connected by a plurality of contact electrodes 215, thereby forming a contact chain resistance pattern as shown in FIG. In FIG. 18C, the silicon substrate 211, the insulating film 212, and the interlayer insulating film 214 are not shown. Further, instead of the insulating film 212 and the lower layer wiring 213, a source / drain impurity layer of the transistor is formed on the surface portion of the silicon substrate 211, and a contact electrode for connecting the source / drain impurity layer and the upper layer wiring is formed. Also good.

  Here, a setting example of the number of contacts n of the contact chain resistance pattern shown in FIG. 18C will be described with reference to FIG.

As shown in FIG. 19, a case where one contact electrode 215A becomes defective in a contact chain resistance pattern in which a plurality of lower layer wirings 213 and a plurality of upper layer metal wirings 216 are connected by a plurality of contact electrodes 215 is considered. . Here, when the resistance value of one normal contact electrode 215 is rc, whereas the resistance value of the defective contact electrode 215A is rc + Δr, the resistance value Rc of the contact chain resistance pattern represents the total number of contacts as n. As
Rc = n × rc + Δr
It becomes. Therefore, for example, when a resistance variation component caused by a defect of one contact electrode 215 is detected with an accuracy of 1% or more with respect to the total resistance Rc of the contact chain resistance pattern,
(Δr / Rc) × 100 = (Δr / (n × rc + Δr)) × 100 ≧ 1%
The relationship expressed by must be established. That is,
n ≦ 99 × Δr / rc
Must be satisfied.

Therefore, when one normal contact electrode resistance rc = 20Ω / Co (/ Co means per contact electrode) and one defective contact electrode resistance variation component Δr = 40Ω / Co, one contact In order to detect a resistance variation component due to electrode failure with an accuracy of 1% with respect to the total resistance of the contact chain resistance pattern (that is, resistance variation of one defective contact electrode with respect to the resistance value of one normal contact electrode) In order to detect the resistance variation even when the ratio of the component is Δr / rc = 2 times), the contact number n of the contact chain resistance pattern is:
n = 99 × 40/20 = 198. In the present embodiment, a contact chain resistance pattern with n = 198 contacts is formed for the reasons described above.

  Next, a method for calculating the number P of arrangement patterns in one chip region (or one shot region) of the above-mentioned contact chain resistance pattern having 198 contacts will be described.

A recent semiconductor integrated circuit device has an enormous number of contacts. For example, in a chip having an area of about 40 mm ^{2 with a} rule of 0.13 μm, the number of contacts connecting between a transistor and a wiring layer is 5 to 30 million. It reaches about one piece. For example, when evaluating a contact failure in the semiconductor integrated circuit device A having N = 10 million contacts, the required number P0 of contact chain resistance patterns completely corresponding to the number of contacts N = 10 million is:
P0 = N / n = 1 × 10 7/198 = 50505 pieces to be calculated.

  In the present embodiment, the number P of contact chain resistance pattern arrangement patterns is set to a range of 1/10 times or more and 10 times or less the value calculated by N / n. Specifically, in the present embodiment, the number P of arrangement patterns corresponding to about half of N / n in the above-described range P = 25000 (the total number of contacts included in 25000 contact chain resistance patterns is 25000 × 198). = About 4.9 million). The reason is as follows.

FIG. 20 shows the total number of contacts N (the total number of contacts mounted on the semiconductor integrated circuit device or the total number of contacts included in all contact chain resistance patterns in the contact resistance failure monitoring device) and the total contact yield (semiconductor integrated circuit device). Or it is a figure which shows the relationship with yield (unit:%) of the yield of 1 chip | tip area | region of a contact resistance defect monitoring apparatus. In FIG. 20, the total number of contacts N is represented on the horizontal axis, and the yield Yield of the total contacts is represented on the vertical axis. Here, when the failure occurrence rate of one contact is λ, the yield Yield of the total contact in the contact resistance failure monitoring device in one chip region is
Yield = EXP (−λ × N)
Holds. By using this Yield calculation formula for the total contact yield, the yield Yield of the total contact when the defect occurrence rate λ of one contact is 1 ppb (ppb: 1 billion), 10 ppb, 100 ppb, and 1000 ppb, respectively. FIG. 20 shows the results calculated for various total number N of contacts.

  As shown in FIG. 20, when the total number of contacts N of the contact resistance defect monitoring device is 10 million as in the product (semiconductor integrated circuit device), the same yield can be obtained. Can be evaluated. In this case, as described above, the number of contact chain resistance patterns needs to be 50505. On the other hand, in this embodiment, N = 25000 is set. In this case, as shown in FIG. 20, the total number of contacts N of the contact resistance failure monitoring device is 4.9 million, so the total contact yield. Yield is calculated to be higher than the yield of the product, but the calculated value is a value sufficient to perform product yield evaluation (yield prediction) using a yield conversion formula.

  That is, when the number of contacts of the contact chain resistance pattern is n and the total number of contacts to be evaluated in the integrated circuit device is N, the number of contact chain resistance patterns that need to be inserted in one chip is N / n. When the value is set in a range of 1/10 times or more and 10 times or less of the value calculated in (1), the product yield can be predicted based on the yield obtained for the contact resistance defect monitoring device.

  As described above, according to the contact failure monitoring apparatus according to the eleventh embodiment, the contact chain resistance pattern has the number of contacts that can measure the resistance variation component that causes the resistance variation failure. Specifically, the contact chain resistance pattern of the present embodiment has a resistance variation component Δr in one contact (where Δr / rc = 2 times when one resistance value of the contact is rc) as the total resistance of the contact chain resistance pattern. The number of contacts that can be detected with 1% accuracy. Therefore, it is possible to accurately evaluate a soft open defect in a part of the contact, for example, one of many contacts. Further, on each chip 201 on the wafer 200, a number of contact chain resistance patterns (for example, 25000 in this embodiment) that can evaluate the yield of all contacts mounted on the semiconductor integrated circuit device are arranged. For this reason, the resistance of each contact chain resistance pattern in each chip 201 is measured, and the number of soft open defects is detected based on the measurement result, thereby evaluating the yield of all contacts mounted on the semiconductor integrated circuit device. It becomes possible to do. Specifically, it is possible to evaluate the yield of a product (semiconductor integrated circuit device) that takes into account the soft open defect that has a resistance fluctuation defect of Δr / rc = 2 times or more per contact, that is, the influence of the soft open defect on the product yield. It becomes.

  In the eleventh embodiment, the contact failure monitoring device is provided on the wafer in units of one chip region (chip 201) corresponding to the semiconductor integrated circuit device. However, instead of this, a contact failure monitoring device may be provided on the wafer in units of one shot area which is one exposure area in the lithography process. In this case, the one-shot region may have a region where the contact chain resistance pattern is not provided. Similarly, also in the present embodiment, the chip 201 may have a region where the contact chain resistance pattern is not provided.

Further, in the eleventh embodiment, the measurable range of the resistance variation component that becomes defective is
(Δr / Rc) × 100 = (Δr / (n × rc + Δr)) × 100 ≧ 1% (Rc: total resistance of contact chain resistance pattern (= n × rc + Δr), n: number of contacts in contact chain resistance pattern, rc : Resistance value of one normal contact electrode, Δr: resistance fluctuation component generated in one defective contact electrode), it goes without saying that this range is not particularly limited. Further, (Δr / Rc) × 100 is preferably 1 time (100%) or less. That is, generally, if the resistance variation of the evaluation pattern varies within about ± 10% with respect to the target value, the evaluation pattern is evaluated as a non-defective product. It only has to be detected. In addition, when a complete disconnection occurs, the magnitude of the resistance fluctuation component detected is infinite times (∞%), so it is necessary to evaluate the resistance failure using a conventional large-scale contact chain resistance pattern. Can do. Therefore, (Δr / Rc) × 100 may be 10000% or less in order to distinguish from the conventional resistance failure evaluation by a large-scale contact chain resistance pattern.

  In the eleventh embodiment, it is assumed that the resistance variation defect occurs in one place in the contact chain resistance pattern. However, the present embodiment is applied when the resistance variation defect occurs in two or more places in the contact chain resistance pattern. Needless to say, you can.

  In the eleventh embodiment, the type of contact to be evaluated is not particularly limited. For example, a contact electrode formed by embedding a refractory metal film or a metal film in a contact hole may be used. . Also, the type of the base pattern of the contact to be evaluated (the conductor electrically connected to the lower part of the contact) is not particularly limited. For example, the gate electrode wiring layer, the source / drain impurity layer, or the lower layer metal wiring It may be a layer.

(Twelfth embodiment)
Hereinafter, a contact resistance defect evaluation apparatus (contact resistance defect monitor apparatus) according to a twelfth embodiment of the present invention, specifically, a wafer (in order to evaluate a resistance variation defect of a contact mounted on a semiconductor integrated circuit device). An evaluation apparatus provided on an evaluation wafer will be described with reference to the drawings.

  In the contact resistance failure monitoring apparatus according to the present embodiment, each chip 201 arranged at a plurality of locations (for example, 51 locations) on the wafer 200, as in the 11th embodiment (see FIG. 18B). A contact chain resistance pattern having a number of contacts (for example, 198) capable of measuring a resistance variation component that causes a resistance variation failure occurring in the contact to be evaluated is provided. Here, each contact chain resistance pattern is composed of contacts having substantially the same structure as the contact to be evaluated. Similarly to the eleventh embodiment (see FIG. 18A), each chip 201 is partitioned into a number (for example, 25,000) of blocks 202 capable of evaluating the yield of the semiconductor integrated circuit device. Inside each block 202, one contact chain resistance pattern is provided as an evaluation pattern for contact failure. Therefore, the total number of contact chain resistance patterns in this embodiment is 25000 × 51 locations = 1275000 per wafer.

  FIG. 21A is a plan view showing an example of a contact chain resistance pattern of the present embodiment. In FIG. 21A, the same members as those in the contact chain resistance pattern of the eleventh embodiment shown in FIG. Here, the number of contacts in the contact chain resistance pattern shown in FIG. 21A is n, and the distance between the contact electrodes 215 that are electrically connected by the lower layer wiring 213 (base pattern) in the contact chain resistance pattern. (Hereinafter simply referred to as the pattern length), that is, the pattern length of the semiconductor integrated circuit device to be evaluated is L.

  21B to 21D are plan views showing an example of a plurality of first calibration patterns provided in the vicinity of the contact chain resistance pattern in each block 202. FIG. Each first calibration pattern is used to calibrate the resistance value of the base pattern that determines the resistance value of the contact chain resistance pattern. In FIGS. 21B to 21D, the same members as those in the contact chain resistance pattern of the eleventh embodiment shown in FIG. Here, the first calibration pattern shown in FIG. 21B has a pattern length L1 equivalent to the pattern length L to be evaluated, and the first calibration pattern shown in FIG. 21C is from the pattern length L1. The first calibration pattern shown in FIG. 21D has a pattern length L3 longer than the pattern length L2. Note that the number of contacts of each first calibration pattern is m.

  As described above, according to the twelfth embodiment, in addition to the same effects as those of the eleventh embodiment, the following effects can be obtained. In other words, in addition to one contact chain resistance pattern, a calibration pattern having three different pattern lengths L1, L2, and L3 is provided in the same block 202, which affects the resistance value of one contact chain resistance pattern. It is possible to calibrate the variation in resistance value of the underlying pattern (for example, the polysilicon electrode wiring layer or the source / drain impurity layer). For this reason, since the resistance evaluation of the contact chain resistance pattern can be performed with high accuracy, the soft open defect can be detected with higher accuracy.

  In the twelfth embodiment, the type of the base pattern of the contact chain resistance pattern or the calibration pattern, that is, the type of the base pattern of the contact to be evaluated is not particularly limited. For example, the gate electrode wiring layer, source / drain impurities It may be a layer or a lower metal wiring layer.

  In the twelfth embodiment, the first calibration pattern group having three types of pattern lengths including the evaluation target pattern length L is used. However, the number of types of pattern lengths and the pattern lengths in the first calibration pattern group are used. The size of is not particularly limited.

(13th Embodiment)
Hereinafter, a contact resistance defect evaluation apparatus (contact resistance defect monitor apparatus) according to a thirteenth embodiment of the present invention, specifically, a wafer (in order to evaluate a resistance variation defect of a contact mounted on a semiconductor integrated circuit device) An evaluation apparatus provided on an evaluation wafer will be described with reference to the drawings.

  In the contact resistance failure monitoring apparatus according to the present embodiment, as in the twelfth embodiment, the evaluation target contacts are provided in the chips 201 arranged at a plurality of locations (for example, 51 locations) on the wafer 200. A contact chain resistance pattern having a number of contacts (for example, 198) capable of measuring a resistance variation component that causes a resistance variation failure is provided. Here, each contact chain resistance pattern is composed of contacts having substantially the same structure as the contact to be evaluated. Each chip 201 is partitioned into a number (for example, 25000) of blocks 202 capable of evaluating the yield of the semiconductor integrated circuit device, and inside each block 202 is a contact chain as a contact failure evaluation pattern. One resistance pattern is provided. Therefore, the total number of contact chain resistance patterns in this embodiment is 25000 × 51 locations = 1275000 per wafer.

  FIG. 22A is a plan view showing an example of a contact chain resistance pattern of the present embodiment. In FIG. 22A, the same members as those in the contact chain resistance pattern of the eleventh embodiment shown in FIG. Here, the number of contacts of the contact chain resistance pattern shown in FIG. 22A is n, and the diameter of the contact electrode 215 constituting the contact chain resistance pattern, that is, the contact diameter of the semiconductor integrated circuit device to be evaluated is d. It is.

  22B to 22D are plan views showing a plurality of second calibration patterns provided in the vicinity of the contact chain resistance pattern in each block 202. FIG. Each second calibration pattern is used to evaluate the dependency of the contact chain resistance pattern on the contact diameter. In FIGS. 22B to 22D, the same members as those in the contact chain resistance pattern of the eleventh embodiment shown in FIG. Here, the second calibration pattern shown in FIG. 22B has a contact diameter d1 smaller than the contact diameter d to be evaluated, and the second calibration pattern shown in FIG. 22C is the contact to be evaluated. The second calibration pattern shown in FIG. 22D has a contact diameter d3 that is larger than the contact diameter d to be evaluated. The number of contacts of each second calibration pattern is m.

  As described above, according to the thirteenth embodiment, in addition to the same effects as those of the eleventh embodiment, the following effects can be obtained. That is, in order to provide calibration patterns having three different contact diameters d1, d2 and d3 in addition to one contact chain resistance pattern in the same block 202, the resistance value of each calibration pattern is measured. As a result, it is possible to calibrate the influence of the contact size variation on the resistance value of the contact chain resistance pattern in the wafer surface and in the chip region or the shot region. In addition, a margin evaluation of contact dimensions can be performed.

  In the thirteenth embodiment, the type of the base pattern of the contact chain resistance pattern or the calibration pattern, that is, the type of the base pattern of the contact to be evaluated is not particularly limited. For example, the gate electrode wiring layer, the source / drain impurities It may be a layer or a lower metal wiring layer.

  In the thirteenth embodiment, the second calibration pattern group having three types of contact diameters including the evaluation target contact diameter d is used. However, the number of types of contact diameters and the contact diameters in the second calibration pattern group are used. The size of is not particularly limited.

  In the thirteenth embodiment, the first calibration pattern group of the twelfth embodiment may be provided in the block 202 in addition to one contact chain resistance pattern and the second calibration pattern group.

(Fourteenth embodiment)
Hereinafter, a semiconductor integrated circuit device using the contact resistance failure evaluation method (contact resistance failure monitoring method) according to the fourteenth embodiment of the present invention, specifically, the contact resistance failure monitoring device according to the twelfth embodiment. A method for evaluating a resistance variation defect (soft open defect) of a contact mounted on the board will be described with reference to the drawings. Here, in the contact resistance failure monitoring apparatus according to the twelfth embodiment, in addition to one contact chain resistance pattern, a ground pattern (for example, gate electrode wiring) that determines the resistance value of the contact chain resistance pattern is included in each block. A first calibration pattern group having three different pattern lengths L1 (= evaluation target pattern length L), L2 and L3, which is used to calibrate the resistance value of the layer or the source / drain impurity layer), is provided. ing.

  First, in the first step, the contact resistance defect monitoring device according to the twelfth embodiment shown in FIGS. 21A to 21D is used to uniformly distribute within the wafer surface and within the chip region or shot region. The respective resistance values of the contact chain resistance pattern and the first calibration patterns in the arranged blocks are measured at a plurality of locations in the wafer surface and in each chip area (or in each shot area).

Next, in the second step, the resistance value of each first calibration pattern in each block measured in the first step is set to r1, r2, and r3 for the pattern lengths L1, L2, and L3, respectively, and the pattern length L1 , L2 and L3 and the resistance values r1, r2 and r3 of the first calibration patterns are plotted on the X axis and the Y axis, respectively, to create a graph. FIG. 23A is a diagram showing an example of the graph created in this way. Subsequently, from the Y-intercept value (= Rr) of the created graph, the resistance value rc per contact constituting the contact chain resistance pattern in the block is calculated.
rc = Rr / m
Calculate according to Note that m is the number of contacts of each first calibration pattern, and m = 2 in this embodiment. Here, in the calculation of the resistance value rc per contact, the resistance value of the upper pattern (for example, the upper metal wiring 216 shown in FIGS. 21A to 21D) connecting the contacts is so large that it can be ignored. It is.

  Next, in the third step, the resistance value rc per contact calculated in the second step and the contact are calculated by using the resistance value of the contact chain resistance pattern in each block measured in the first step as Rc. A graph is created by plotting the resistance value Rc of the chain resistance pattern on the X axis and the Y axis, respectively. FIG. 23B is a diagram showing an example of the graph created in this way. As can be seen from FIG. 23B, there is a variation in the contact diameter of the contact chain resistance pattern in the wafer surface, in the chip region, or in the shot region, so that the resistance value rc per contact varies. . Therefore, by plotting the resistance value Rc of the contact chain resistance pattern with respect to such variation in rc, it is possible to extract a contact chain resistance pattern in which the resistance value Rc increases discretely from the measurement results. Become. In other words, when the resistance value of one contact in the contact chain resistance pattern rises and a resistance rise failure (soft open failure) occurs, the contact chain resistance pattern in which the resistance rise failure occurs is extracted It becomes possible to do.

  Therefore, in the fourth step subsequent to the third step, contact points are extracted by extracting points at which the resistance value Rc of the contact chain resistance pattern has increased discretely based on the graph created in the third step. Detects soft open failure of chain resistance pattern.

  As described above, according to the fourteenth embodiment, the same effect as the twelfth embodiment can be obtained by introducing the calibration pattern of the twelfth embodiment. Specifically, by using the calibration pattern of the twelfth embodiment having a different pattern length, the component of the resistance value of the base pattern (for example, the polysilicon electrode wiring layer or the source / drain impurity layer) is removed, Rr (Y intercept value) or rc (resistance value per contact) at the measurement point (block) can be obtained with high accuracy. As a result, it is possible to eliminate the influence of contact diameter variation or the like on the resistance value of the contact chain resistance pattern in the wafer surface, the chip region, or the shot region. Therefore, it is possible to plot the resistance value of the contact chain resistance pattern in consideration of the contact diameter dependency, and as a result, it is possible to detect a soft open defect of the contact chain resistance pattern. Further, the yield evaluation of the semiconductor integrated circuit device can be performed by detecting the number of soft open defects. In other words, it is possible to evaluate the influence of the soft open defect on the yield of the semiconductor integrated circuit device to be manufactured.

In the fourteenth embodiment, instead of plotting the resistance value Rc of the contact chain resistance pattern against the resistance value rc per contact in the third step, the following processing may be performed. . That is, using the resistance value rc per contact calculated in the second step and the contact resistance value (predetermined value) ρc per unit area, the electrical equivalent contact diameter d in each block is
d = (ρc / (π × rc)) ^1/2 (Expression 6)
Calculate according to Subsequently, assuming that the resistance value of the contact chain resistance pattern in each block measured in the first step is Rc, the calculated electrical conversion contact diameter d or its reciprocal and the resistance value Rc of the contact chain resistance pattern are respectively X-axis. And create a graph by plotting on the Y axis. FIG. 23C shows an example of the graph created in this way. In FIG. 23C, the reciprocal 1 / d of the electrical equivalent contact diameter d is plotted on the X axis, and the resistance value Rc of the contact chain resistance pattern is plotted on the Y axis. Based on the graph created in the third step in this way, it is also possible to extract the point where the resistance value Rc of the contact chain resistance pattern has increased discretely in the fourth step. Open defects can be detected.

(Fifteenth embodiment)
Hereinafter, a semiconductor integrated circuit device using the contact resistance failure evaluation method (contact resistance failure monitoring method) according to the fifteenth embodiment of the present invention, specifically, the contact resistance failure monitoring device according to the twelfth embodiment. A method for evaluating a resistance variation defect (soft open defect) of a contact mounted on the board will be described with reference to the drawings. Here, in the contact resistance failure monitoring apparatus according to the twelfth embodiment, in addition to one contact chain resistance pattern, a ground pattern (for example, gate electrode wiring) that determines the resistance value of the contact chain resistance pattern is included in each block. A first calibration pattern group having three different pattern lengths L1 (= evaluation target pattern length L), L2 and L3, which is used to calibrate the resistance value of the layer or the source / drain impurity layer), is provided. ing.

  First, as in the fourteenth embodiment, in the first step, using the contact resistance defect monitoring device according to the twelfth embodiment shown in FIGS. The resistance values of the contact chain resistance pattern and each of the above-described first calibration patterns in each block arranged uniformly in the area or in the shot area are set in the wafer surface and in each chip area (or in each shot area). ) At multiple points.

  Next, in the second step, the resistance value of each first calibration pattern in each block measured in the first step is set to r1, r2, and r3 for the pattern lengths L1, L2, and L3, respectively, and the pattern length L1 , L2 and L3 and the resistance values r1, r2 and r3 of the first calibration patterns are plotted on the X axis and the Y axis, respectively, to create a graph. The graph created in this way is the same as the graph of the fourteenth embodiment shown in FIG. Subsequently, the resistance value per unit length of the base pattern of the contact chain resistance pattern in the block is calculated from the slope of the created graph. Here, in the calculation of the resistance value per unit length of the base pattern, the resistance value of the upper pattern (for example, the upper metal wiring 216 shown in FIGS. 21A to 21D) that connects the contacts is large enough to be ignored. That's it. In other words, the slope of the created graph indicates the resistance value (resistance value per unit length) of the base pattern excluding the contact resistance and the resistance of the upper pattern, for example, the resistance value Rg per unit length of the gate electrode wiring layer or the source / The resistance value Rd per unit length of the drain impurity layer is shown.

Next, in the third step, the resistance value of the contact chain resistance pattern in each block measured in the first step is Rc, and all the contact chain resistance patterns in the wafer surface calculated in the second step are calculated. Assuming that the average value of the resistance value Ru per unit length of the ground pattern is Ru (Ave), the correction value Rc ′ of the resistance value Rc of the contact chain resistance pattern is
Rc ′ = Rc × Ru (Ave) / Ru (Expression 7)
Calculate according to Specifically, when the underlying pattern is a gate electrode wiring layer, Ru = Rg, Ru (Ave) = Rg (Ave), and the correction value Rc ′ of the resistance value Rc of the contact chain resistance pattern is
Rc ′ = Rc × Rg (Ave) / Rg (Formula 8)
Calculate according to When the underlying pattern is a source / drain impurity layer, Ru = Rd, Ru (Ave) = Rd (Ave), and the correction value Rc ′ of the resistance value Rc of the contact chain resistance pattern is
Rc ′ = Rc × Rd (Ave) / Rd (Formula 9)
Calculate according to

  Next, in the fourth step, a distribution map of the correction value Rc ′ calculated in the third step in the wafer surface, each chip region, or each shot region is created.

  Next, in the fifth step, by detecting the points at which the correction values Rc ′ are discretely increased based on the distribution diagram created in the fourth step, detection of resistance fluctuation defects in the contact chain resistance pattern To do.

  As described above, according to the fifteenth embodiment, similar to the fourteenth embodiment, the same effects as those of the twelfth embodiment can be obtained by using the calibration pattern of the twelfth embodiment. . Specifically, by using the calibration pattern of the twelfth embodiment with different pattern lengths, Ru (resistance value per unit length of the base pattern) at the measurement point (block) can be obtained with high accuracy. As a result, it is possible to eliminate the influence of variations in the resistance value of the base pattern on the resistance value of the contact chain resistance pattern in the wafer surface, the chip region, or the shot region. That is, since the resistance value Rc of the contact chain resistance pattern can be accurately corrected, it is possible to detect a soft open defect of the contact chain resistance pattern. Further, the yield evaluation of the semiconductor integrated circuit device can be performed by detecting the number of soft open defects. In other words, it is possible to evaluate the influence of the soft open defect on the yield of the semiconductor integrated circuit device to be manufactured.

  In the third step (especially (Expression 7) to (Expression 9)) of the fifteenth embodiment, instead of the average value Ru (Ave) (or Rg (Ave) or Rd (Ave) corresponding thereto) The average value Rushot (Ave) of the resistance value Ru per unit length of the base pattern of all the contact chain resistance patterns in one of the chip regions or one of the shot regions calculated in the second step (or corresponding to it) Rgshot (Ave) or Rdshot (Ave)), or the average value Rublock (Ave) () of the resistance value Ru per unit length of the base pattern of all the contact chain resistance patterns in one of the blocks calculated in the second step. Alternatively, Rgblock (Ave) or Rdblock (Ave)) corresponding thereto may be used.

(Sixteenth embodiment)
Hereinafter, a method of manufacturing a contact resistance failure evaluation device (contact resistance failure monitoring device) according to the sixteenth embodiment of the present invention, specifically, a contact in the contact resistance failure monitoring device according to the twelfth or thirteenth embodiment. A method for forming a chain resistance pattern and a calibration pattern (or at least one calibration pattern when there are a plurality of types) will be described with reference to the drawings.

  FIGS. 24A to 24E are cross-sectional views showing respective steps of the method of manufacturing the contact resistance failure monitoring apparatus according to the sixteenth embodiment.

  First, as shown in FIG. 24A, after an insulating film 252 is formed on a silicon substrate 251 made of an evaluation wafer, a first conductive film made of, for example, a polysilicon film or an amorphous silicon film is formed on the insulating film 252. A body film 253 is deposited.

  Subsequently, as shown in FIG. 24B, after forming a resist pattern (not shown) that covers the contact chain resistance pattern formation region and the calibration pattern formation region using a lithography process, the resist pattern is used as a mask. By etching the first conductor film 253, the base pattern 253A of the contact chain resistance pattern and the calibration pattern is formed. Although illustration is omitted here, a step of forming a sidewall insulating film on the side surface of the base pattern 253A or a step of siliciding the upper portion of the base pattern 253A is performed as necessary.

  Subsequently, as shown in FIG. 24C, an interlayer insulating film 254 is deposited on the silicon substrate 251 on which the base pattern 253A is formed.

  Next, as shown in FIG. 24D, after forming a resist pattern (not shown) that covers the contact formation region using a lithography process, the interlayer insulating film 254 is dry-etched using the resist pattern as a mask. To form a plurality of contact holes reaching the respective underlying patterns 253A. Thereafter, a second conductor film made of, for example, a refractory metal film is embedded in each contact hole, and the second conductor film embedded in each contact hole is left, and the outside of each contact hole is left. The second conductor film, that is, the second conductor film on the interlayer insulating film 254 is removed by CMP to form a plurality of contact electrodes 255.

  Finally, as shown in FIG. 24E, after depositing a third conductor film made of a metal film for wiring formation on each contact electrode 255 and on the interlayer insulating film 254, a lithography process is performed. After forming a resist pattern (not shown) covering the wiring formation region using the resist pattern, the third conductive film is dry-etched using the resist pattern as a mask to electrically connect to each contact electrode 255 A plurality of upper layer metal wirings 256 are formed. As a result, a contact chain resistance pattern and a calibration pattern in which a plurality of base patterns 253A and a plurality of upper metal wirings 256 are connected by a plurality of contact electrodes 255 are completed.

  As described above, according to the sixteenth embodiment, the twelfth or thirteenth embodiment is compared with the manufacture of a semiconductor integrated circuit device (including MOS transistor formation, contact formation, or multilayer wiring formation). Such a contact resistance defect monitoring device can be manufactured in a very short process TAT. That is, the step of patterning the first conductive film 253 to form the base pattern 253A, the step of patterning the interlayer insulating film 254 to form a contact hole, and the step of forming the upper metal wiring 256 The contact resistance defect monitoring device can be manufactured by only a minimum of three lithography steps of patterning the third conductor film. As a result, each contact resistance defect monitoring device of the present invention can be manufactured in a very short process TAT, so that a contact resistance variation defect (soft open defect) can be evaluated early and easily, so that the yield of the semiconductor integrated circuit device can be improved. It is possible to quickly evaluate the impact of soft open defects. In other words, the evaluation result of the soft open defect can be fed back to the process countermeasures in an early and timely manner.

  In this embodiment, the silicon substrate 251 that is an evaluation wafer is used, but it goes without saying that the evaluation wafer is not limited to a semiconductor substrate.

  In the present embodiment, the contact electrode 255 is formed by making contact and embedding a refractory metal film in the contact hole. However, the type of contact is not particularly limited, and instead of the contact electrode 255, The contact electrode may be formed by embedding a metal film such as copper in the contact hole. Also, the type of the base pattern 253A is not particularly limited, and instead of the gate electrode wiring layer made of a polysilicon layer or an amorphous silicon layer, for example, a source / drain impurity layer or a lower metal wiring layer made of aluminum, copper or the like May be formed.

  The present invention relates to an evaluation device for resistance failure or contact failure, an evaluation method using the same, and a method of manufacturing the evaluation device, and detects a resistance rise failure (soft open failure) of a resistance element or contact mounted on an integrated circuit device. This is useful when evaluating the influence of soft open defects on the yield of integrated circuit devices.

(A) is a top view of 1-chip area | region of the resistance defect monitoring apparatus based on the 1st Embodiment of this invention, (b) is a resistance defect monitoring apparatus shown to (a) uniformly arrange | positioned in a wafer surface. (C) and (d) are diagrams each showing an example of a resistance failure evaluation pattern in the resistance failure monitoring device shown in (a), and (e) and (f) are ( It is a figure for demonstrating the setting method of the length of the resistance defect evaluation pattern shown to c), (g) is for demonstrating the number of resistance defect evaluation patterns which need to be provided in the inside of the chip | tip shown to (a). FIG. (A)-(f) is a figure for demonstrating the setting method of the length of the resistance defect evaluation pattern in the resistance defect monitoring apparatus which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the setting method of the number of resistance defect evaluation patterns in 1 chip area | region of the resistance defect monitoring apparatus which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating the shot area | region in the resistance defect monitoring apparatus which concerns on the 1st Embodiment of this invention. (A) is a top view of 1-chip area | region of the resistance defect monitoring apparatus based on the 2nd Embodiment of this invention, (b) is a resistance defect monitoring apparatus shown to (a) uniformly arrange | positioned in a wafer surface. (C) is a figure which shows the mode in the block in the resistance defect monitoring apparatus shown to (a). (A) And (b) is a figure which shows a mode that the common probing pad was provided in the resistance defect evaluation pattern and calibration pattern in the resistance defect monitor apparatus which concerns on the 2nd Embodiment of this invention. (A) And (b) is a figure which shows the mode in the block in the resistance defect monitoring apparatus based on the 3rd Embodiment of this invention, respectively. (A) is a top view of the 1-chip area | region of the resistance defect monitoring apparatus based on the 4th Embodiment of this invention, (b) is a resistance defect monitoring apparatus shown to (a) uniformly arrange | positioned in a wafer surface. (C) is a figure which shows the state in the block in the resistance defect monitoring apparatus shown to (a), (d) and (e) are resistance defect monitoring apparatuses shown to (a) (F) and (g) are a plan view and a sectional view of a first calibration pattern in the resistance defect monitoring device shown in (a), (h) And (i) are a plan view and a cross-sectional view of a second calibration pattern in the resistance defect monitoring device shown in (a). It is a figure which shows the mode in the block in the resistance defect monitoring apparatus which concerns on the 5th Embodiment of this invention. It is a figure which shows the mode in the block in the resistance defect monitoring apparatus which concerns on the 6th Embodiment of this invention. (A) is a figure which shows distribution in the wafer surface of the electrical conversion dimension ECD calculated at the 2nd process in the resistance defect monitoring method which concerns on the 7th Embodiment of this invention, (b) and (c) These are figures which show the distribution in the wafer center chip | tip of the said ECD, and the distribution in the wafer notch side chip | tip. (A) And (b) is a figure which shows the graph obtained by the plot in the 3rd process in the resistance defect monitoring method which concerns on the 7th Embodiment of this invention, respectively. (A)-(e) is a figure for demonstrating the difference of the resistance value before and behind correction | amendment with respect to the resistance value of the resistance defect evaluation pattern in the resistance defect monitoring method which concerns on the 8th Embodiment of this invention. . (A) is a figure which shows the wafer surface distribution of the resistance value (before correction | amendment) of the resistance defect evaluation pattern measured at the 1st process in the resistance defect monitoring method which concerns on the 8th Embodiment of this invention, ( b) is the in-wafer surface of the correction value RR ′ (1) (dimension correction value) of the resistance value of the resistance defect evaluation pattern calculated in the second step in the resistance defect monitoring method according to the eighth embodiment of the present invention. It is a figure which shows distribution. (A) Wafer of resistance value correction value RR ′ (2) (sheet resistance correction value) of resistance defect evaluation pattern calculated in the second step in the resistance defect monitoring method according to the eighth embodiment of the present invention; It is a figure which shows in-plane distribution, (b) is correction value RR '(3) of the resistance value of the resistance defect evaluation pattern calculated at the 2nd process in the resistance defect monitoring method concerning the 8th Embodiment of this invention. FIG. 6 is a diagram showing a distribution within a wafer surface (value obtained by correcting a dimension and a sheet resistance). (A)-(g) is sectional drawing which shows each process of the manufacturing method of the resistance defect monitor apparatus which concerns on the 9th Embodiment of this invention. (A)-(h) is sectional drawing which shows each process of the manufacturing method of the resistance defect monitor apparatus which concerns on the 10th Embodiment of this invention. (A) is a top view of 1-chip area | region of the contact resistance defect monitoring apparatus based on the 11th Embodiment of this invention, (b) is a contact resistance defect monitoring apparatus shown to (a) uniformly in a wafer surface It is a figure which shows a mode that it has arrange | positioned, (c) is a top view which shows an example of the contact chain resistance pattern in the resistance defect monitoring apparatus shown to (a), (d) is cc 'of (c). It is sectional drawing of a line. It is a figure for demonstrating the setting method of the number of contacts of the contact chain resistance pattern in the contact resistance defect monitoring apparatus which concerns on the 11th Embodiment of this invention. It is a figure for demonstrating the setting method of the number of contact chain resistance patterns in the 1-chip area | region of the contact resistance defect monitoring apparatus which concerns on the 11th Embodiment of this invention. (A) is a top view which shows an example of the contact chain resistance pattern in the contact resistance defect monitoring apparatus based on the 12th Embodiment of this invention, (b)-(d) is a 12th Embodiment of this invention. It is a top view which shows an example of the 1st calibration pattern group in the contact resistance defect monitoring apparatus which concerns. (A) is a top view which shows an example of the contact chain resistance pattern in the contact resistance defect monitoring apparatus based on 13th Embodiment of this invention, (b)-(d) is 13th Embodiment of this invention. It is a top view which shows an example of the 2nd calibration pattern group in the contact resistance defect monitoring apparatus which concerns. (A) is a figure which shows an example of the graph produced at the 2nd process in the contact resistance defect monitoring method which concerns on the 14th or 15th embodiment of this invention, (b) and (c) are this, respectively. It is a figure which shows an example of the graph produced at the 3rd process in the contact resistance defect monitoring method which concerns on 14th Embodiment of invention. (A)-(e) is sectional drawing which shows each process of the manufacturing method of the contact resistance defect monitoring apparatus based on the 16th Embodiment of this invention. It is a figure which shows an example of the conventional comb-shaped (Comb) and snake-shaped (Serp) wiring pattern. (A) is a top view which shows an example of the conventional contact chain resistance pattern, (b) is sectional drawing of the a-a 'line in (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Wafer 101 Chip 101A Shot area 102 Resistance defect evaluation pattern 102a Line part 102b Terminal 103 Resistance defect 104 Polysilicon layer 105 Silicide layer 110 Semiconductor integrated circuit device 111 Resistance element 120 Block 121 Calibration pattern 121A First calibration pattern 121B Second Second calibration pattern 121C Third calibration pattern 131 Silicon substrate 132 Insulating film 133 Polysilicon electrode 134 Silicide layer 135 Side wall insulating film 136 Silicidation preventing insulating film 151 Semiconductor substrate 152 First insulating film 153 Silicon film 153A Patterning Silicon film 154 Side wall insulating film 155 Second insulating film 156 Silicide layer 161 Semiconductor substrate 161a Trench 162 First Edge film 162A Patterned first insulating film 163 Second insulating film 163A Trench isolation 164 Impurity layer 165 Third insulating film 166 Silicide layer 200 Wafer 201 Chip 202 Block 211 Substrate 212 Insulating film 213 Lower layer wiring 214 Interlayer insulating Film 215 Contact electrode 215A Defective contact electrode 216 Upper metal wiring 251 Silicon substrate 252 Insulating film 253 First conductor film 253A Base pattern 254 Interlayer insulating film 255 Contact electrode 256 Upper metal wiring

Claims (30)

Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation apparatus provided on a wafer for evaluating defects,
Each of a plurality of blocks defining each chip region or each shot region of the wafer has a length capable of measuring a resistance variation component that causes the resistance variation failure due to the disconnection of the silicide layer, and is the same as the resistance element A resistance failure evaluation pattern composed of the silicon-containing layer and the silicide layer having a width of 1 mm, and a first calibration for the calibration comprising the silicon-containing layer having the same length as the resistance failure evaluation pattern and the same width as the resistance element Pattern
The resistance defect evaluation apparatus according to claim 1, wherein the blocks are arranged uniformly in the wafer surface and in each chip area or each shot area. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation apparatus provided on a wafer for evaluating defects,
Each of a plurality of blocks defining each chip region or each shot region of the wafer has a length capable of measuring a resistance variation component that causes the resistance variation failure due to the disconnection of the silicide layer, and is the same as the resistance element A resistance failure evaluation pattern composed of the silicon-containing layer and the silicide layer having a width of 2 mm, and a second layer composed of the silicon-containing layer having the same length as that of the resistance failure evaluation pattern and a width of 5 times or more the resistance element. A calibration pattern,
The resistance defect evaluation apparatus according to claim 1, wherein the blocks are arranged uniformly in the wafer surface and in each chip area or each shot area. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation apparatus provided on a wafer for evaluating defects,
Each of a plurality of blocks defining each chip region or each shot region of the wafer has a length capable of measuring a resistance variation component that causes the resistance variation failure due to the disconnection of the silicide layer, and is the same as the resistance element A resistance failure evaluation pattern composed of the silicon-containing layer and the silicide layer of the width, and the silicon-containing layer and the silicide layer having the same length as the resistance failure evaluation pattern and a width five times or more than the resistance element A third calibration pattern consisting of:
The resistance defect evaluation apparatus according to claim 1, wherein the blocks are arranged uniformly in the wafer surface and in each chip area or each shot area. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation apparatus provided on a wafer for evaluating defects,
Each of a plurality of blocks defining each chip region or each shot region of the wafer has a length capable of measuring a resistance variation component that causes the resistance variation failure due to the disconnection of the silicide layer, and is the same as the resistance element A resistance failure evaluation pattern composed of the silicon-containing layer and the silicide layer having a width of 1 mm, and a first calibration for the calibration comprising the silicon-containing layer having the same length as the resistance failure evaluation pattern and the same width as the resistance element A second calibration pattern composed of the silicon-containing layer having the same length as the resistance defect evaluation pattern and having a width of 5 times or more the resistance element;
The resistance defect evaluation apparatus according to claim 1, wherein the blocks are arranged uniformly in the wafer surface and in each chip area or each shot area. In each block, a plurality of other resistance failure evaluation patterns including the silicon-containing layer and the silicide layer having the same length as the resistance failure evaluation pattern and two or more different widths from the resistance failure evaluation pattern; And a plurality of other first calibration patterns having the same length as the first calibration pattern and comprising the silicon-containing layer having two or more different widths from the first calibration pattern. The resistance failure evaluation apparatus according to claim 4 , wherein Each block further includes a third calibration pattern including the silicon-containing layer and the silicide layer, which has the same length as the resistance defect evaluation pattern and is at least five times as wide as the resistance element. The resistance failure evaluation apparatus according to claim 4 or 5 . Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation apparatus provided on a wafer for evaluating defects,
Each of a plurality of blocks defining each chip region or each shot region of the wafer has a length capable of measuring a resistance variation component that causes the resistance variation failure due to the disconnection of the silicide layer, and is the same as the resistance element A resistance failure evaluation pattern composed of the silicon-containing layer and the silicide layer having a width of 1 mm, and a first calibration for the calibration comprising the silicon-containing layer having the same length as the resistance failure evaluation pattern and the same width as the resistance element And a third calibration pattern comprising the silicon-containing layer and the silicide layer having the same length as the resistance defect evaluation pattern and a width of 5 times or more the resistance element,
The resistance defect evaluation apparatus according to claim 1, wherein the blocks are arranged uniformly in the wafer surface and in each chip area or each shot area. The length A of the resistance failure evaluation pattern is:
A resistance variation component that is a difference between a first resistance value of the resistance failure evaluation pattern in which resistance variation failure occurs in at least one place and a second resistance value of the resistance failure evaluation pattern in which no resistance variation failure exists It is set to be 2% or more with respect to the second resistance value,
Assuming that the total length of the resistance elements mounted on the semiconductor integrated circuit device is B, the number of the resistance defect evaluation patterns included in one of the chip regions or one of the shot regions is B / A. The resistance defect evaluation apparatus according to claim 1 , wherein the resistance defect evaluation apparatus is 1/10 or more and 10 or less. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation method for evaluating defects,
5. The resistance failure evaluation apparatus according to claim 4 , wherein each resistance value of the resistance failure evaluation pattern, the first calibration pattern, and the second calibration pattern in each block is determined in the wafer plane. And a first step of measuring at a plurality of locations in each chip area or each shot area,
The design value of the width of the second calibration pattern is DR, and the resistance values of the first calibration pattern and the second calibration pattern measured in the first step are R1 and R2, respectively. The electrical conversion dimension ECD of the resistance failure evaluation pattern in the block is
ECD = DR × R2 / R1
A second step of calculating according to
A graph is created by plotting the electrical conversion dimension ECD calculated in the second step and the resistance value R of the resistance defect evaluation pattern measured in the first step on the X axis and the Y axis, respectively. Or
The length of the resistance failure evaluation pattern is A, and the sheet resistance value Rs of the resistance failure evaluation pattern in each block is
Rs = R × ECD / A
A third step of creating a graph by plotting the calculated sheet resistance value Rs and the electrical conversion dimension ECD calculated in the second step on the Y axis and the X axis, respectively,
Based on the graph created in the third step, the resistance fluctuation of the resistance defect evaluation pattern is extracted by extracting points where the resistance value R of the resistance defect evaluation pattern or the sheet resistance value Rs is discretely increased. And a fourth step of detecting a defect. A resistance defect evaluation method, comprising: In each of the blocks, a plurality of other resistance failure evaluation patterns including the silicon-containing layer and the silicide layer having the same length as the resistance failure evaluation pattern and different widths from the resistance failure evaluation pattern. And a plurality of other first calibration patterns having the same length as the first calibration pattern and made of the silicon-containing layer having two or more different widths from the first calibration pattern. And
In the first step, the respective resistance values of the other resistance defect evaluation patterns and the other first calibration patterns in the blocks are set in the wafer surface and in the chip regions or in the respective areas. The resistance defect evaluation method according to claim 9 , comprising a step of measuring at a plurality of locations in the shot region. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation method for evaluating defects,
Using the resistance failure evaluation apparatus according to claim 1 , the respective resistance values of the resistance failure evaluation pattern and the first calibration pattern in each block are set in the wafer surface and in each chip region, or A first step of measuring at a plurality of locations in each shot region;
The resistance values of the resistance defect evaluation pattern and the first calibration pattern in each block measured in the first step are set to RR and r1, respectively, in the wafer plane measured in the first step. Assuming that the average value of the resistance values of all the first calibration patterns is r1 (Ave), the correction value RR ′ (1) of the resistance value RR of the resistance defect evaluation pattern is
RR ′ (1) = RR × r1 (Ave) / r1
A second step of calculating according to
A third step of creating a distribution map of the correction value RR ′ (1) calculated in the second step in the wafer surface, in each chip region, or in each shot region;
Based on the distribution map created in the third step, a point at which the correction value RR ′ (1) rises discretely is extracted to detect a resistance fluctuation failure in the resistance failure evaluation pattern. A method for evaluating resistance failure, comprising: a fourth step. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation method for evaluating defects,
Using the resistance failure evaluation apparatus according to claim 3 , the resistance values of the resistance failure evaluation pattern and the third calibration pattern in each block are set in the wafer surface and in each chip region, or A first step of measuring at a plurality of locations in each shot region;
The resistance values of the resistance defect evaluation pattern and the third calibration pattern in each block measured in the first step are set to RR and r3, and the wafer surface measured in the first step Assuming that the average value of the resistance values of all the third calibration patterns is r3 (Ave), the correction value RR ′ (2) of the resistance value RR of the resistance defect evaluation pattern is
RR ′ (2) = RR × r3 (Ave) / r3
A second step of calculating according to
A third step of creating a distribution map of the correction value RR ′ (2) calculated in the second step in the wafer surface, in each chip region, or in each shot region;
Based on the distribution map created in the third step, a point at which the correction value RR ′ (2) is discretely extracted is extracted to detect a resistance fluctuation failure in the resistance failure evaluation pattern. A method for evaluating resistance failure, comprising: a fourth step. Resistance variation of a resistance element which is at least one of a gate electrode wiring and a source / drain impurity layer constituting a MOS transistor mounted on a semiconductor integrated circuit device, and which includes a silicon-containing layer and a silicide layer formed thereon. An evaluation method for evaluating defects,
Using the resistance failure evaluation apparatus according to claim 7 , the resistance values of the resistance failure evaluation pattern, the first calibration pattern, and the third calibration pattern in each block are determined in the wafer plane. And a first step of measuring at a plurality of locations in each chip area or each shot area,
The resistance values of the resistance defect evaluation pattern, the first calibration pattern, and the third calibration pattern in each block measured in the first step are set to RR, r1, and r3, respectively, and the first step. R1 (Ave) and r3 (Ave) are the average values of the resistance values of all the first calibration patterns and the resistance values of all the third calibration patterns in the wafer plane measured in step The correction value RR ′ (1), the correction value RR ′ (2) and the correction value RR ′ (3) of the resistance value RR of the resistance defect evaluation pattern are respectively
RR ′ (1) = RR × r1 (Ave) / r1
RR ′ (2) = RR × r3 (Ave) / r3
RR ′ (3) = RR × r1 (Ave) × r3 (Ave) / (r1 × r3)
A second step of calculating according to
Each of the correction value RR ′ (1), the correction value RR ′ (2), and the correction value RR ′ (3) calculated in the second step within the wafer surface, within each chip region, or A third step of creating a distribution map in each shot area;
Points where the correction value RR ′ (1), the correction value RR ′ (2), and the correction value RR ′ (3) are discretely increased based on the respective distribution diagrams created in the third step. And a fourth step of detecting a resistance fluctuation defect of the resistance defect evaluation pattern by extracting the resistance defect evaluation method. In the second step, instead of the average value r1 (Ave), all of the first calibration patterns in one of the chip regions or one of the shot regions measured in the first step are used. An average value r1shot (Ave) of resistance values or an average value r1block (Ave) of resistance values of all the first calibration patterns in one of the blocks measured in the first step is used. The resistance defect evaluation method according to claim 11 or 13 . In the second step, instead of the average value r3 (Ave), all of the third calibration patterns in one of the chip regions or one of the shot regions measured in the first step An average value r3shot (Ave) of resistance values or an average value r3block (Ave) of resistance values of all the third calibration patterns in one of the blocks measured in the first step is used. The resistance defect evaluation method according to claim 12 or 13 . A method for manufacturing a resistance defect evaluation apparatus according to any one of claims 1 to 8 ,
The resistance element to be evaluated is a gate electrode wiring constituting a MOS transistor mounted on the semiconductor integrated circuit device,
Forming a first insulating film on a substrate made of the wafer;
Depositing a silicon-containing layer on the first insulating film;
Etching the silicon-containing layer using a first mask pattern, thereby patterning the silicon-containing layer into respective shapes of the resistance defect evaluation pattern and the calibration pattern;
Depositing a second insulating film for preventing silicidation after forming a sidewall on the side surface of the patterned silicon-containing layer;
Etching is performed on the second insulating film by using a second mask pattern, thereby preventing silicidation in which the second insulating film is removed and silicidation prevention in which the second insulating film remains. A step of setting an area;
And a step of forming a gate electrode wiring by forming a silicide layer on the silicon-containing layer in the silicidation region using a salicide process. A method for manufacturing a resistance defect evaluation apparatus according to any one of claims 1 to 8 ,
The resistance element to be evaluated is a source / drain impurity layer constituting a MOS transistor mounted on the semiconductor integrated circuit device,
Forming a first insulating film on a semiconductor substrate made of the wafer;
Patterning the first insulating film into respective shapes of the resistance defect evaluation pattern and the calibration pattern by etching the first insulating film using a first mask pattern; ,
Etching the semiconductor substrate using the patterned first insulating film as a mask to form a trench;
Burying a second insulating film in the trench;
Planarizing the surface of the second insulating film by CMP and then removing the first insulating film to form trench isolation;
After an impurity layer is formed by introducing impurities into the exposed surface portion of the semiconductor substrate where the trench isolation is not formed, a third insulating film for preventing silicidation is formed on the semiconductor substrate. Depositing, and
Etching is performed on the third insulating film using the second mask pattern, thereby preventing the silicidation region from which the third insulating film is removed and silicidation prevention in which the third insulating film remains. A step of setting an area;
Forming a source / drain impurity layer by forming a silicide layer above the impurity layer in the silicidation region using a salicide process. A method for manufacturing a resistance defect evaluation apparatus provided on a wafer in order to evaluate a resistance variation defect of a resistance element mounted on a semiconductor integrated circuit device,
A resistance defect evaluation pattern having a length capable of measuring a resistance variation component that causes the resistance variation defect, and a resistance value of the resistance defect evaluation pattern in each of a plurality of blocks that divide each chip region or each shot region of the wafer. A calibration pattern used to calibrate at least one of dimensions, film thickness and resistivity to determine
Each block is uniformly arranged in the wafer surface and in each chip area or each shot area,
The resistance element to be evaluated is a gate electrode wiring constituting a MOS transistor mounted on the semiconductor integrated circuit device,
Forming a first insulating film on a substrate made of the wafer;
Depositing a silicon-containing layer on the first insulating film;
Etching the silicon-containing layer using a first mask pattern, thereby patterning the silicon-containing layer into respective shapes of the resistance defect evaluation pattern and the calibration pattern;
Depositing a second insulating film for preventing silicidation after forming a sidewall on the side surface of the patterned silicon-containing layer;
Etching is performed on the second insulating film by using a second mask pattern, thereby preventing silicidation in which the second insulating film is removed and silicidation prevention in which the second insulating film remains. A step of setting an area;
And a step of forming a gate electrode wiring by forming a silicide layer on the silicon-containing layer in the silicidation region using a salicide process. A method for manufacturing a resistance defect evaluation apparatus provided on a wafer in order to evaluate a resistance variation defect of a resistance element mounted on a semiconductor integrated circuit device,
A resistance defect evaluation pattern having a length capable of measuring a resistance variation component that causes the resistance variation defect, and a resistance value of the resistance defect evaluation pattern in each of a plurality of blocks that divide each chip region or each shot region of the wafer. A calibration pattern used to calibrate at least one of dimensions, film thickness and resistivity to determine
Each block is uniformly arranged in the wafer surface and in each chip area or each shot area,
The resistance element to be evaluated is a source / drain impurity layer constituting a MOS transistor mounted on the semiconductor integrated circuit device,
Forming a first insulating film on a semiconductor substrate made of the wafer;
Patterning the first insulating film into respective shapes of the resistance defect evaluation pattern and the calibration pattern by etching the first insulating film using a first mask pattern; ,
Etching the semiconductor substrate using the patterned first insulating film as a mask to form a trench;
Burying a second insulating film in the trench;
Planarizing the surface of the second insulating film by CMP and then removing the first insulating film to form trench isolation;
After an impurity layer is formed by introducing impurities into the exposed surface portion of the semiconductor substrate where the trench isolation is not formed, a third insulating film for preventing silicidation is formed on the semiconductor substrate. Depositing, and
Etching is performed on the third insulating film using the second mask pattern, thereby preventing the silicidation region from which the third insulating film is removed and silicidation prevention in which the third insulating film remains. A step of setting an area;
Forming a source / drain impurity layer by forming a silicide layer above the impurity layer in the silicidation region using a salicide process. When the length of the resistance defect evaluation pattern is A and the total length of the resistance elements mounted on the semiconductor integrated circuit device is B, the chip is included in one of the chip regions or one of the shot regions. 20. The method for manufacturing a resistance defect evaluation apparatus according to claim 18, wherein the number of resistance defect evaluation patterns is 1/100 times or more and 10 times or less of B / A. 20. The method for manufacturing a resistance defect evaluation apparatus according to claim 18, wherein the resistance defect evaluation pattern and the calibration pattern are provided with independent probing pads. The length A of the resistance failure evaluation pattern is:
A resistance variation component that is a difference between a first resistance value of the resistance failure evaluation pattern in which resistance variation failure occurs in at least one place and a second resistance value of the resistance failure evaluation pattern in which no resistance variation failure exists The method for manufacturing a resistance defect evaluation apparatus according to any one of claims 18 to 21, wherein the resistance value is set to 2% or more with respect to the second resistance value. An evaluation apparatus provided on a wafer for evaluating a resistance variation defect of a contact mounted on a semiconductor integrated circuit device,
For each chip area of the wafer or for each shot area, a contact chain resistance pattern having a number of contacts capable of measuring a resistance variation component that causes the resistance variation failure,
The contact chain resistance included in one of the chip regions or one of the shot regions, where n is the number of contacts in the contact chain resistance pattern and N is the total number of contacts mounted on the semiconductor integrated circuit device. The number of patterns is not less than 1/10 times N / n and not more than 10 times,
The contact chain resistance pattern is disposed in each of a plurality of blocks that divide each chip region or each shot region of the wafer,
In the vicinity of the contact chain resistance pattern in each block, an inter-contact equivalent to the pattern length L between contacts used for calibrating the resistance value of the base pattern that determines the resistance value of the contact chain resistance pattern. A plurality of first calibration patterns each having a pattern length L1, an inter-contact pattern length L2 longer than the inter-contact pattern length L1, and an inter-contact pattern length L3 longer than the inter-contact pattern length L2.
Wherein each block uniformly arranged features and to Turkey Ntakuto defect evaluation apparatus that has in each of the interior of the wafer surface and the each chip area or each shot area. The contact number n of the contact chain resistance pattern is:
A resistance fluctuation component that is a difference between a first resistance value of the contact chain resistance pattern in which a resistance fluctuation defect has occurred in at least one place and a second resistance value of the contact chain resistance pattern in which the resistance fluctuation defect does not exist 24. The contact failure evaluation apparatus according to claim 23 , wherein the contact defect evaluation apparatus is set to be 1% or more with respect to the first resistance value. The contact failure evaluation apparatus according to claim 23 or 24 , wherein the contact is a contact electrode formed by embedding a refractory metal film or a metal film in a contact hole. 26. The contact failure evaluation apparatus according to claim 23 , wherein the base pattern of the contact is a gate electrode wiring layer, a source / drain impurity layer, or a lower metal wiring layer. An evaluation method for evaluating a resistance variation defect of a contact mounted on a semiconductor integrated circuit device,
24. Using the contact failure evaluation apparatus according to claim 23 , the respective resistance values of the contact chain resistance pattern and the first calibration patterns in each block are set in the wafer surface and in each chip region. Or a first step of measuring at a plurality of locations in each shot region;
The resistance value of each first calibration pattern in each block measured in the first step is set to r1, r2, and r3 for the inter-contact pattern lengths L1, L2, and L3, and the inter-contact pattern length L1. , L2 and L3 and the resistance values r1, r2 and r3 of the first calibration patterns are plotted on the X-axis and Y-axis, respectively. A second step of calculating a resistance value rc per contact constituting the contact chain resistance pattern;
The resistance value rc per contact calculated in the second step and the contact chain resistance pattern, where Rc is the resistance value of the contact chain resistance pattern in each block measured in the first step. A graph by plotting the resistance value Rc of x on the X-axis and the Y-axis, respectively, or
Using the resistance value rc per contact calculated in the second step and the contact resistance value ρc per unit area, the electrical equivalent contact diameter d in each block is
d = (ρc / (π × rc)) ^1/2
And the calculated electrical converted contact diameter d or its reciprocal and the resistance of the contact chain resistance pattern, where Rc is the resistance value of the contact chain resistance pattern in each block measured in the first step. A third step of creating a graph by plotting the values Rc on the X and Y axes respectively;
Based on the graph created in the third step, a point at which the resistance value Rc of the contact chain resistance pattern rises discretely is extracted, thereby detecting a resistance variation defect of the contact chain resistance pattern. 4. A contact failure evaluation method comprising the steps of 4. An evaluation method for evaluating a resistance variation failure of a contact mounted on a semiconductor integrated circuit device,
24. Using the contact failure evaluation apparatus according to claim 23 , the respective resistance values of the contact chain resistance pattern and the first calibration patterns in each block are set in the wafer surface and in each chip region. Or a first step of measuring at a plurality of locations in each shot region;
The resistance value of each first calibration pattern in each block measured in the first step is set to r1, r2, and r3 for the inter-contact pattern lengths L1, L2, and L3, and the inter-contact pattern length L1. , L2 and L3 and the resistance values r1, r2 and r3 of the first calibration patterns are plotted on the X-axis and Y-axis, respectively, and the value of the slope of the created graph is used to calculate the value of the block. A second step of calculating a resistance value Ru per unit length of the base pattern of the contact chain resistance pattern;
Rc is the resistance value of the contact chain resistance pattern in each block measured in the first step, and the base pattern of all the contact chain resistance patterns in the wafer surface calculated in the second step Assuming that the average value of the resistance value Ru per unit length is Ru (Ave), the correction value Rc ′ of the resistance value Rc of the contact chain resistance pattern is
Rc ′ = Rc × Ru (Ave) / Ru
A third step of calculating according to
A fourth step of creating a distribution map of the correction value Rc ′ calculated in the third step within the wafer surface or within each chip region or within each shot region;
Based on the distribution map created in the fourth step, a point where the correction value Rc ′ is discretely extracted is extracted, thereby detecting a resistance variation defect of the contact chain resistance pattern. A contact failure evaluation method comprising the steps of: In the third step, instead of the average value Ru (Ave), the contact chain resistance patterns of all the contact chain resistance patterns in one of the chip regions or one of the shot regions calculated in the second step The average value Rushot (Ave) of the resistance value Ru per unit length of the base pattern, or per unit length of the base pattern of all the contact chain resistance patterns in one of the blocks calculated in the second step The contact failure evaluation method according to claim 28 , wherein an average value Rublock (Ave) of the resistance value Ru is used. It is a manufacturing method of the contact failure evaluation device according to any one of claims 23-26 ,
Forming a base pattern of each of the contact chain resistance pattern and the calibration pattern on a substrate made of the wafer;
Forming an insulating film on the substrate on which the base pattern is formed;
Forming a plurality of holes reaching each of the base patterns in the insulating film;
Forming a plurality of contacts by embedding a conductor film in each of the holes;
And a step of forming an upper layer wiring on each of the contacts and on the insulating film.