JP2006005232A - Method of setting etching qualification, semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to confirm whether an etching qualification at the time of forming a via-hole or the like with less effort is suitable or not. <P>SOLUTION: A conductive film 2 and an interlayer insulating film 3 are formed on a semiconductor substrate 1 having a reference, a lowland which is lower than the reference, and a highland which is higher than the reference. The front surface of the interlayer insulating film 3 is flattened. By etching the interlayer insulating film 3, there are simultaneously formed first and second connection holes 3a which are located above the lowland, a third connection hole 3b which is located above the reference, and a fourth connection hole 3c which is located above the highland. The first to fourth conductors 4a to 4c are embedded in the first to fourth connection holes 3a to 3c, respectively. On the interlayer insulating film 3, there is formed an upper electrode 5b mutually connecting the first conductor 4a, the third conductor 4b and the fourth conductor 4c. A resistance between the upper electrode 5b and the first conductor 4a is measured. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an etching condition setting method, a semiconductor device manufacturing method, and a semiconductor device. In particular, the present invention relates to a method for setting etching conditions, a method for manufacturing a semiconductor device, and a semiconductor device that can determine whether or not etching conditions are appropriate when forming a connection hole with little effort.

Each drawing in FIG. 11 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device.
First, as shown in FIG. 11A, an element isolation film 102 is formed on a silicon substrate 101, and element regions are separated from each other. Next, a MOS transistor is formed in the element region. The MOS transistor includes a gate oxide film 103, a gate electrode 104, a sidewall 105, low-concentration impurity regions 106a and 106b, and impurity regions 107a and 107b.
Next, titanium silicide films 104a, 108a, and 108b are formed on the surfaces of the gate electrode 104 and the impurity regions 107a and 107b, respectively.

  Next, as illustrated in FIG. 11B, an interlayer insulating film 109 is formed over the entire surface including the top of the transistor. Next, by etching the interlayer insulating film 109, contact holes 109a and 109b located above the impurity regions 107a and 107b and contact holes (not shown) located above the gate electrode 104 are formed in the interlayer insulating film 109, respectively. Form. Next, W plugs 110 a and 110 b are embedded in the contact holes 109 a and 109 b, respectively, and W plugs (not shown) are embedded in the contact holes on the gate electrode 104.

  Next, an Al alloy film is deposited on each W plug and on the interlayer insulating film 109, and a TiN film is further deposited thereon. Next, the laminated film of the Al alloy film and the TiN film is patterned. Thus, Al alloy wirings 111a, 111b, and 111c are formed on the interlayer insulating film 109. The Al alloy wirings 111 a and 111 b are connected to the W plugs 110 a and 110 b, respectively, and the Al alloy wiring 111 c is connected to the W plug on the gate electrode 104.

  Next, as shown in FIG. 11C, a second interlayer insulating film 112 is formed on the entire surface including the top of each of the Al alloy wirings 111a to 111c. Next, by etching the second interlayer insulating film 112, the second interlayer insulating film 112 is positioned on the Al alloy wirings 111 a and 111 b and the via holes 112 a and 112 b and the Al alloy wiring 111 c, respectively. A via hole (not shown) is formed. Next, W plugs 113a and 113b are embedded in the via holes 112a and 112b, respectively, and W plugs (not shown) are embedded in the via holes on the Al alloy wiring 111c.

  Next, Al alloy wirings 114 a, 114 b and 114 c are formed on the second interlayer insulating film 112. The Al alloy wirings 114a and 114b are connected to the W plugs 113a and 113b, respectively, and the Al alloy wiring 114c is connected to the W plug on the Al alloy wiring 111c.

In the semiconductor device manufactured by the above-described process, a via hole or a contact hole (hereinafter referred to as a via hole) is required in order for each wiring to normally connect to a transistor or a wiring located below (hereinafter referred to as a transistor). It needs to be formed normally.
That is, when the via hole or the like does not penetrate the interlayer insulating film, each wiring is not connected to the transistor or the like, or the connection resistance has a high value. In addition, if the etching for forming the via hole is excessive, the TiN film of the Al alloy wiring may be damaged and the connection resistance may be increased.

  On the other hand, the thickness of the interlayer insulating films 109 and 112 varies to some extent. For this reason, in the etching process for forming a via hole or the like, it is necessary to set etching conditions (such as an etching time) so that the via hole or the like is normally formed in all the interlayer insulating films within the range of this variation. There is.

Conventionally, this etching condition has been set by producing a monitor substrate and analyzing the produced monitor wafer as follows.
First, as shown in FIG. 12A, a conductive film 122 such as a polysilicon film or an Al alloy film is formed on a silicon substrate 121. Next, an interlayer insulating film 123 is formed over the conductive film 122. At this time, the thickness of the interlayer insulating film 123 is set to the maximum value T _max within the allowable variation of the interlayer insulating film in the actual manufacturing process. Next, a connection hole 123a is formed in the interlayer insulating film 123, and a W plug 124 is embedded in the connection hole 123a.

Next, as illustrated in FIG. 12B, a conductive film 122 and an interlayer insulating film 123 are stacked in this order on another silicon substrate 121. At this time, the thickness of the interlayer insulating film 123 is set to the minimum value T _min within the allowable variation of the interlayer insulating film in the actual manufacturing process. Next, a connection hole 123a is formed in the interlayer insulating film 123, and a W plug 124 is embedded in the connection hole 123a.

  Thereafter, cross sections of each of the two types of monitor substrates are confirmed by SEM, and it is confirmed whether or not the connection holes 123a and the W plugs 124 are normally formed in each of the monitor substrates. In any monitor substrate, when the connection hole 123a and the W plug 124 are not normally formed, the etching conditions are changed and the above-described processing is performed again.

  As another etching condition setting method, there is a method of actually manufacturing a plurality of types of semiconductor devices by changing the etching amount of the interlayer insulating film, and measuring the yield of these semiconductor devices for each etching amount.

The above-described method for setting etching conditions has the following problems. First, in the method using a monitor substrate, the cross section of the monitor substrate is confirmed by SEM to confirm whether or not via holes or the like and W plugs are normally formed. This process required a lot of labor, such as polishing the monitor substrate to obtain a cross section. Further, in order to change the thickness of the interlayer insulating film, it is necessary to manufacture a plurality of monitor wafers, and more labor is required. For this reason, the number of via holes and W plugs that can be confirmed was small.
Therefore, the confirmation is insufficient and appropriate etching conditions may not be set.

In the method of actually manufacturing a semiconductor device and measuring the yield, there are factors other than via holes and W plugs that affect the yield. For this reason, it is necessary to finally confirm the cross section of the semiconductor device with an SEM and to identify the factors that have affected the yield.
Further, since it is necessary to actually manufacture a plurality of types of semiconductor devices by changing the etching amount of the interlayer insulating film, much labor is required.

  The present invention has been made in consideration of the above-described circumstances, and the purpose of the present invention is to set whether or not the etching conditions can be confirmed whether or not the etching conditions when forming a via hole or the like are appropriate with a small amount of labor. A method, a manufacturing method of a semiconductor device, and a semiconductor device are provided.

In order to solve the above-described problem, the etching condition setting method according to the present invention includes:
On the surface of the semiconductor substrate, forming a reference portion, a lowland portion that is lower than the reference portion, and a highland portion that is higher than the reference portion;
Forming a conductive film continuously on the low ground part, on the reference part and on the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, the interlayer insulating film is provided with first and second connection holes located above the low ground portion, third connection holes located above the reference portion, and the high ground. Forming a fourth connection hole located above the portion;
Embedding first to fourth conductors in each of the first to fourth connection holes;
Forming an upper electrode connecting the second conductor, the third conductor, and the fourth conductor on the interlayer insulating film; and
Measuring a resistance value between the upper electrode and the first conductor.

When the etching amount when forming the connection hole is insufficient, the first and second connection holes do not penetrate the interlayer insulating film, and the first and second conductors are not connected to the conductive film. For this reason, the measured resistance value is higher than that when the etching amount is appropriate. For this reason, it can be judged whether etching amount is insufficient based on resistance value. Further, the labor for measuring the resistance is much less than the labor for checking the cross section with SEM.
Therefore, according to this semiconductor manufacturing apparatus evaluation method, the suitability of the etching conditions for forming the connection holes can be determined with little effort.

  If the measured resistance value is higher than the reference value, it is judged that the etching amount is insufficient, and the etching conditions are adjusted so that the etching amount increases.If the measured resistance value is less than the reference value, the etching amount May be provided after the step of measuring the resistance value.

Another etching condition setting method according to the present invention is as follows:
On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film on the low ground part and the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, first and second connection holes located above the low ground portion are formed in the interlayer insulating film, and third and fourth positions located above the high ground portion are formed. Forming a connection hole of
Embedding first to fourth conductors in each of the first to fourth connection holes;
Comparing the resistance value between the first and second conductors with the resistance value between the third and fourth conductors.

  When the etching amount when forming the connection hole is insufficient, the first and second connection holes do not penetrate the interlayer insulating film, and the first and second conductors are not connected to the conductive film. For this reason, the resistance value between the first and second conductors is higher than the resistance value between the third and fourth conductors. For this reason, it can be judged whether etching amount is insufficient based on resistance value. Therefore, the suitability of the etching conditions when forming the connection holes can be determined with little effort.

After the step of comparing the resistance values, if the resistance value between the first and second conductors is higher than the resistance value between the third and fourth conductors, it is determined that the etching amount is insufficient. Then, the etching condition is adjusted so that the etching amount increases, and the difference between the resistance value between the first and second conductors and the resistance value between the third and fourth conductors is within a predetermined range. In such a case, a step of determining that the etching amount is appropriate may be further included.
In addition, an upper electrode that connects the second conductor and the third conductor is formed on the interlayer insulating film between the step of embedding the first to fourth conductors and the step of comparing the resistance values. In the step of further comprising the step of comparing the resistance values, the resistance between the first conductor and the upper electrode is measured, and the resistance between the fourth conductor and the upper electrode is measured. Good.

Another etching condition setting method according to the present invention is as follows:
On the surface of the semiconductor substrate, forming a reference portion, a lowland portion that is lower than the reference portion, and a highland portion that is higher than the reference portion;
Forming a conductive film continuously on the low ground part, on the reference part and on the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, a first connection hole located above the low ground part, a second connection hole located above the reference part, and an upper part of the high ground part are formed in the interlayer insulating film. Forming a third connection hole located at
Embedding first to third conductors in each of the first to third connection holes;
Measuring the resistance between the first and second conductors and the resistance between the second and third conductors, respectively.

Another etching condition setting method according to the present invention is as follows:
On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film on the low ground part and the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
Etching the interlayer insulating film to simultaneously form in the interlayer insulating film a first connection hole located above the low ground portion and a second connection hole located above the high ground portion; ,
Embedding first and second conductors in the first and second connection holes, respectively;
Measuring a resistance between the first conductor and the second conductor.

In the above-described semiconductor manufacturing apparatus evaluation method, the step between the low ground portion and the high ground portion is made equal to the difference between the minimum thickness and the maximum thickness of the interlayer insulating film allowed for the semiconductor device, and the surface of the interlayer insulating film is flattened. In the process, the thickness of the interlayer insulating film on the low ground portion is substantially equal to the maximum thickness of the interlayer insulating film allowed for the semiconductor device, and the thickness of the interlayer insulating film on the high ground portion is allowed for the semiconductor device. It is preferable that the thickness is substantially equal to the minimum thickness of the interlayer insulating film.
In this case, the level difference between the lowland portion and the highland portion is, for example, 150 nm or more and 200 nm or less.

Another etching condition setting method according to the present invention is as follows:
On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film on the low ground part and the high ground part;
Continuously forming the second conductive film having a higher resistance than the conductive film on the conductive film;
Forming an interlayer insulating film on the second conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, first and second connection holes located above the low ground portion are formed in the interlayer insulating film, and third and fourth positions located above the high ground portion are formed. Forming a connection hole of
Embedding first to fourth conductors in each of the first to fourth connection holes;
Measuring a first resistance value that is a resistance value between the first and second conductors and a second resistance value that is a resistance value between the third and fourth conductors, respectively; When,
Determining whether the etching amount of the interlayer insulating film is excessive based on the first resistance value and the second resistance value, and adjusting an etching condition;
It comprises.

When the etching amount of the interlayer insulating film is excessive, the third and fourth connection holes positioned above the high ground portion penetrate the second conductive film and are directly connected to the conductive film. In this case, the second resistance value is lower than when the etching amount is appropriate.
Further, when the etching amount of the interlayer insulating film is insufficient, the first and second connection holes located above the low ground portion do not penetrate the interlayer insulating film. In this case, the first resistance value is higher than when the etching amount is appropriate.
Therefore, based on the first resistance value and the second resistance value, it can be determined whether the etching amount of the interlayer insulating film is appropriate, and the etching conditions can be adjusted.

For example, when the etching amount is excessive, the first and second connection holes are appropriately formed, but the third and fourth connection holes often penetrate the second conductive film. In such a case, the second resistance value is smaller than the first resistance value, and the difference between the resistance values is within a predetermined range.
When the etching amount is insufficient, the third and fourth connection holes are appropriately formed, but the first and second connection holes often do not penetrate the interlayer insulating film. In such a case, the first resistance value is greater than the second resistance value, and the difference between these resistance values is greater than or equal to the reference value. Note that this reference value is outside the predetermined range.
In these cases, the etching conditions can be adjusted in the direction in which the etching amount decreases, or can be adjusted in the direction in which the etching amount increases.
When the conductive film is an Al alloy film, the second conductive film is a TiN film.

A method for manufacturing a semiconductor device according to the present invention includes:
Setting the etching conditions of the etching apparatus;
Forming an interlayer insulating film on the conductive film;
Forming a connection hole located on the conductive film in the interlayer insulating film by etching the interlayer insulating film using the etching apparatus;
Comprising
The step of setting the etching conditions includes:
On the surface of the semiconductor substrate, forming a reference portion, a lowland portion that is lower than the reference portion, and a highland portion that is higher than the reference portion;
A step of continuously forming a conductive film for evaluation on the reference portion, the low ground portion, and the high ground portion;
Forming an evaluation interlayer insulating film on the evaluation conductive film;
Planarizing the surface of the evaluation interlayer insulating film;
By etching the interlayer insulating film for evaluation, first and second evaluation connection holes positioned above the low ground portion and a third position positioned above the reference portion are formed in the interlayer insulating film for evaluation. Forming a connection hole for evaluation, and a fourth connection hole for evaluation located above the high altitude part;
Embedding first to fourth conductors in each of the first to fourth evaluation connection holes;
Forming an upper electrode connecting the second conductor, the third conductor, and the fourth conductor on the interlayer insulating film; and
Measuring a resistance value between the upper electrode and the first conductor;
If the measured resistance value is higher than the reference value, it is determined that the etching amount is insufficient, the etching condition is adjusted in the direction of increasing the etching amount, and when the measured resistance value is less than the reference value, And a step of determining that the etching amount is appropriate.

Another method of manufacturing a semiconductor device according to the present invention is as follows.
Setting the etching conditions of the etching apparatus;
Forming an interlayer insulating film on the conductive film;
Forming a connection hole located on the conductive film in the interlayer insulating film by etching the interlayer insulating film using the etching apparatus;
Comprising
The step of setting the etching conditions includes:
On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film for evaluation on the lowland portion and the highland portion;
Forming an evaluation interlayer insulating film on the evaluation conductive film;
Planarizing the surface of the evaluation interlayer insulating film;
By etching the evaluation interlayer insulating film, first and second evaluation connection holes located above the low ground portion are formed in the evaluation interlayer insulating film, and positioned above the high ground portion. Forming third and fourth evaluation connection holes;
Embedding first to fourth conductors in each of the first to fourth evaluation connection holes;
Comparing the resistance value between the first and second conductors with the resistance value between the third and fourth conductors;
If the resistance value between the first and second conductors is higher than the resistance value between the third and fourth conductors, it is determined that the etching amount is insufficient, and the etching conditions are When the etching amount is adjusted to increase and the difference between the resistance value between the first and second conductors and the resistance value between the third and fourth conductors is within a predetermined range, etching is performed. Determining that the amount is appropriate.

A semiconductor device according to the present invention includes:
On the surface, a semiconductor substrate in which a reference part, a lowland part that is lower than the reference part, and a highland part that is higher than the reference part are formed,
A conductive film located on the semiconductor substrate and continuously formed on the low ground part, on the reference part and on the high ground part;
An interlayer insulating film formed on the conductive film and having a planarized surface;
First and second connection holes formed in the interlayer insulating film and located above the low-ground part,
A third connection hole formed in the interlayer insulating film and located above the reference portion;
A fourth connection hole formed in the interlayer insulating film and located above the highland portion;
First to fourth conductors embedded in each of the first to fourth connection holes;
An upper electrode formed on the interlayer insulating film and connecting the second conductor, the third conductor, and the fourth conductor to each other;
It comprises.

Other semiconductor devices according to the present invention are:
On the surface, a semiconductor substrate in which a lowland part and a highland part that is higher than the lowland part are formed, and
A conductive film located on the semiconductor substrate and continuously formed on the low and high ground portions; and
An interlayer insulating film formed on the conductive film and having a planarized surface;
First and second connection holes formed in the interlayer insulating film and located above the low ground portion;
Third and fourth connection holes formed in the interlayer insulating film and located above the high-altitude portion;
First to fourth conductors embedded in each of the first to fourth connection holes;
It comprises.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The first embodiment of the present invention is a method for evaluating a semiconductor manufacturing apparatus by examining etching conditions for forming contact holes or via holes in an interlayer insulating film of a semiconductor device using a monitor wafer. 1 and 2 are cross-sectional views for explaining a method for forming a monitor wafer according to the first embodiment.

First, as shown in FIG. 1A, a photoresist film is applied on the entire surface of the silicon substrate 1, and this photoresist film is exposed and developed. As a result, a resist pattern 50 is formed on the silicon substrate 1.
Next, the silicon substrate 1 is etched using the resist pattern 50 as a mask. As a result, the reference portion 1 b is formed on the silicon substrate 1. At this time, the step between the surface of the non-etched portion of the silicon substrate 1 (corresponding to the high altitude portion) and the surface of the reference portion 1b is approximately half of the difference between the maximum allowable thickness and the minimum allowable thickness of the interlayer insulating film of the semiconductor device. To.

  Thereafter, as shown in FIG. 1B, the resist pattern 50 is removed. Next, a photoresist film is applied on the entire surface of the silicon substrate 1 including the reference portion 1b, and this photoresist film is exposed and developed. As a result, a resist pattern 52 is formed on the silicon substrate 1. The resist pattern 52 has an opening on a part of the reference portion 1b.

  Next, the silicon substrate 1 is etched using the resist pattern 52 as a mask. Thereby, a part of the reference portion 1b is further deepened, and the low-order portion 1a is formed. The step between the surface of the non-etched portion of the silicon substrate 1 and the lower portion 1a is approximately equal to or slightly larger than the difference between the maximum allowable thickness and the minimum allowable thickness of the interlayer insulating film of the semiconductor device.

  Thereafter, as shown in FIG. 1C, the resist pattern 52 is removed. Next, a conductive film is formed on the entire surface including the top of the low ground portion 1a and the reference portion 1b. This conductive film is preferably a film of the same quality as the film connected to the lower part of the contact hole or via hole in the product semiconductor device. For example, a polysilicon film, an Al alloy film, a silicide film such as Ti and Co, Ti A film, a Mo film, a W film, or a Cu film. In addition, you may be comprised from electroconductive substances other than these.

  Next, a photoresist film (not shown) is applied on the conductive film, and this photoresist film is exposed and developed. Next, the conductive film is etched using this photoresist film as a mask. Thereby, the conductive film pattern 2 is formed on the silicon substrate 1. The conductive film pattern 2 is continuous from the low ground portion 1a to the surface of the non-etched portion of the silicon substrate 1 via the reference portion 1b. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 2A, an interlayer insulating film 3 is formed on the conductive film pattern 2 and the silicon substrate 1. Next, the surface of the interlayer insulating film 3 is polished and planarized by the CMP method. Thereby, the thickness of the interlayer insulating film 3 is different between the non-etched portion of the silicon substrate 1, the reference portion 1b, and the low ground portion 1a. Specifically, the thickness of the interlayer insulating film 3 is substantially equal to the minimum allowable thickness of the interlayer insulating film in the actual semiconductor device on the non-etched portion of the silicon substrate 1, and the actual semiconductor is formed on the low ground portion 1a. It is approximately equal to the maximum allowable thickness in the device. On the reference portion 1b, the thickness of the interlayer insulating film 3 is substantially equal to the optimum thickness of the actual semiconductor device.

  Next, a photoresist film (not shown) is applied on the interlayer insulating film 3, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the interlayer insulating film 3. Next, using an etching apparatus, the interlayer insulating film 3 is etched using the resist pattern as a mask. The etching conditions (etching time, etc.) at this time are matched with the etching conditions when actually manufacturing the semiconductor device.

  Thereby, connection holes 3a, 3b, 3c are formed in the same process in the interlayer insulating film 3. A plurality of connection holes 3a are formed above the low ground portion 1a. The connection hole 3b is formed above the reference portion 1b. The connection hole 3 c is formed above the non-etched portion of the silicon substrate 1. That is, each of the connection holes 3a, 3b, and 3c is formed in a portion having a different thickness in the interlayer insulating film 3 and has a different depth. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 2B, a tungsten (W) film is deposited in each of the connection holes 3 a, 3 b, 3 c and on the interlayer insulating film 3. Next, the tungsten film is removed from the interlayer insulating film 3 by CMP or etch back. Thereby, the W plugs 4a, 4b, 4c are embedded in the connection holes 3a, 3b, 3c, respectively.

  Next, as shown in FIG. 2C, a conductive film is formed on each of the W plugs 4 a to 4 c and on the interlayer insulating film 3. This conductive film is preferably a film of the same quality as the film connected to the lower part of the contact hole or via hole in the semiconductor device to be the product. For example, a polysilicon film, an Al alloy film, a silicide film such as Ti and Co, Ti A film, a Mo film, a W film, or a Cu film. In addition, you may comprise from electroconductive substances other than this.

Next, a photoresist film (not shown) is applied on the conductive film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the conductive film. Next, the conductive film is etched using this resist pattern as a mask. Thereby, the upper electrode 5 a and the upper electrode 5 b are formed on the interlayer insulating film 3. The upper electrode 5a is located on one W plug 4a. The upper electrode 5b is formed to connect the other W plug 4a and the W plugs 4b and 4c to each other.
In this way, a monitor wafer for examining the etching conditions is formed.

Next, a method for examining the suitability of the etching conditions for the interlayer insulating film 3 using the monitor wafer shown in FIGS. 1 and 2 will be described with reference to FIG.
When the etching conditions of the interlayer insulating film 3 are appropriate, each of the connection holes 3 a to 3 c penetrates the interlayer insulating film 3. Each of the W plugs 4 a to 4 c is connected to the conductive film pattern 2. The upper electrode 5a is connected to the conductive film pattern 2 through one W plug 4a, and the upper electrode 5b is connected to the conductive film pattern 2 through the other W plug 4a and W plugs 4b and 4c, respectively. Connected. For this reason, the resistance between the upper electrode 5a and the upper electrode 5b is lower than the reference value.

  On the other hand, as shown in FIG. 3, when the etching of the interlayer insulating film 3 is insufficient, each of the connection holes 3b and 3c penetrates the interlayer insulating film 3, but the connection hole 3a penetrates the interlayer insulating film 3. do not do. For this reason, the W plug 4 a is not connected to the conductive film pattern 2. For this reason, the upper electrode 5a and the upper electrode 5b are insulated or close to an insulated state, and the resistance value is very high compared to the reference value.

Therefore, according to the present embodiment, the resistance value between the upper electrode 5a and the upper electrode 5b is measured and compared with the reference value, so that etching is insufficient when the connection hole is formed in the interlayer insulating film 3. It can be determined whether or not. The effort to measure the resistance is much less than the effort to check the cross section with SEM. In particular, in the above-described embodiment, since the upper electrodes 5a and 5b are formed on the W plugs 4a to 4c, it is easy to contact a terminal for measuring resistance. For this reason, the suitability of the etching conditions can be determined with little effort.
Therefore, more samples can be examined in a shorter time than in the prior art, and the reliability of evaluation of etching conditions is improved.

  If the measured resistance value is lower than the reference value, it is determined that the etching amount for forming the connection hole is insufficient, and the etching conditions of the etching apparatus are changed so that the etching amount increases. Thereafter, the above-described steps are repeated, and the etching conditions are evaluated again.

  If the measured resistance value is higher than the reference value, it is determined that the etching conditions for forming the connection hole are appropriate, and the etching apparatus is incorporated into the semiconductor device manufacturing line while maintaining the etching conditions. When the conductive film pattern 2 is made of polysilicon, the incorporated etching apparatus is used in the process of forming a contact hole. Further, when the conductive film pattern 2 is formed of Al alloy, Ti, Mo, W, Cu or the like, the incorporated etching apparatus is used in the process of forming the via hole.

  FIG. 4 is a cross-sectional view of a monitor wafer used in the semiconductor manufacturing apparatus evaluation method according to the second embodiment. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The monitor wafer according to the present embodiment is the same as the monitor wafer according to the first embodiment except that there is one connection hole 3a and one W plug 4a and the shape of the upper electrode formed on the interlayer insulating film 3. Is the same. That is, the silicon substrate 1 is formed with a low ground portion 1a and a reference portion 1b, and further includes a conductive film pattern 2, an interlayer insulating film 3, connection holes 3a, 3b, 3c, and W plugs 4a, 4b, 4c. Is formed. These forming methods are the same as those in the first embodiment except for the shape of the resist pattern formed on the interlayer insulating film 3.

  On the interlayer insulating film 3, upper electrodes 6a, 6b, 6c located on the W plugs 4a, 4b, 4c, respectively, are formed. The formation method of the upper electrodes 6a, 6b, 6c is the same as the formation method of the upper electrodes 5a, 5b according to the first embodiment except for the shape of the resist pattern formed on the conductive film.

  Then, the resistance between the upper electrodes 6a and 6b and the resistance between the upper electrodes 6b and 6c are measured. If the etching for forming the connection hole in the interlayer insulating film 3 is insufficient, the connection hole 3 a does not penetrate the interlayer insulating film 3, and therefore the W plug 4 a is not connected to the conductive film pattern 2. For this reason, the resistance value between the upper electrodes 6a and 6b is much higher than the normal value, that is, the reference value, and is higher than the resistance value between the upper electrodes 6b and 6c.

  Further, when the etching amount is large and insufficient, the connection hole 3 c does not penetrate the interlayer insulating film 3. For this reason, the W plug 4 c is not connected to the conductive film pattern 2. In this case, not only the resistance value between the upper electrodes 6a and 6b but also the resistance value between the upper electrodes 6b and 6c is higher than the normal value, that is, the reference value. Therefore, it can be seen that when the resistance value between the upper electrodes 6b and 6c is high, the etching deficiency is large.

Thus, according to the present embodiment, the resistance value between the upper electrodes 6a and 6b and the resistance value between the upper electrodes 6b and 6c are measured, and these resistance values are compared with the respective reference values. It can be determined whether or not the etching amount when forming the connection hole is insufficient. For this reason, the same effect as 1st Embodiment can be acquired. Further, as in the first embodiment, an etching apparatus with appropriate etching conditions can be incorporated into a semiconductor device manufacturing line.
In addition, since it is possible to examine in detail how much etching is insufficient, setting of etching conditions becomes easy.

  In addition, the resistance value between the upper electrodes 6a and 6c and the resistance value between the upper electrodes 6b and 6c may be measured, and these resistance values may be compared with respective reference values. When the etching amount is insufficient, the resistance value between the upper electrodes 6a and 6c is higher than the reference value. When the etching amount is large and insufficient, the resistance value between the upper electrodes 6a and 6c and the resistance value between the upper electrodes 6b and 6c are higher than the reference value.

FIG. 5 is a cross-sectional view for explaining a method for manufacturing a monitor wafer used in the semiconductor manufacturing apparatus evaluation method according to the third embodiment. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
First, as shown in FIG. 5A, a resist pattern 50 is formed on the silicon substrate 1, and the silicon substrate 1 is etched using the resist pattern 50 as a mask. As a result, a low ground portion 1 a is formed on the silicon substrate 1.

Thereafter, as shown in FIG. 5B, the resist pattern 50 is removed. Next, a conductive film pattern 2 is formed on the surface of the silicon substrate 1. The conductive film pattern 2 is continuous from the surface of the non-etched portion of the silicon substrate 1 to the low ground portion 1a. Next, an interlayer insulating film 3 is formed on the conductive film pattern 2 and the silicon substrate 1, and the surface of the interlayer insulating film 3 is planarized.
Next, a plurality of connection holes 3a and 3c are formed in the interlayer insulating film 3, and W plugs 4a and 4c are embedded in the connection holes 3a and 3c, respectively.
Except for these forming methods and the shape of the resist pattern formed on the interlayer insulating film 3, the present embodiment is the same as the first embodiment.

Next, as illustrated in FIG. 5C, a conductive film is formed over the interlayer insulating film 3. The conductive film is, for example, a polysilicon film, an Al alloy film, a Ti film, a Mo film, a W film, or a Cu film, but may be made of a conductive material other than these.
Next, a photoresist film is applied on the conductive film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the conductive film. Next, the conductive film is etched using this resist pattern as a mask. Thus, the conductive film is patterned, and the upper electrode 7a located on one W plug 4a, the upper electrode 7b connecting the other W plug 4a and one W plug 4c, and the other W plug 4c are located. The upper electrode 7c is formed.
In this way, a monitor wafer for examining the etching conditions is formed.

  Next, a method for examining the suitability of the etching conditions of the interlayer insulating film 3 using the monitor wafer shown in FIG. 5 will be described with reference to each drawing of FIG. First, as shown in FIG. 6A, the resistance value between the upper electrodes 7a and 7b is measured. Next, as shown in FIG. 6B, the resistance value between the upper electrodes 7b and 7c is measured. Then, the two measured resistance values are compared.

  As shown in FIGS. 6A and 6B, when the etching of the interlayer insulating film 3 at the time of forming the connection hole is insufficient, the connection hole 3 a does not penetrate the interlayer insulating film 3. For this reason, the W plug 4 a is not connected to the conductive film pattern 2. Therefore, the upper electrode 7a and the conductive film pattern 2 are not connected, and the resistance value between the upper electrodes 7a and 7b is higher than the resistance value between the upper electrodes 7b and 7c, and the difference between them is equal to or greater than the reference value. .

  On the other hand, as shown in FIG. 5C, when the etching conditions of the interlayer insulating film 3 at the time of forming the connection hole are appropriate, each of the connection holes 3a and 3c penetrates the interlayer insulating film 3, and the W plug 4a, Each of 4 c is connected to conductive film pattern 2. For this reason, the resistance between the upper electrodes 7a and 7b and the resistance between the upper electrodes 7b and 7c each show a low value, and the difference between these resistance values is below the reference value.

Therefore, by comparing the resistance value between the upper electrodes 7a and 7b and the resistance value between the upper electrodes 7b and 7c, it can be detected that etching of the interlayer insulating film 3 is insufficient.
As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, as in the first embodiment, an etching apparatus with appropriate etching conditions can be incorporated into a semiconductor device manufacturing line.

  FIG. 7 is a cross-sectional view for explaining a method for manufacturing a monitor wafer used in the semiconductor manufacturing apparatus evaluation method according to the fourth embodiment. In the following description, the same components as those in the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 7A, the low ground portion 1a is formed on the silicon substrate 1. Next, the surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide film 30 on the entire surface. Next, an Al alloy film is deposited on the entire surface of the silicon oxide film 30, and a TiN film is further deposited thereon. Next, the laminated film of the Al alloy film and the TiN film is patterned. Thus, the conductive film pattern 2 and the TiN film pattern 21 made of an Al alloy film are laminated on the silicon oxide film 30 in this order.

Next, as shown in FIG. 7B, an interlayer insulating film 3, a plurality of connection holes 3a, 3c, a plurality of W plugs 4a, 4c, and upper electrodes 7a, 7b, 7c are formed. These forming methods are the same as those in the third embodiment.
In this way, a monitor wafer for examining the etching conditions is formed.

Next, a method for examining the suitability of the etching conditions for the interlayer insulating film 3 using the monitor wafer shown in FIG. 7 will be described. First, as in the third embodiment, the resistance between the upper electrodes 7a and 7b and the resistance between the upper electrodes 7b and 7c are measured. Then, the two measured resistance values are compared.
When the interlayer insulating film 3 is insufficiently etched, the resistance value between the upper electrodes 7a and 7b is higher than that when the etching amount is appropriate, and the resistance value between the upper electrodes 7b and 7c is higher. , Higher than the reference value. The reason is the same as in the third embodiment.

  Further, as shown in FIG. 8, when the interlayer insulating film 3 is over-etched, the connection hole 3c penetrates the TiN film pattern 21 and is directly connected to the conductive film pattern 2 as a lower layer. The resistance of the TiN film pattern 21 is larger than the resistance of the conductive film pattern 2 that is an Al alloy film. For this reason, when the interlayer insulating film 3 is over-etched, the resistance value between the upper electrodes 7b and 7c is lower than the resistance value between the upper electrodes 7a and 7b. In addition, the difference is small compared with the case where the etching amount is insufficient.

For this reason, when the resistance value between the upper electrodes 7a and 7b is smaller than the resistance value between the upper electrodes 7b and 7c and the difference between the resistance values is equal to or greater than the first reference value, the connection hole is formed. It is judged that the etching amount for forming is insufficient, and the etching conditions of the etching apparatus are changed so that the etching amount increases.
Further, when the resistance value between the upper electrodes 7b and 7c is lower than the resistance value between the upper electrodes 7a and 7b but within a predetermined range equal to or less than the first reference value, the etching amount for forming the connection hole Therefore, the etching condition of the etching apparatus is changed so that the etching amount is reduced.
Thereafter, the above-described steps are repeated, and the etching conditions are evaluated again.

Further, when the difference between the two measured resistance values is within the second predetermined range which is a range smaller than the first predetermined range, it is determined that the etching conditions for forming the connection hole are appropriate, While maintaining the etching conditions, the etching apparatus is incorporated into a semiconductor device manufacturing line. The incorporated etching apparatus is used in the process of forming a via hole.
Thus, according to the present embodiment, the same effect as that of the first embodiment can be obtained. It can also be detected that the interlayer insulating film 3 is over-etched.

  FIG. 9 is a cross-sectional view for explaining a monitor wafer used in the semiconductor manufacturing apparatus evaluation method according to the fifth embodiment. Hereinafter, the same components as those of the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  This monitor wafer is formed as follows. First, the low ground portion 1a is formed on the silicon substrate 1, and the conductive film pattern 2, the interlayer insulating film 3, the connection holes 3a and 3c, and the W plugs 4a and 4c are further formed. Each of the connection hole 3c and the W plug 4c is formed in a single number instead of a plurality. These forming methods are the same as those in the third embodiment except for the shape of the resist pattern on the interlayer insulating film 3.

Next, a conductive film is formed on each of the W plugs 4 a and 4 c and on the interlayer insulating film 3. The conductive film is, for example, a polysilicon film, an Al alloy film, a Ti or Co silicide film, a Ti film, a Mo film, a W film, or a Cu film, but may be made of a conductive material other than these.
Next, a photoresist film is applied on the conductive film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the conductive film. Next, the conductive film is etched using this resist pattern as a mask. Thereby, the conductive film is patterned to form the upper electrodes 10a and 10b. The upper electrode 10a is located on one W plug 4a, and the upper electrode 10b connects the other W plug 4a and the W plug 4c to each other.
In this way, a monitor wafer for examining the etching conditions is formed.

  Also in this monitor wafer, when the etching of the interlayer insulating film 3 is insufficient, the connection hole 3a does not penetrate the interlayer insulating film 3, and the W plug 4a is not connected to the conductive film pattern 2, so that the upper electrode 10a , 10b has a high resistance value. For this reason, the same effects as those of the first embodiment can be obtained in this embodiment. Further, as in the first embodiment, an etching apparatus with appropriate etching conditions can be incorporated into a semiconductor device manufacturing line.

  FIG. 10 is a cross-sectional view for explaining a monitor wafer used in the semiconductor manufacturing apparatus evaluation method according to the sixth embodiment. Hereinafter, the same components as those of the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  This monitor wafer is formed as follows. First, the low ground portion 1a is formed on the silicon substrate 1, and the conductive film pattern 2, the interlayer insulating film 3, the connection holes 3a and 3c, and the W plugs 4a and 4c are further formed. Each of the connection holes 3a, 3c and the W plugs 4a, 4c is formed one by one instead of plural. These forming methods are the same as those in the third embodiment except for the shape of the resist pattern on the interlayer insulating film 3.

Next, a conductive film is formed on each of the W plugs 4 a and 4 c and on the interlayer insulating film 3. The conductive film is, for example, a polysilicon film, an Al alloy film, a Ti or Co silicide film, a Ti film, a Mo film, a W film, or a Cu film, but may be made of a conductive material other than this.
Next, a photoresist film is applied on the conductive film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the conductive film. Next, the conductive film is etched using this resist pattern as a mask. Thereby, the conductive film is patterned to form the upper electrodes 12a and 12b. The upper electrode 12a is located on the W plug 4a, and the upper electrode 12b is located on the W plug 4c.
In this way, a monitor wafer for examining the etching conditions is formed.

  Also in this monitor wafer, when the etching of the interlayer insulating film 3 is insufficient, the connection hole 3a does not penetrate the interlayer insulating film 3, and the W plug 4a is not connected to the conductive film pattern 2, so that the upper electrode 12a , 12b increases in resistance value. For this reason, the same effects as those of the first embodiment can be obtained in this embodiment. Further, as in the first embodiment, an etching apparatus with appropriate etching conditions can be incorporated into a semiconductor device manufacturing line.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in each of the embodiments described above, the upper electrode may be embedded in the interlayer insulating film 3 by the damascene method.

  In each of the second, fifth, and sixth embodiments, the conductive film pattern 2 may be formed of an Al alloy, and a TiN film on the surface of the conductive film pattern 2 may be formed. In this manner, when the interlayer insulating film 3 is over-etched, the contact hole 3c penetrates the TiN film, so that the W plug 4c embedded in the contact hole 3c is directly connected to the conductive film pattern 2.

In this case, in the second embodiment, the resistance between the upper electrodes 6b and 6c is smaller than the resistance between the upper electrodes 6a and 6b. In the fifth embodiment, the resistance between the upper electrodes 10a and 10b is smaller than when the etching conditions are appropriate. In the sixth embodiment, the resistance between the upper electrodes 12a and 12b is smaller than when the etching conditions are appropriate.
For this reason, as in the fourth embodiment, overetching can be detected.

(A) is sectional drawing for demonstrating the formation method of the monitor wafer which concerns on 1st Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of. (A) is a cross-sectional view for explaining the next step of FIG. 1 (C), (B) is a cross-sectional view for explaining the next step of (A), and (C) is the next step of (B). Sectional drawing for demonstrating a process. FIG. 4 is a cross-sectional view for explaining a method for examining suitability of etching conditions for an interlayer insulating film 3; Sectional drawing of the monitor wafer which concerns on 2nd Embodiment. (A) is sectional drawing for demonstrating the formation method of the monitor wafer which concerns on 3rd Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of. (A) And (B) is sectional drawing for demonstrating the method of investigating the suitability of the etching conditions of the interlayer insulation film 3. FIG. (A) is sectional drawing for demonstrating the formation method of the monitor wafer which concerns on 4th Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). Sectional drawing for demonstrating the next process of. FIG. 4 is a cross-sectional view for explaining a method for examining suitability of etching conditions for an interlayer insulating film 3; Sectional drawing of the monitor wafer which concerns on 5th Embodiment. Sectional drawing of the monitor wafer which concerns on 6th Embodiment. (A) is sectional drawing for demonstrating the manufacturing method of a semiconductor device, (B) is sectional drawing for demonstrating the next process of (A), (C) demonstrates the next process of (B). Sectional drawing for. (A), (B) is sectional drawing for demonstrating the setting method of the conventional etching conditions.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101,121 ... Silicon substrate, 2 ... Conductive film pattern, 3 ... Interlayer insulation film, 3a, 3b, 3c ... Connection hole, 4a, 4b, 4c ... W plug, 5a, 5b, 6a, 6b, 6c, 7a , 7b, 7c, 10a, 10b, 12a, 12b ... upper electrode, 21 ... TiN film, 50, 52 ... resist pattern, 102 ... element isolation film, 103 ... gate oxide film, 104 ... gate electrode, 104a, 108a, 108b ... Titanium silicide film, 105 ... Side wall, 106a, 106b ... Low-concentration impurity region, 107a, 107b ... impurity region, 109 ... Interlayer insulating film, 109a, 109b ... Contact hole, 110a, 110b ... W plug, 111a, 111b, 111c ... Al alloy wiring, 112 ... second interlayer insulating film, 112a, 112b ... via hole, 113a, 13b ... W plugs, 114a, 114b, 114c ... Al alloy wiring, 122 ... conductive film, 123 ... interlayer insulation film, 123a ... connection hole, 124 ... W plugs

Claims (16)

On the surface of the semiconductor substrate, forming a reference portion, a lowland portion that is lower than the reference portion, and a highland portion that is higher than the reference portion;
Forming a conductive film continuously on the low ground part, on the reference part and on the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, the interlayer insulating film is provided with first and second connection holes located above the low ground portion, third connection holes located above the reference portion, and the high ground. Forming a fourth connection hole located above the portion;
Embedding first to fourth conductors in each of the first to fourth connection holes;
Forming an upper electrode connecting the second conductor, the third conductor, and the fourth conductor on the interlayer insulating film; and
An etching condition setting method comprising: measuring a resistance value between the upper electrode and the first conductor. After the step of measuring the resistance value,
If the measured resistance value is higher than the reference value, it is determined that the etching amount is insufficient, and the etching conditions are adjusted in the direction of increasing the etching amount,
The method for setting etching conditions according to claim 1, further comprising a step of determining that the etching amount is appropriate when the measured resistance value is equal to or less than a reference value. On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film on the low ground part and the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, first and second connection holes located above the low ground portion are formed in the interlayer insulating film, and third and fourth positions located above the high ground portion are formed. Forming a connection hole of
Embedding first to fourth conductors in each of the first to fourth connection holes;
A method for setting etching conditions, comprising: comparing a resistance value between the first and second conductors with a resistance value between the third and fourth conductors. After the step of comparing the resistance values,
If the resistance value between the first and second conductors is higher than the resistance value between the third and fourth conductors, it is determined that the etching amount is insufficient, and the etching conditions are Adjust the direction to increase the etching amount,
Determining that the etching amount is appropriate when the difference between the resistance value between the first and second conductors and the resistance value between the third and fourth conductors are within a predetermined range; The etching condition setting method according to claim 3, further comprising: An upper electrode connecting the second conductor and the third conductor is formed on the interlayer insulating film between the step of embedding the first to fourth conductors and the step of comparing the resistance values. Further comprising the step of forming
The step of comparing the resistance values includes measuring a resistance between the first conductor and the upper electrode and measuring a resistance between the fourth conductor and the upper electrode. 5. A method for setting etching conditions according to 3 or 4. On the surface of the semiconductor substrate, forming a reference portion, a lowland portion that is lower than the reference portion, and a highland portion that is higher than the reference portion;
Forming a conductive film continuously on the low ground part, on the reference part and on the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, a first connection hole located above the low ground part, a second connection hole located above the reference part, and an upper part of the high ground part are formed in the interlayer insulating film. Forming a third connection hole located at
Embedding first to third conductors in each of the first to third connection holes;
And a step of measuring the resistance between the first and second conductors and the resistance between the second and third conductors, respectively. On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film on the low ground part and the high ground part;
Forming an interlayer insulating film on the conductive film;
Planarizing the surface of the interlayer insulating film;
Etching the interlayer insulating film to simultaneously form in the interlayer insulating film a first connection hole located above the low ground portion and a second connection hole located above the high ground portion; ,
Embedding first and second conductors in the first and second connection holes, respectively;
An etching condition setting method comprising: measuring a resistance between the first conductor and the second conductor. The step between the low ground portion and the high ground portion is equal to the difference between the minimum thickness and the maximum thickness of the interlayer insulating film allowed for the semiconductor device,
In the step of planarizing the surface of the interlayer insulating film,
The thickness of the interlayer insulating film on the low-land portion is substantially equal to the maximum thickness of the interlayer insulating film allowed for the semiconductor device,
8. The etching condition setting method according to claim 1, wherein a thickness of the interlayer insulating film on the high ground portion is substantially equal to a minimum thickness of the interlayer insulating film allowed for the semiconductor device. 9.   The etching condition setting method according to claim 8, wherein a level difference between the lowland portion and the highland portion is 150 nm or more and 400 nm or less. On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film on the low ground part and the high ground part;
Continuously forming the second conductive film having a higher resistance than the conductive film on the conductive film;
Forming an interlayer insulating film on the second conductive film;
Planarizing the surface of the interlayer insulating film;
By etching the interlayer insulating film, first and second connection holes located above the low ground portion are formed in the interlayer insulating film, and third and fourth positions located above the high ground portion are formed. Forming a connection hole of
Embedding first to fourth conductors in each of the first to fourth connection holes;
Measuring a first resistance value that is a resistance value between the first and second conductors and a second resistance value that is a resistance value between the third and fourth conductors, respectively; When,
It is determined whether the etching amount of the interlayer insulating film is insufficient based on the first resistance value, and the etching amount of the interlayer insulating film is excessive based on the second resistance value. Determining whether or not, adjusting the etching conditions,
Etching condition setting method comprising: The step of adjusting the etching conditions includes:
When the first resistance value is greater than the second resistance value and the difference between the resistance values is greater than or equal to a reference value, it is determined that the etching amount of the interlayer insulating film is insufficient, and the etching conditions Is adjusted to increase the etching amount,
When the second resistance value is smaller than the first resistance value and the difference between the resistance values is within a predetermined range equal to or less than the reference value, the etching amount of the interlayer insulating film is excessive. The method for setting etching conditions according to claim 10, which is a step of judging and adjusting the etching conditions so as to reduce the etching amount. The conductive film is an Al alloy film,
The method for setting etching conditions according to claim 10 or 11, wherein the step of forming the second conductive film is a step of forming a TiN film on the surface of the Al alloy film. Setting the etching conditions of the etching apparatus;
Forming an interlayer insulating film on the conductive film;
Forming a connection hole located on the conductive film in the interlayer insulating film by etching the interlayer insulating film using the etching apparatus;
Comprising
The step of setting the etching conditions includes:
On the surface of the semiconductor substrate, forming a reference portion, a lowland portion that is lower than the reference portion, and a highland portion that is higher than the reference portion;
A step of continuously forming a conductive film for evaluation on the reference portion, the low ground portion, and the high ground portion;
Forming an evaluation interlayer insulating film on the evaluation conductive film;
Planarizing the surface of the evaluation interlayer insulating film;
By etching the interlayer insulating film for evaluation, first and second evaluation connection holes positioned above the low ground portion and a third position positioned above the reference portion are formed in the interlayer insulating film for evaluation. Forming a connection hole for evaluation, and a fourth connection hole for evaluation located above the high altitude part;
Embedding first to fourth conductors in each of the first to fourth evaluation connection holes;
Forming an upper electrode connecting the second conductor, the third conductor, and the fourth conductor on the interlayer insulating film; and
Measuring a resistance value between the upper electrode and the first conductor;
If the measured resistance value is higher than the reference value, it is determined that the etching amount is insufficient, the etching condition is adjusted in the direction of increasing the etching amount, and when the measured resistance value is less than the reference value, And a step of determining that the etching amount is appropriate. Setting the etching conditions of the etching apparatus;
Forming an interlayer insulating film on the conductive film;
Forming a connection hole located on the conductive film in the interlayer insulating film by etching the interlayer insulating film using the etching apparatus;
Comprising
The step of setting the etching conditions includes:
On the surface of the semiconductor substrate, forming a lowland part and a highland part that is higher than the lowland part, and
A step of continuously forming a conductive film for evaluation on the lowland portion and the highland portion;
Forming an evaluation interlayer insulating film on the evaluation conductive film;
Planarizing the surface of the evaluation interlayer insulating film;
By etching the evaluation interlayer insulating film, first and second evaluation connection holes located above the low ground portion are formed in the evaluation interlayer insulating film, and positioned above the high ground portion. Forming third and fourth evaluation connection holes;
Embedding first to fourth conductors in each of the first to fourth evaluation connection holes;
Comparing the resistance value between the first and second conductors with the resistance value between the third and fourth conductors;
If the resistance value between the first and second conductors is higher than the resistance value between the third and fourth conductors, it is determined that the etching amount is insufficient, and the etching conditions are When the etching amount is adjusted to increase and the difference between the resistance value between the first and second conductors and the resistance value between the third and fourth conductors is within a predetermined range, etching is performed. And a step of determining that the amount is appropriate. On the surface, a semiconductor substrate in which a reference part, a lowland part that is lower than the reference part, and a highland part that is higher than the reference part are formed,
A conductive film located on the semiconductor substrate and continuously formed on the low ground part, on the reference part and on the high ground part;
An interlayer insulating film formed on the conductive film and having a planarized surface;
First and second connection holes formed in the interlayer insulating film and located above the low-ground part,
A third connection hole formed in the interlayer insulating film and located above the reference portion;
A fourth connection hole formed in the interlayer insulating film and located above the highland portion;
First to fourth conductors embedded in each of the first to fourth connection holes;
An upper electrode formed on the interlayer insulating film and connecting the second conductor, the third conductor, and the fourth conductor to each other;
A semiconductor device comprising: On the surface, a semiconductor substrate in which a lowland part and a highland part that is higher than the lowland part are formed, and
A conductive film located on the semiconductor substrate and continuously formed on the low and high ground portions; and
An interlayer insulating film formed on the conductive film and having a planarized surface;
First and second connection holes formed in the interlayer insulating film and located above the low ground portion;
Third and fourth connection holes formed in the interlayer insulating film and located above the high-altitude portion;
First to fourth conductors embedded in each of the first to fourth connection holes;
A semiconductor device comprising:

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