JP2002094004A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of reducing dispersion of characteristics of a large-area semiconductor element and capable of monitoring the characteristics with a small-area test element. SOLUTION: In a semiconductor device, having a large-area semiconductor element 5 which is larger as compared with a test element in size, the large-area semiconductor element 5 is divided into a plurality of small-area semiconductor elements 8, which they are mutually connected. Each split semiconductor element has a correlation with the test element with respect to their characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a semiconductor element having a larger area than a test element.

[0002]

2. Description of the Related Art In an input protection circuit or an analog circuit, a transistor having a large area or a diffusion layer may be used. As an example of the large area transistor, for example,
The input protection circuit will be described.

FIG. 9 shows an example of an equivalent circuit diagram of an input protection circuit. In the input protection circuit shown in FIG. 9, a large-area transistor 1 is provided in the middle of the input wiring 6 from the pad portion 4 to the main circuit 2 in order to prevent the main circuit 2 from being broken by static electricity or the like. The transistor 1 is normally off, but when an overcurrent due to static electricity or the like is input to the pad portion 4, the transistor 1 is turned on and escapes to the ground 3 without applying the overcurrent to the main circuit 2. It has the function of protecting the circuit 2.

FIG. 10 is a plan view of the transistor 1. FIG. 11A is a plan view of the gate electrode and the source / drain diffusion layers of the transistor 1 in the portion A of FIG. Since a large current flows instantaneously in the transistor 1, a MOS transistor structure as shown in FIGS. 10 and 11, for example, is conventionally used. In the transistor 1 shown in FIGS. 10 and 11,
On the rectangular active region 20 surrounded by the element isolation insulating film (LOCOS), a plurality of gate electrodes 13a
Is arranged. The input-side wiring layer 18 is connected to the drain diffusion layer 15 located on one side of each gate electrode 13 a via the input-side contact plug 17. Further, an output-side wiring layer 19 is connected to the source diffusion layer 14 located on the other side of each gate electrode 13 a via an output-side contact plug 16.

In such a transistor 1, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 13a due to static electricity or the like, the input side wiring layer 18 and the output side wiring layer 19 pass through the channel region thereunder. The conduction state occurs, and the overcurrent is released to the ground through the output-side wiring layer 19.

In general, semiconductor wafers include
A TEG (Test Element Group) is formed. TE
G is used to evaluate a single element such as a transistor and a contact that constitutes an electronic circuit of a semiconductor chip. When forming a semiconductor chip, such a single element is individually and separately from the electronic circuit of the semiconductor chip. It is provided.

[0007] For example, the TEG may be formed on a scribe line between semiconductor chips at the time of assembling a semiconductor device, or may be formed inside a semiconductor chip.

[0008] The TEG is not used for shipment as a product, but is used, for example, for collecting management data in a mass production line. Specifically, the TEG is optimized by feeding back to each semiconductor process. It is used when doing so. It is also used for new technology development. For example, when a new device structure is to be developed, a TEG including a pattern combining various structures and dimensions may be formed for the purpose of design optimization.

LS in a semiconductor wafer inspection process
In a characteristic test of a semiconductor chip using an I tester or the like, when a defective semiconductor chip is present at a specific portion in a semiconductor wafer surface, a result of a TEG characteristic test performed in advance and an electronic circuit of the semiconductor chip are performed. By determining the correlation between abnormal parameters from the characteristic test results, the cause of the failure of the semiconductor chip is grasped.

FIG. 11B shows, for example, a large-area source diffusion layer 14 and a drain diffusion layer 1 shown in FIG.
5 shows the structure of a TEG for a transistor having 5; FIG.
In the TEG shown in FIG. 1B, a gate electrode 13b having a smaller gate electrode width than the large-area transistor shown in FIG. 11A is formed on an active region of a semiconductor substrate, and a side portion of the gate electrode 13b is formed. The semiconductor substrate of FIG.
A source diffusion layer 14a and a drain diffusion layer 15a having a smaller area than those of the source diffusion layer 14 and the drain diffusion layer 15 having a large area shown in FIG.
, An input contact plug 17 is formed, and an output contact plug 16 is formed in the source diffusion layer 14a.

As shown in FIG. 11, a large-area semiconductor element such as a transistor used in the above input protection circuit or analog circuit usually has a gate electrode 13b having a width of 10
For a TEG having a size of about μm, the gate electrode 13a
Some transistors have a width of several 100 μm, and some have a diffusion layer area several tens of times larger than that of the TEG. The transistor has a different structure from the TEG. It is necessary to determine the correlation between the large-area semiconductor element and the TEG from the ratio of the size of the diffusion layer area and the like.

[0012]

SUMMARY OF THE INVENTION However, TEG
When a semiconductor element such as a large-area transistor is formed, a deviation occurs in the processing accuracy of a gate electrode or the like in a processed shape, and the characteristics of the semiconductor element such as the large-area transistor described above. Has a problem that the characteristics deviate from the characteristics expected from the TEG.

One of the factors is that even when the same film is processed under the same conditions, the etching characteristics change in accordance with the surface area and pattern size of the film to be etched. Such phenomena include, for example, the micro-loading effect,
This is a phenomenon in which the etching characteristics such as the etching rate and the shape change according to the dimensions of the pattern. As a specific example, for example, it is known that a difference in etching characteristics occurs between a portion where patterns are dense and a portion where patterns are isolated, even if the size is the same.

Therefore, since the processing conditions for a large-area transistor are usually determined based on the processing conditions for a large number of small-sized transistors existing on a chip, the processing accuracy for a fine small-area transistor is good. In addition, the processing accuracy of a large-area transistor may be deteriorated.

As described above, when the characteristics of a large-area transistor or the like deviate from the characteristics that can be monitored from a small-area TEG due to a deviation in processing accuracy or the like, a correlation between the characteristics of the TEG and the characteristics of the transistor is obtained. Finding relationships is difficult. As a result, it becomes difficult to monitor a process abnormality or the like, and there is a problem that it is not possible to optimize a process condition for forming a desired transistor. In addition, as a result of the deterioration in processing accuracy of large-area transistors, there is also a problem that characteristics of large-area transistors vary.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and accordingly, the present invention prevents a variation in the characteristics of a large-area semiconductor element and enables monitoring from a small-area test element. The purpose is to provide.

[0017]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a semiconductor element having a larger area than a test element. Is divided into a plurality of small-area semiconductor elements having a correlation with the characteristics of the test element, and the divided semiconductor elements are connected.

Preferably, the large-area semiconductor element is divided into a plurality of small-area semiconductor elements having characteristics substantially equivalent to the characteristics of the test element, and the divided semiconductor elements are connected.

For example, as the large-area semiconductor element,
The large-area transistor is divided into a plurality of small-area transistors having a correlation with characteristics of a test element for the transistor, and the divided transistors are connected.

For example, in the large-area transistor, a semiconductor substrate having a plurality of divided regions as active regions includes a gate electrode extending on the semiconductor substrate in the plurality of active regions, A diffusion layer formed on the semiconductor substrate on the side of the gate electrode and containing a conductive impurity, and a wiring layer connecting the plurality of diffusion layers.

For example, as the large-area semiconductor element,
A semiconductor resistor having a large area, wherein the large-area semiconductor resistor is divided into a plurality of small-area semiconductor resistors having a correlation with characteristics of a test element for the semiconductor resistor; Are connected.

For example, as the large-area semiconductor element,
It has a large area capacitor, and the large area capacitor is divided into a plurality of small area capacitors having a correlation with the characteristics of the test element for the capacitor, and the divided capacitors are connected.

According to the semiconductor device of the present invention, the large-area semiconductor element is divided into a plurality of small-area semiconductor elements having a correlation with the characteristics of the test element, and the divided semiconductor elements are connected. Therefore, the characteristics of the large-area semiconductor element are close to the sum of the small-area semiconductor elements having a correlation with the characteristics of the test element, and the large-area semiconductor element has characteristics that can be expected from the characteristics of the test element. . Therefore, a correlation between the characteristics of the large-area semiconductor device and the characteristics of the test device can be obtained. The large-area semiconductor element includes a large-area transistor,
It includes a resistor, a capacitor, and the like.

[0024]

Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

First Embodiment In this embodiment, the present invention is applied to a transistor having a large-area source / drain diffusion layer and the like used in an input protection circuit, an input / output inverter, and an analog circuit. FIG. 1 is a plan view of a large-area transistor according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. The large-area transistor 5 shown in FIG.
A plurality of transistors 8 having a small area are connected to each other.

The small-area transistor 8 has a gate electrode 13a common to the small-area transistors, and has a source diffusion layer 14a and a drain diffusion layer 15a, respectively. As shown in FIG.
Is separated by an element isolation insulating film 11, and an interlayer insulating film 21 is formed to cover each small-area transistor, and the interlayer insulating film 21 has a contact reaching the drain diffusion layer 15a. A plug 17 is formed, and each drain diffusion layer 15 a is connected to the same wiring layer 18 via a contact plug 17.
Although not shown, similarly, the source diffusion layer 14a of each small-area transistor 8 is isolated by the element isolation insulating film 11, and the source diffusion layer 14a is formed in the interlayer insulating film 21.
Is formed, and the source diffusion layers 14 a are connected to the same wiring layer 19 via the contact plug 16.

FIG. 3 is a sectional view taken along the line BB 'of FIG. In the transistor 8 having a small area shown in FIG. 3, a gate electrode 13a is formed via an gate insulating film 12a on an active region of a semiconductor substrate 10 which is isolated by an element isolation insulating film 11, and the gate electrode 13a side The source diffusion layer 14a and the drain diffusion layer 15a each having a small area containing a conductive impurity are formed on a portion of the semiconductor substrate 10. An interlayer insulating film 21 is formed to cover the transistor 8 having a small area. In the interlayer insulating film 21, contact plugs (16, 17) are formed in contact holes reaching the source / drain diffusion layers (14a, 15a). Each is connected to a wiring layer (19, 18) via a contact plug (16, 17).

The small-area transistor has substantially the same structure and characteristics as a TEG (test element) formed on a semiconductor wafer. As described above, the large-area transistor 5 is different from the TEG having a normal gate electrode width of about 10 μm shown in FIG.
As shown in FIG. 7, a transistor 8 having a small area equivalent to the size of the TEG is connected.

Large-area transistor 5 according to this embodiment
Then, since the pattern equivalent to the TEG is substantially connected, the processing accuracy between the TEG and the small-area transistor 8 is extremely close to each other. Is also obtained. Therefore, since the characteristics such as the current driving capability of the large-area transistor 5 can be obtained very close to the sum of the characteristics of the TEG, it is necessary to determine the correlation between the characteristics of the TEG and the characteristics of the large-area transistor 5. This makes it possible to monitor process abnormalities and the like, and to optimize process conditions for forming a desired transistor. Further, even if the processing conditions for the large-area transistor 5 are determined based on the processing conditions for a large number of small-sized transistors existing on a chip, the large-area transistor according to the present embodiment is connected to the small-area transistors. With such a structure, the processing accuracy is improved, and as a result, it is possible to suppress variations in characteristics between the plurality of large-area transistors 5.

Next, an example of a method for manufacturing the large-area transistor according to the present embodiment will be described. First, FIG.
As shown in FIG. 1A, an element isolation insulating film 11 for isolating source / drain diffusion layers of small-area transistors is formed on a semiconductor substrate 10 of, for example, p-type silicon by a LOCOS process. This element isolation insulating film 1
In the formation process 1, for example, a silicon oxide film (not shown) is formed on the surface of the semiconductor substrate 10 by a thermal oxidation method, and a silicon nitride film (not shown) is formed on the silicon oxide film in a region other than the element isolation insulating film formation region. A film is formed, and the surface of the semiconductor substrate 10 is thermally oxidized using the silicon nitride film as an oxidation-resistant mask to form an element isolation insulating film 11. afterwards,
The element isolation insulating film 11 is formed by selectively etching away the silicon nitride film.

Next, as shown in FIG. 4B, a gate insulating film 12 made of, for example, silicon oxide is formed on the semiconductor substrate 10 by, for example, a thermal oxidation method.

Next, as shown in FIG.
PCVD (Low Pressure Chemical Vapor Deposition)
For example, a polycrystalline silicon film is deposited on the gate insulating film 12 by a method to form the gate electrode layer 13.

Next, as shown in FIG. 5D, a resist film (not shown) having a gate electrode pattern of the transistor is formed by lithography, and the gate is formed by RIE (Reactive Ion Etching). The gate electrode layer 13 and the gate insulating film 12 other than the electrode portion are removed. As a result, the gate insulating film 12a and the gate electrode 13a are formed.

Next, as shown in FIG. 5E, a resist film (not shown) having an opening in the transistor formation region is formed by lithography and the n-type impurity such as arsenic ( As ⁺ ) is ion-implanted to form an n-type source diffusion layer 14a and a drain diffusion layer 15a in the semiconductor substrate 10 on both sides of the gate electrode 13a. After that, the resist film is removed.

Next, as shown in FIG. 5F, the semiconductor substrate 10, the element isolation insulating film 11, and the gate electrode 13a
, For example, by CVD (Chemical Vapor Dep
The silicon oxide is deposited by an osition method to form an interlayer insulating film 21.

In the subsequent steps, contact holes reaching the source / drain diffusion layers (14a, 15a) are formed in the interlayer insulating film 21 by lithography technology.
The inside of the contact hole is buried with a metal such as aluminum by a sputtering method, for example, and is patterned to form the source / drain diffusion layers (14a, 15a) through the contact plug (16, 17) and the contact plug (16, 17). ) Are formed to reach the large-area transistor 5 shown in FIG.

Second Embodiment A semiconductor device according to this embodiment is one in which the present invention is applied to a semiconductor resistor. FIG. 6 is a cross-sectional view of a large-area semiconductor resistor according to the present embodiment. In the semiconductor resistance element shown in FIG. 6, a plurality of diffusion layers 31 containing, for example, n-type impurity arsenic are formed on a semiconductor substrate 10 made of, for example, p-type silicon, and openings are formed at both ends of each diffusion layer 31. An insulating film 32 having 32a is formed, and a wiring layer 33 made of aluminum or the like for electrically connecting the diffusion layers 31 to each other is formed through each opening 32a.
Diffusion layer 31 and wiring layer 3 connected to both ends of diffusion layer 31
3, a small-area semiconductor resistance element r is formed, and the small-area semiconductor resistance element r is connected in series to form a large-area semiconductor resistance element.
The small-area semiconductor resistance element r has substantially the same structure and characteristics as the TEG formed on the semiconductor wafer.

In the large-area semiconductor resistor according to the present embodiment, as shown in FIG. 6, a semiconductor resistor having the same size as the TEG is connected in series, as in the first embodiment. For example, the characteristics such as the resistance value of the large-area semiconductor resistance element become very close to the sum of the characteristics of the TEG, and it becomes easy to obtain the correlation between the characteristic of the TEG and the characteristic of the large-area semiconductor resistance element. . Therefore, it is possible to monitor a process abnormality or the like, and it is possible to optimize process conditions for forming a large-area semiconductor resistor element as intended. In addition, even if the processing conditions for a large-area semiconductor resistor are determined based on the processing conditions for a large number of small-sized semiconductor resistors existing on a chip, the large-area semiconductor resistor according to the present embodiment is
Since it has a structure in which small-area semiconductor resistance elements are connected, processing accuracy is improved, and as a result, variations in characteristics among a plurality of large-area semiconductor resistance elements can be suppressed.

Third Embodiment A semiconductor device according to this embodiment is one in which the present invention is applied to a capacitor. FIG. 7A is a plan view of a large-area capacitor according to the present embodiment.
FIG. 7B is an equivalent circuit diagram of the capacitor shown in FIG. The large-area capacitor shown in FIG.
As shown in (b), small-area capacitors are connected in parallel.

FIG. 8 is a sectional view taken along the line CC 'of FIG. 7A. In the small-area capacitor shown in FIG. 8, a diffusion layer 41 containing, for example, an arsenic of an n-type impurity is formed on a semiconductor substrate 10 made of, for example, p-type silicon, and an opening 42 a is formed at one end of the diffusion layer 41. A thin insulating film 42 is formed, and a wiring layer 45 made of aluminum or the like electrically connected to the diffusion layer 41 is formed through a contact plug 44 formed in the opening 42a. A wiring layer 46 is formed on the thin insulating film 42, and the wiring layer 46, the thin insulating film 42, and the diffusion layer 4 are formed.
1 forms a capacitor.

As shown in FIG. 7A, large-area capacitors are formed by connecting small-area capacitors having the structure shown in FIG. 8 in parallel by wiring layers (45, 46). . A small-area capacitor has substantially the same structure and characteristics as a TEG formed on a semiconductor wafer.

As shown in FIG. 7, the large-area capacitor according to the present embodiment has a structure in which capacitors having the same size as the TEG are connected in parallel, as in the first embodiment. The characteristics such as the capacitance of the capacitor become very close to the sum of the characteristics of the TEG.
It is easy to find the correlation between the characteristics of the EG and the characteristics of the large-area capacitor. Therefore, it is possible to monitor a process abnormality or the like, and to optimize a process condition for forming a capacitor having a large area as intended. In addition, even if the processing conditions for a large-area capacitor are determined based on the processing conditions for a large number of small-sized capacitors existing on a chip, the large-area capacitor according to the present embodiment is connected to the small-area capacitors. Due to the structure, the processing accuracy is improved, and as a result, it is possible to suppress variations in characteristics between a plurality of large-area capacitors.

Embodiments of the semiconductor device of the present invention are not limited to the above description. In the present embodiment, a semiconductor element such as a small-area transistor, a semiconductor resistor, and a capacitor has a structure and characteristics substantially equivalent to those of a TEG formed on a semiconductor wafer. The size and the size are not limited, and may be larger than the TEG as long as they have a structure and characteristics that have a substantial correlation with the TEG. In addition, the number of small-area semiconductor elements forming a large-area semiconductor element is not limited. Further, for example, in the second embodiment and the third embodiment as well, similarly to the first embodiment, it is possible to separate the semiconductor resistor element and the capacitor of each small area by the element isolation insulating film. Further, in the present embodiment, as an example of a large-area transistor, a transistor used for an input protection circuit or an analog circuit has been described. However, the same applies to the case where the transistor is used for other circuits. Transistor applications are possible. In addition, various changes can be made without departing from the gist of the present invention.

[0044]

According to the semiconductor device of the present invention, the correlation between the characteristics of a large-area semiconductor element and the test element can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view of a large-area transistor according to a first embodiment.

FIG. 2 is a sectional view taken along line AA ′ of FIG. 1;

FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG. 1;

FIG. 4 is a cross-sectional view showing a manufacturing process of the method for manufacturing a large-area transistor according to the first embodiment, and FIG.
5A shows the steps up to the step of forming the element isolation insulating film, FIG. 5B shows the steps up to the step of forming the gate insulating film, and FIG.

5 is a cross-sectional view showing a step subsequent to that of FIG. 4; FIG. 5D shows up to a step of forming a gate electrode and a gate insulating film; and FIG. 5E shows a step up to a step of forming a source / drain diffusion layer. , (F) show the steps up to the step of forming the interlayer insulating film.

FIG. 6 is a cross-sectional view of a large-area semiconductor resistor according to a second embodiment.

FIG. 7A is a plan view of a large-area capacitor according to a third embodiment, and FIG.
FIG. 8 shows an equivalent circuit diagram of the capacitor shown in FIG.

FIG. 8 is a sectional view taken along line CC ′ of FIG. 7;

FIG. 9 shows an example of an equivalent circuit diagram of the input protection circuit.

FIG. 10 is a plan view of a conventional large-area transistor used in the input protection circuit shown in FIG. 9;

11A is a plan view of a gate electrode and a source / drain diffusion layer of a large-area transistor in a portion A of FIG. 10; FIG.
FIG. 11A is a plan view of the test element for a large-area transistor shown in FIG.

[Explanation of symbols]

1 ... transistor, 2 ... main circuit, 3 ... ground, 4 ...
Pad portion, 6 input wiring, 10 semiconductor substrate, 11 element isolation insulating film, 12 and 12a gate insulating film, 13 gate electrode layer, 13a gate electrode, 14 and 14a source diffusion layer, 15, 15a: Drain diffusion layer, 16, 1
7 ... contact plug, 18 ... (input side) wiring layer, 19
... (output side) wiring layer, 20 ... active region, 21 ... interlayer insulating film, 31 ... diffusion layer, 32 ... insulating film, 32a ... opening, 3
3 ... wiring layer, 41 ... diffusion layer, 42 ... thin insulating film, 42
a: opening, 44: contact plug, 45, 46: wiring.

Claims (6)

[Claims] 1. A semiconductor device having a semiconductor element having a larger area than a test element, wherein the large-area semiconductor element has a plurality of small-area semiconductor elements having a correlation with characteristics of the test element. Divided into
A semiconductor device to which the divided semiconductor elements are connected. 2. The semiconductor element having a large area is divided into a plurality of small-area semiconductor elements having characteristics substantially equivalent to characteristics of the test element, and the divided semiconductor elements are connected. 13. The semiconductor device according to claim 1. 3. A large-area transistor as the large-area semiconductor element, wherein the large-area transistor is divided into a plurality of small-area transistors having a correlation with characteristics of a transistor test element; 2. The semiconductor device according to claim 1, wherein said dividing transistors are connected. 4. A large-area transistor comprising: a semiconductor substrate having a plurality of divided regions as active regions; a gate electrode extending on the semiconductor substrate in the plurality of active regions; 4. The semiconductor device according to claim 3, further comprising: a diffusion layer formed on the semiconductor substrate on the side of the gate electrode and containing a conductive impurity; and a wiring layer connecting the plurality of diffusion layers. 5. A semiconductor element having a large area as the semiconductor element having a large area, wherein the semiconductor element having a large area has a plurality of small areas having a correlation with characteristics of a test element for the semiconductor resistance element. 2. The semiconductor device according to claim 1, wherein the semiconductor resistance element is divided into the plurality of semiconductor resistance elements, and the divided semiconductor resistance elements are connected. 6. The large-area semiconductor device has a large-area capacitor, and the large-area capacitor is divided into a plurality of small-area capacitors having a correlation with characteristics of a capacitor test element. 2. The semiconductor device according to claim 1, wherein said divided capacitors are connected.