CN110335861B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN110335861B CN110335861B CN201910611279.XA CN201910611279A CN110335861B CN 110335861 B CN110335861 B CN 110335861B CN 201910611279 A CN201910611279 A CN 201910611279A CN 110335861 B CN110335861 B CN 110335861B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein a detection structure is additionally arranged on the semiconductor device, the detection structure comprises a first metal layer, at least two measuring plug arrays and a second metal layer which are sequentially formed on a cutting channel of a semiconductor substrate, the detection structure can detect whether a plug to be measured has a circuit breaking problem, the detection structure can accurately detect the circuit breaking problem of the plug to be measured, and the detection structure does not need to be confused with measurement parameters in other measurement items, so that the electrical property defect caused by the circuit breaking of the plug can be quickly and directly detected.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.
Background
WAT (Wafer acceptance test) is an electrical measurement performed on a chip after a process flow is finished, and is used to check whether each process flow meets a standard, and test items include a device characteristic test, a capacitance test, a contact resistance test, a breakdown test, and the like.
In the WAT of the flash memory, it is found that a problem of failure of various detection items occurs in a plurality of chips in a central area of a wafer, and a specific failure reason cannot be known, which affects the time for solving the problem. Analysis has shown that the problem is caused by plug opens, and therefore, a structure that can directly detect the defective semiconductor device is required.
Disclosure of Invention
The present invention provides a semiconductor device and a method for fabricating the same, which can rapidly and directly detect the electrical defect caused by the plug open circuit.
In order to solve the above problem, the present invention provides a semiconductor device comprising:
the semiconductor substrate comprises a functional region and a cutting way;
a first metal layer formed on the semiconductor substrate;
a first insulating layer formed on the first metal layer;
the plug to be measured is embedded in the first insulating layer of the functional region and is electrically connected with the first metal layer;
at least two measuring plug arrays embedded in the first insulating layer of the cutting channel and electrically connected with the first metal layer;
the second metal layer is formed on the first insulating layer, the plug to be measured and the at least two measuring plug arrays and is electrically connected with the plug to be measured and the measuring plug arrays;
the first metal layer, the at least two measuring plug arrays and the second metal layer which are positioned in the cutting channel jointly form a detection structure of the plug to be measured.
Optionally, the measurement plug arrays are connected in series.
Further, the measuring plug array includes 2nAnd the measuring plugs are provided, wherein n is more than or equal to 1 and is a positive integer.
Further, the measurement plugs in the measurement plug array are connected in series.
Furthermore, the measuring plugs in the measuring plug array are connected in series through the first metal layer or the second metal layer.
Furthermore, the plug to be measured is connected in series with the detection structure through the first metal layer.
Optionally, the scribe line further includes a second insulating layer, the second insulating layer is formed on the second metal layer, and the second insulating layer exposes the detection window of the second metal layer in the scribe line.
On the other hand, the invention also provides a manufacturing method of the semiconductor device, and the method for manufacturing the semiconductor device comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a functional region and a cutting way;
forming a first metal layer and a first insulating layer on the semiconductor substrate;
embedding a plug to be measured and at least two measuring plug arrays in the first insulating layer, wherein the plug to be measured is embedded in the first insulating layer of the functional region and is electrically connected with the first metal layer, and the at least two measuring plug arrays are embedded in the first insulating layer of the cutting channel and are electrically connected with the first metal layer;
and forming a second metal layer on the first insulating layer, the plug to be measured and the at least two measuring plug arrays, wherein the second metal layer is electrically connected with the plug to be measured and the measuring plug arrays, and the first metal layer, the at least two measuring plug arrays and the second metal layer which are positioned in the cutting channel jointly form a detection structure of the plug to be measured.
Optionally, the forming the first metal layer includes:
forming a first metal film layer on the semiconductor substrate;
forming a first patterned photoresist layer on the first metal film layer, and etching the first metal film layer by taking the first patterned photoresist layer as a mask to form the first metal layer;
and removing the patterned first photoresist layer.
Optionally, the forming the second metal layer includes:
forming a second metal film layer on the first insulating layer;
forming a second patterned photoresist layer on the second metal film layer, and etching the second metal film layer by taking the second patterned photoresist layer as a mask to form the second metal layer;
and removing the patterned second photoresist layer.
Compared with the prior art, the method has the following beneficial effects:
the invention provides a semiconductor device and a manufacturing method thereof, wherein a detection structure is additionally arranged on the semiconductor device, the detection structure comprises a first metal layer, at least two measuring plug arrays and a second metal layer which are sequentially formed on a cutting channel of a semiconductor substrate, the detection structure can detect whether the plug to be measured has a circuit breaking problem, the detection structure can accurately detect the circuit breaking problem of a single plug to be measured, and the detection structure does not need to be confused with measurement parameters in other measurement items, so that the poor electrical property caused by the circuit breaking of the plug can be quickly and directly detected.
Drawings
FIG. 1 is a schematic diagram of a plug-break in a semiconductor device;
fig. 2 is a schematic top view of a semiconductor device in accordance with an embodiment of the present invention;
FIG. 3 is a schematic side view of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention.
Description of reference numerals:
a-undesirable phenomena; i-a functional region; II, cutting a channel;
100-a semiconductor substrate; 210-a first metal layer; 220-a second metal layer; 310-a first insulating layer;
320-a second insulating layer; 410-the plug to be measured; 420-an array of measurement plugs; 421-measuring plug;
500-detection window.
Detailed Description
As described in the background art, it is found that, in the WAT of the flash memory, when the source line voltage Vsl is 4V (volts), the source line current Isl increases by a steep order of magnitude, and this problem is judged to be a short circuit somewhere. In order to find out the position of the problem, as shown in fig. 1, further performing Physical Failure Analysis (PFA) finds that the plug at the position where a single plug is electrically connected with the via has a bad phenomenon a to cause the plug to break, the break causes the via electrically connected with the word line to break, and the erasure failure is caused, thereby causing the source line current not to be read normally. In the conventional method, a structure for specially detecting the bad phenomenon of the plug at the position of the single plug electric connection path is not provided, so that the bad phenomenon cannot be directly measured, and the time for solving the problem is influenced.
Based on the above research, the present invention provides a semiconductor device and a method for manufacturing the same, wherein a detection structure is added to the semiconductor device, the detection structure comprises a first metal layer, at least two measurement plug arrays and a second metal layer which are sequentially formed on a scribe line of a semiconductor substrate, the detection structure can detect whether a plug to be measured has a disconnection problem, the detection structure can accurately detect the disconnection problem of a single plug to be measured, and the disconnection problem does not need to be confused with measurement parameters in other measurement items, so that the electrical property defect caused by the disconnection of the plug can be rapidly and directly detected.
A semiconductor device and a method of fabricating the same of the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
Fig. 2 is a schematic top view of a semiconductor device according to this embodiment; fig. 3 is a schematic structural diagram of a semiconductor device according to this embodiment. As shown in fig. 2 and 3, the semiconductor device includes a semiconductor substrate 100, a first metal layer 210, a first insulating layer 310, a plug 410 to be measured, a second metal layer 220, a second insulating layer 320, and at least two measurement plug arrays 420.
It should be noted that the first metal layer, the second metal layer, the plugs to be measured, and the at least two measurement plug arrays are not actually visible in a top view, and fig. 2 is only to show the positions and the electrical connection relationships among them from a top view. Similarly, the first metal layer 210, the second metal layer 220, the plug 410 to be measured, and the at least two measurement plug arrays 420 cannot be seen at the same time in a side view, are not on the same plane in the thickness direction of the semiconductor substrate, the components are shown on the same plane in fig. 3 only to show the positions and electrical connection relationships between them from a side view, and the positions of the components in fig. 2 and 3 do not correspond one to one.
The semiconductor substrate 100 may provide an operation platform for a subsequent process, and may be any substrate known to those skilled in the art for supporting a component of a semiconductor integrated circuit, such as a bare die, or a wafer processed by an epitaxial growth process, and in detail, the semiconductor substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate. The semiconductor substrate 100 may have a Shallow Trench Isolation (STI) therein and an active region defined by the STI for fabricating a MOS transistor. The semiconductor substrate 100 may also have a well region therein, wherein the conductivity type of the dopant ions in the well region is generally opposite to the conductivity type of the dopant ions in the subsequently formed source/drain regions. The semiconductor substrate 100 has a functional region I and a scribe line II.
The first metal layer 210 is formed on the semiconductor substrate 100 and located in the functional region and the scribe line, the first metal layer 210 located in the functional region is used for setting and electrically connecting the plugs 410 to be measured, and the first metal layer 210 located on the scribe line is used for setting and electrically connecting the measuring plug array 420. The first metal layer 210 located in the functional region and the first metal layer 210 located on the scribe line are staggered, that is, the first metal layer 210 located in the functional region and the first metal layer 210 located on the scribe line are not on the same plane in the thickness direction. The first metal layers 210 are, for example, aluminum layers, and the first metal layers 210 may be square or straight.
The first insulating layer 310 is formed on the first metal layer 210, and the plug 410 to be measured and at least two measuring plug arrays 420 are embedded in the first insulating layer 310. The plug 410 to be measured is an electrical connection path between different layers of the functional region I, and is embedded in the first insulating layer 310 of the functional region I, and is electrically connected to the first metal layer 210 of the functional region I. In the present embodiment, the plug 410 to be measured refers to a plug that can separately perform an electrical connection path between different layers of the functional region I.
At least two of the measuring plug arrays 420 are electrically connected to the first metal layer 210 on the scribe line and electrically connected to the plugs 410 to be measured, so as to perform the open circuit measurement thereon. Each of the measurement plug arrays 420 includes 2 measurement plugs 421nWherein n is more than or equal to 1 and is an integer. Specifically, when the number of at least two measurement plug arrays 420 is, for example, 1, the number of the measurement plugs 421 in the measurement plug arrays 420 may be 2, 4, 8, 16, 32, 1024, 2048, or the like; when the number of the at least two measurement plug arrays 420 is at least two, for example, taking the two measurement plug arrays 420 as an example, the number of the measurement plugs 421 in the two measurement plug arrays 420 may be the same or different, for example, each may be 2, 4, 8, 16, 32, etc., or one may be 2, 4, 8, 16, 32, etc., and the other may be 512, 1024, 2048, etc. The number of the measurement plug arrays 420 and the number of the measurement plugs 421 in each measurement plug array can be flexibly determined according to the size of the specific area, that is, at least two measurement plug arrays can be formed when the area where the measurement plug array can be formed is small, each measurement plug array can be 2, 4, 8, and so on, and at least two measurement plug arrays, for example, 7, can be formed when the area where the measurement plug array can be formed is largeThe plug array may be a mixed-size array of 2, 4, 8, 64, 128, 256, 1024, 2048, 4096, etc. At least two measuring plug arrays are adopted to fully utilize each space, so that the cutting channels of the flash memory are more reasonably distributed, and the process capability of photoetching and etching processes after the detection structure is formed can be detected. In this embodiment, the measuring plug array 420 includes two measuring plug arrays 420, one measuring plug array 420 near the plug 410 to be measured includes 2 measuring plugs 421, and one measuring plug array 420 on the side away from the plug 410 to be measured includes 4 measuring plugs 421. The adjacent measurement plug arrays 420 in at least two measurement plug arrays 420 are spaced apart, and the measurement plugs 421 in each measurement plug array 420 are isolated by the first insulating layer 310, that is, the measurement plugs 421 in each measurement plug array 420 are spaced apart, and the measurement plugs 421 in the measurement plug arrays 420 are all connected in series and finally connected in series with the plugs to be measured 421, so as to detect whether the plugs to be measured 410 have an open circuit problem, so that whether the plugs to be measured 410 are open circuit can be directly measured. The plugs 410 to be measured and the measurement plugs 421 in the at least two measurement plug arrays 420 are, for example, tungsten plugs. The second metal layer 220 is formed on the first insulating layer 310 and electrically connected to the plug 410 to be measured and the at least two measuring plug arrays 420, and the second metal layer 220 is, for example, an aluminum layer.
The series connection between the measurement plugs 421 in the measurement plug array 420, and the series connection between the measurement plugs 421 and the plugs 410 to be measured form interconnects by electrical connection with the first metal layer 210 or the second metal layer 220.
The second insulating layer 320 is formed on the second metal layer 220, the second insulating layer 320 may include a silicon oxide layer formed on the surface of the second metal layer 220 and a silicon nitride layer located on the surface of the silicon oxide layer, the silicon oxide layer has better coverage, the stress caused by the silicon nitride layer can be relieved while the second metal layer 220 is well protected, and the silicon nitride layer has good compactness and can well protect the surface of the semiconductor device for a hard film. The second insulating layer 320 exposes the detection window 500 of the second metal layer 220 in the scribe line. The detection window 500 serves as a probe detection position for detecting plug disconnection in the WAT.
The first metal layer 210, the second metal layer 220 and the at least two measuring plug arrays 420 located in the scribe line together form a detecting structure for measuring the open circuit of the plug to be measured, each detecting structure is electrically connected to one plug 410 to be measured, so that the open circuit problem of the plug 410 to be measured, which is independently electrically connected to the via, can be directly detected by the detecting structure during WAT without being confused with the measurement parameters in other measurement items, thereby quickly solving the electrical defect caused by the open circuit of the plug to be measured. Detecting an open circuit of the plug to be measured 410 includes an open circuit of the plug to be measured itself (e.g., an internal open), an open circuit between the plug to be measured and the first metal layer, and an open circuit between the plug to be measured and the second metal layer. The semiconductor device includes a plurality of plugs 410 to be measured, and each of the plugs 410 to be measured is electrically connected to a detecting structure for detecting a disconnection problem of each of the plugs 410 to be measured.
Fig. 4 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to this embodiment. As shown in fig. 4 and referring to fig. 2 and fig. 3, the present embodiment further provides a method for manufacturing a semiconductor device, including the following steps:
step S10: a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a functional region and a scribe line.
Step S20: forming a first metal layer 210 and a first insulating layer 310 on the semiconductor substrate 100, wherein a method of forming the first metal layer 210 includes the steps of:
forming a first metal film layer on the semiconductor substrate 100;
forming a patterned first photoresist layer on the first metal film layer, and etching the first metal film layer by using the patterned first photoresist layer as a mask to form the first metal layer 210;
and removing the patterned first photoresist layer.
Step S30: embedding a plug 410 to be measured and at least two measuring plug arrays 420 in the first insulating layer 310, wherein the plug 410 to be measured is located in the functional region and electrically connected to the first metal layer 210 of the functional region, and the at least two measuring plug arrays 420 are located in the scribe line and electrically connected to the first metal layer 210 of the scribe line;
step S40: forming a second metal layer 220 on the first insulating layer 310, the plugs to be measured 410 and the at least two measuring plug arrays 420, wherein the second metal layer 220 located in the functional region is electrically connected to the plugs to be measured 410, the second metal layer 220 located in the scribe line is electrically connected to the measuring plugs 421 in the at least two measuring plug arrays 420, the plugs to be measured 410 are connected in series to the measuring plugs 421 in the adjacent measuring plug arrays 420 through the first metal layer 210 or the second metal layer 220, and the measuring plugs 421 in the at least two measuring plug arrays 420 and the measuring plug arrays 420 are connected in series. Wherein forming the second metal layer 220 comprises the following steps:
forming a second metal film layer on the first insulating layer 310;
forming a patterned second photoresist layer on the second metal film layer, and etching the second metal film layer by using the patterned second photoresist layer as a mask to form the second metal layer 220;
and removing the patterned second photoresist layer.
Step S50: a second insulating layer 320 is formed on the second metal layer 220, and the second insulating layer 320 exposes the detection window 500 of the second metal layer 220 in the scribe line.
In summary, the present invention provides a semiconductor device and a method for manufacturing the same, wherein a detection structure is added to the semiconductor device, the detection structure includes a first metal layer, at least two measurement plug arrays and a second metal layer sequentially formed on a scribe line of a semiconductor substrate, the detection structure can detect whether a plug to be measured has an open circuit problem, the detection structure can accurately detect the open circuit problem of the plug to be measured, and the detection structure does not need to be confused with measurement parameters in other measurement items, so that an electrical defect caused by the open circuit of the plug can be rapidly and directly detected.
In addition, it should be noted that the terms "first", "second", and the like in the specification are used for distinguishing each component, element, step, and the like in the specification, and are not used for representing a logical relationship or a sequential relationship between each component, element, step, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (7)
1. A semiconductor device, comprising:
the semiconductor substrate comprises a functional region and a cutting way;
a first metal layer formed on the semiconductor substrate;
a first insulating layer formed on the first metal layer;
the plug to be measured is embedded in the first insulating layer of the functional region and is electrically connected with the first metal layer;
at least two measuring plug arrays which are embedded in the first insulating layer of the cutting channel and electrically connected with the first metal layer, wherein the measuring plug arrays are connected in series;
the second metal layer is formed on the first insulating layer, the plug to be measured and the at least two measuring plug arrays and is electrically connected with the plug to be measured and the measuring plug arrays, and measuring plugs in the measuring plug arrays are connected in series through the first metal layer or the second metal layer;
the first metal layer, the at least two measuring plug arrays and the second metal layer which are positioned on the cutting channel jointly form a detection structure of the plug to be measured, and the plug to be measured is connected with the detection structure in series through the first metal layer.
2. The semiconductor device of claim 1, wherein the array of measurement plugs comprises 2nAnd the measuring plugs are provided, wherein n is more than or equal to 1 and is a positive integer.
3. The semiconductor device according to claim 2, wherein the measurement plugs in the measurement plug array are connected in series.
4. The semiconductor device according to any one of claims 1 to 3, further comprising a second insulating layer formed on the second metal layer and exposing a detection window of the second metal layer in the scribe line.
5. A method of manufacturing a semiconductor device, the semiconductor device according to any of claims 1 to 4 being manufactured, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a functional region and a cutting way;
forming a first metal layer and a first insulating layer on the semiconductor substrate;
embedding a plug to be measured and at least two measuring plug arrays in the first insulating layer, wherein the plug to be measured is embedded in the first insulating layer of the functional region and is electrically connected with the first metal layer, the at least two measuring plug arrays are embedded in the first insulating layer of the cutting channel and are electrically connected with the first metal layer, and the measuring plug arrays are connected in series;
and forming a second metal layer on the first insulating layer, the plug to be measured and the at least two measuring plug arrays, wherein the second metal layer is electrically connected with the plug to be measured and the measuring plug arrays, the measuring plugs in the measuring plug arrays are connected in series through the first metal layer or the second metal layer, the first metal layer, the at least two measuring plug arrays and the second metal layer which are positioned in the cutting channel jointly form a detection structure of the plug to be measured, and the plug to be measured is connected in series with the detection structure through the first metal layer.
6. The method of claim 5, wherein forming the first metal layer comprises:
forming a first metal film layer on the semiconductor substrate;
forming a first patterned photoresist layer on the first metal film layer, and etching the first metal film layer by taking the first patterned photoresist layer as a mask to form the first metal layer;
and removing the patterned first photoresist layer.
7. The method of claim 5, wherein forming the second metal layer comprises:
forming a second metal film layer on the first insulating layer;
forming a second patterned photoresist layer on the second metal film layer, and etching the second metal film layer by taking the second patterned photoresist layer as a mask to form the second metal layer;
and removing the patterned second photoresist layer.
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| CN115706072A (en) * | 2021-08-16 | 2023-02-17 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Citations (1)
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| JPH0661298A (en) * | 1992-08-11 | 1994-03-04 | Hitachi Ltd | Semiconductor integrated circuit device |
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| KR20030047031A (en) * | 2001-12-07 | 2003-06-18 | 주식회사 하이닉스반도체 | A test pattern of semiconductor device |
| KR20100079261A (en) * | 2008-12-31 | 2010-07-08 | 주식회사 동부하이텍 | Method for manufacturing semiconductor device |
| US20110050273A1 (en) * | 2009-08-25 | 2011-03-03 | Ssu-Pin Ma | Fast testable wafer and wafer test method |
| CN105336639B (en) * | 2015-10-30 | 2018-02-16 | 上海华虹宏力半导体制造有限公司 | The method of testing of semi-conductor test structure, its forming method and conductive plunger performance |
| CN109166843B (en) * | 2018-08-28 | 2020-09-11 | 武汉新芯集成电路制造有限公司 | Semiconductor device, manufacturing method thereof and semiconductor device testing method |
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