JP2007116041A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of evaluating differences between an etching rate of a dense pattern and etching rates of other parts in a dry etching. <P>SOLUTION: The semiconductor device is equipped with a first TEG pattern 4c which is formed on an insulating film 2, and has a first plurality of conductive patterns mutually spaced and arranged almost in parallel and electrically separated each other; a second TEG pattern 4e which is formed on the insulating film 2, has a second plurality of conductive patterns mutually spaced and arranged almost in parallel, and has third conductive patterns mutually connecting the second plurality of conductive patterns; a first checking gate electrode 4a which is connected with any of the first plurality of conductive patterns; a second checking gate electrode 4b which is connected with the second TEG pattern 4e; a first checking gate insulating film 3a which is located under the first checking gate electrode 4a; and a second checking gate insulating film 3b which is located under the second checking gate electrode 4b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a TEG (Test Element Group) and the semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device capable of evaluating a difference between an etching rate at a dense pattern portion and an etching rate at another portion in dry etching.

  FIG. 13 is a plan view for explaining an example of a configuration of a TEG included in a conventional semiconductor device. The TEG shown in this figure is a TEG for evaluating plasma damage during dry etching, and is formed by forming a first metal wiring 101 a and a second metal wiring 101 b on the interlayer insulating film 100.

The first metal wiring 101 a is connected to the gate electrode of a test transistor (not shown) through a connection hole (not shown) formed in the interlayer insulating film 100. The second metal wiring 101b is arranged so as to surround the first metal wiring 101a, and a diode (not shown) is connected through a connection hole (not shown) formed in the interlayer insulating film 100. It is connected to the. Plasma damage is evaluated by evaluating the pressure resistance of the gate insulating film of the inspection transistor. By disposing the second metal wiring 101b connected to the diode, plasma damage applied to the gate insulating film is amplified (see, for example, Patent Document 1).
JP-A-10-79407 (FIG. 1 and 10th to 16th paragraphs)

  FIG. 14 is a diagram for explaining a method of forming a wiring pattern on the insulating film 110. First, as illustrated in FIG. 14A, a conductive film 112 and a resist pattern 120 are formed over the insulating film 110. The resist pattern 120 is a pattern in which a plurality of linear patterns are arranged in parallel to each other.

  Next, as shown in FIG. 14B, the conductive film 112 is dry-etched using the resist pattern 120 as a mask. As a result, the portion of the conductive film 112 positioned below the resist pattern 120 becomes a linear wiring 112a parallel to each other. Note that the etching rate between the straight wirings 112a is slower than the other portions. For this reason, in the state shown in FIG. 14B, the straight wiring 112a is separated from the other parts, but a part of the conductive film 112 remains between them, so that they are electrically connected to each other. Is in a state.

  Thereafter, as shown in FIG. 14C, dry etching is further advanced. Thereby, the straight wirings 112a are separated from each other.

  In a semiconductor chip as a product, other wiring is often arranged around the wiring connected to the gate electrode of the transistor. When the distance between the wiring connected to the gate electrode and the other wiring is narrow, as in the case shown in FIG. 14, these wirings are temporarily electrically connected in the process of dry etching when these wirings are formed. And it will be in the state separated from other conductors (for example, the state shown in FIG. 14B). In this state, the plasma charge applied to the wiring located around the wiring connected to the gate electrode is also transmitted to the gate electrode and damages the gate insulating film.

  Therefore, in dry etching, it is necessary to reduce the difference between the etching rate of the portion where the pattern is dense and the etching rate of the other portion. However, conventionally, the difference between these etching rates could not be evaluated.

  The present invention has been made in consideration of the above-described circumstances, and the object thereof is to evaluate the difference between the etching rate of a portion where the pattern is dense and the etching rate of other portions in dry etching. A semiconductor device manufacturing method and a semiconductor device are provided.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating layer having a first opening pattern and a second opening pattern on a monitoring semiconductor substrate;
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. Forming, and
Forming a conductive film on the insulating layer and on each of the first and second inspection gate insulating films;
A resist pattern is formed on the conductive film, and the conductive film is dry-etched using the resist pattern as a mask, whereby the first inspection gate electrode positioned on the first inspection gate insulating film, the first A second inspection gate electrode positioned on the second inspection gate insulating film; a first TEG pattern positioned on the insulating layer and connected to the first inspection gate electrode; and on the insulating layer Forming each of the second TEG patterns that are located at and connected to the second gate electrode for inspection;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns that are spaced apart and substantially parallel to each other, and a third conductor pattern that connects the plurality of second conductor patterns to each other.

  In the step of forming the first and second TEG patterns of the manufacturing method of the semiconductor device, the resist pattern of the conductive film is between the first conductor patterns and between the second conductor patterns. The conductive film remains thin even after other portions not covered with are removed.

Thereafter, dry etching is continued to remove the thin remaining conductive film. Plasma charge generated in each of the plurality of first conductor patterns is caused by the first conductive film passing through the portion where the conductive film remains thin. Is transmitted to the inspection gate electrode to damage the first inspection gate insulating film.
Similarly, plasma charges are generated in each of the second conductor pattern and the third conductor pattern. These plasma charges are transmitted to the second inspection gate electrode, and the second inspection gate insulating film. Damage to the.

  Note that, after the thin remaining conductive film is removed, plasma damage applied to the first gate insulating film for inspection decreases from the middle. On the other hand, since the second conductor pattern and the third conductor pattern remain connected to each other, the plasma damage applied to the second inspection gate insulating film remains large.

  Therefore, by evaluating the difference in breakdown voltage between the first and second inspection gate insulating films, the etching rate of the dense pattern and the etching rate of the other part when the conductive film is dry-etched. Can be quantitatively evaluated.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating layer having a first opening pattern and a second opening pattern on a monitoring semiconductor substrate;
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. Forming, and
Forming each of a first inspection gate electrode located on the first inspection gate insulating film and a second inspection gate electrode located on the second inspection gate insulating film;
Forming a second insulating layer on or above each of the first insulating layer, the first inspection gate electrode, and the second inspection gate electrode;
Forming a conductive film on the second insulating layer;
A first TEG connected to the first inspection gate electrode is formed on the second insulating layer by forming a resist pattern on the conductive film and dry-etching the conductive film using the resist pattern as a mask. Forming a pattern and a second TEG pattern connected to the second inspection gate electrode;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns that are spaced apart and substantially parallel to each other, and a third conductor pattern that connects the plurality of second conductor patterns to each other.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film having a first opening pattern, a second opening pattern, and a third opening pattern on a semiconductor substrate,
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. And forming a gate insulating film for an element on the semiconductor substrate located in the third opening pattern;
Forming a conductive film on each of the element isolation film, the first and second inspection gate insulating films, and the element gate insulating film;
A resist pattern is formed on the conductive film, and the conductive film is dry-etched using the resist pattern as a mask, whereby the first inspection gate electrode positioned on the first inspection gate insulating film, the first A second test gate electrode positioned on the second test gate insulating film; a first TEG pattern positioned on the element isolation film and connected to the first test gate electrode; and the element isolation film Forming a second TEG pattern that is located above and connected to the second gate electrode for inspection, and an element gate electrode that is located on the element gate insulating film;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns that are spaced apart and substantially parallel to each other, and a third conductor pattern that connects the plurality of second conductor patterns to each other.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation film having a first opening pattern, a second opening pattern, and a third opening pattern on a semiconductor substrate,
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. And forming a gate insulating film for an element on the semiconductor substrate located in the third opening pattern;
On the first inspection gate electrode positioned on the first inspection gate insulating film, the second inspection gate electrode positioned on the second inspection gate insulating film, and on the element gate insulating film Forming each of the device gate electrodes located in
Forming an interlayer insulating film on or above each of the element isolation film, the first inspection gate electrode, the second inspection gate electrode, and the element gate electrode;
Forming a conductive film on the interlayer insulating film;
A first TEG pattern connected to the first gate electrode for inspection on the interlayer insulating film by forming a resist pattern on the conductive film and dry-etching the conductive film using the resist pattern as a mask; Forming a second TEG pattern connected to the second inspection gate electrode and a wiring connected to the element gate electrode;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns that are spaced apart and substantially parallel to each other, and a third conductor pattern that connects the plurality of second conductor patterns to each other.

  In each of the semiconductor device manufacturing methods described above, it is preferable that the interval between the first conductor patterns is substantially equal to the interval between the second conductor patterns. Moreover, it is preferable that the space | interval of the said 1st TEG pattern and the said 2nd TEG pattern is wider than any of the mutual space | interval of the said 1st conductor pattern, and the mutual space | interval of the said 3rd conductor pattern.

A semiconductor device according to the present invention includes a first TEG pattern having a plurality of first conductor patterns formed on an insulating film, spaced apart and substantially parallel to each other, and electrically separated from each other;
A plurality of second conductor patterns formed on the insulating film and arranged substantially parallel to each other and a third conductor pattern connecting the plurality of second conductor patterns to each other; 2 TEG patterns;
A first inspection gate electrode connected to any of the first conductor patterns;
A second inspection gate electrode connected to the second TEG pattern;
A first inspection gate insulating film located under the first inspection gate electrode;
And a second inspection gate insulating film located under the second inspection gate electrode.

  The first TEG pattern and the second TEG pattern are preferably formed on a monitoring semiconductor substrate. In addition, the first TEG pattern and the second TEG pattern are formed on a semiconductor substrate having a plurality of regions to be semiconductor chips, and dicing lines that separate the regions to be the plurality of semiconductor chips from each other. It is preferably located.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. This embodiment is a method of manufacturing a semiconductor device that can evaluate plasma charge when patterning a polysilicon film.

  In the present embodiment, the silicon wafer 1 is a monitor wafer. FIG. 1A is a plan view for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view taken along the line AA in FIG. 2A and 2B are a BB cross-sectional view and a CC cross-sectional view, respectively, in FIG. 3A is a plan view for explaining the next step of FIGS. 1 and 2, and FIG. 3B, FIG. 4A, and FIG. ) AA sectional view, BB sectional view and CC sectional view. FIGS. 5A and 5B are cross-sectional views for explaining the next step of FIG. 3, and correspond to the BB cross-sectional view and the CC cross-sectional view of FIG.

  First, as shown in FIGS. 1 and 2, wells 1 a and 1 b are formed in a silicon wafer 1. Next, a groove is formed on the silicon wafer 1, and an element isolation film 2 (for example, a silicon oxide film) is embedded in the groove. In the element isolation film 2, two opening patterns located on the wells 1a and 1b are formed. Next, the silicon wafer 2 is thermally oxidized. As a result, the first inspection gate insulating film 3a and the second inspection gate insulating film 3b are formed in each of the wells 1a and 1b.

  Next, a polysilicon film 4 is formed on each of the element isolation film 2, the first inspection gate insulating film 3a, and the second inspection gate insulating film 3b by the CVD method. Next, a photoresist film is applied on the polysilicon film 4, and this photoresist film is exposed and developed. As a result, a resist pattern 21 for forming the first TEG pattern and a resist pattern 22 for forming the second TEG pattern are formed on the polysilicon film 4.

  The resist pattern 21 is disposed above the element isolation film 2 and arranged on the opposite side of the linear pattern 21a via the plurality of linear patterns 21a arranged in parallel to each other and the first gate insulating film 3a for inspection. A rectangular pattern 21b and a linear pattern 21c passing above the first inspection gate insulating film 3a are provided. The linear pattern 21c has one end connected to one end of the linear pattern 21a and the other end connected to the rectangular pattern 21b.

  The resist pattern 22 is located above the element isolation film 2 and arranged in parallel to each other, a plurality of linear patterns 22a, a linear pattern 22b that connects the ends of the linear patterns 22a, and a second gate insulation for inspection. A rectangular pattern 22c arranged on the opposite side of the linear patterns 22a and 22b via the film 3b and a linear pattern 22d passing above the second inspection gate insulating film 3b are provided. The linear pattern 22d has one end connected to the linear pattern 22b and the other end connected to the rectangular pattern 21b.

The width _{L 2} of the linear pattern 22a is equal to the width _{L 1} of the straight line pattern 21a, spacing _{S 2} of linear pattern 22a is equal to the mutual spacing _{S 1} of linear pattern 21a. These widths and mutual intervals are preferably the minimum values in the design rule. Moreover, the mutual spacing of the resist pattern 21 is wider than the width _{L 1.}

  Next, as shown in FIGS. 3 and 4, the polysilicon film 4 is dry etched using the resist patterns 21 and 22 as a mask. As a result, the polysilicon film 4 is patterned to form a first TEG pattern 4c positioned below the linear pattern 21a and a second TEG pattern 4e positioned below the linear patterns 22a and 22b.

  In addition, by this processing, the pad 4d located below the rectangular pattern 21b and the linear pattern 21c, that is, the first inspection gate electrode 4a located on the first inspection gate insulating film 3a and the rectangular pattern 22c are provided. And a second inspection gate electrode 4b located below the linear pattern 22d, that is, on the second inspection gate insulating film 3b.

  The first TEG pattern 4c has a shape in which a plurality of linear patterns are arranged in parallel. One end of one of the linear patterns is connected to one end of the first inspection gate electrode 4a. The other end of the first inspection gate electrode 4a is connected to the pad 4d.

  The second TEG pattern 4e has a shape in which a plurality of linear patterns are arranged in parallel and ends of these linear patterns are connected to each other. The second inspection gate electrode 4b has one end connected to the second TEG pattern 4e and the other end connected to the pad 4g.

  Each of FIGS. 3 and 4 shows a state just before the end of the dry etching. In this state, as shown in FIG. 4A, a plurality of the first TEG patterns 4c have A thin polysilicon film 4 remains between the linear patterns. Further, as shown in FIG. 4B, the second TEG pattern 4e also has a thin polysilicon film 4 between a plurality of parallel linear patterns. This is because the etching rate of a portion where the pattern is dense is slower than the etching rate of other portions.

  Thereafter, as shown in FIGS. 5A and 5B, dry etching is continued to remove the thin polysilicon film 4 remaining. In this process, plasma charges are generated in each of the plurality of linear patterns constituting the first TEG pattern 4c. These plasma charges are caused by the first inspection gate through the portion where the polysilicon film 4 remains thin. This is transmitted to the electrode 4a to damage the first inspection gate insulating film 3a located under the first inspection gate electrode 4a.

  Similarly, plasma charges are also generated in each of the plurality of linear patterns constituting the second TEG pattern 4e, and these plasma charges are caused by the second inspection gate insulating film located below the second inspection gate electrode 4b. Damage 3b.

  After the thin remaining polysilicon film 4 is removed, the plurality of linear patterns constituting the first TEG pattern 4c are separated from each other, so that the plasma damage applied to the first inspection gate insulating film 3a is small. Become. On the other hand, since the plurality of linear patterns constituting the second TEG pattern 4e remain connected to each other, the plasma damage applied to the second inspection gate insulating film 3b remains large.

  Thereafter, each resist pattern is removed. Then, probe terminals are connected to the pads 4d and 4g, respectively. Then, a voltage is applied to each of the first inspection gate electrode 4a and the second inspection gate electrode 4b to cause a breakdown voltage of the first inspection gate insulating film 3a, and a second inspection gate insulation. Each voltage at which the film 3b breaks down is inspected.

  As described above, the plasma damage applied to the first inspection gate insulating film 3a and the plasma damage applied to the second inspection gate insulating film 3b are thinly left between a plurality of parallel linear patterns. It differs after the silicon film 4 is removed. Therefore, according to the present embodiment, a plurality of linear patterns are separated from each other in the voltage at which the first inspection gate insulating film 3a breaks down and the voltage at which the second inspection gate insulating film 3b breaks down. There will be a difference depending on the time after

  Therefore, according to the present embodiment, polysilicon is measured by measuring the difference between the voltage at which the first inspection gate insulating film 3a breaks down and the voltage at which the second inspection gate insulating film 3b breaks down. When the film is dry-etched, the difference between the etching rate of the portion where the pattern is dense and the etching rate of the other portion can be quantitatively evaluated.

Accordingly, a plurality of types of first TEG patterns 4c and second TEG patterns 4e having different widths L ₁ and L ₂ and intervals S ₁ and S ₂ are formed under dry etching conditions during product formation. By evaluating the withstand voltage of the gate insulating films 3a and 3b for the test, if the width and interval of the polysilicon wiring pattern are set to any value under the dry etching conditions, It can be evaluated whether the difference from the etching rate of other portions is small.

Further, by changing the dry etching conditions of the polysilicon film 4 without changing the widths L ₁ , L ₂ and the intervals S ₁ , S ₂ , the etching rate between a plurality of parallel linear patterns can be changed, and other portions Etching conditions having a small difference from the etching rate can be found.

FIG. 6A is a plan view for explaining a method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 6B is a cross-sectional view taken along line AA of FIG. is there. 7A and 7B are a BB cross-sectional view and a CC cross-sectional view, respectively, in FIG. 6A. FIG. 8A is a plan view for explaining the next step of FIG. 6 and FIG. 7, and FIG. 8B, FIG. 9A, and FIG. It is AA sectional drawing of A), BB sectional drawing, and CC sectional drawing. FIGS. 10A and 10B are cross-sectional views for explaining the next step of FIGS. 8 and 9, and correspond to the BB cross-sectional view and the CC cross-sectional view of FIG. .
Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIGS. 6 and 7, wells 1a and 1b, an element isolation film 2, first and second inspection gate insulating films 3a and 3b, and first and second wells are formed on a silicon wafer 1. The inspection gate electrodes 4a and 4b are formed. Note that the first and second TEG patterns 4c and 4e and the pads 4d and 4g shown in the first embodiment are not formed.

Next, an interlayer insulating film 10 is formed on the entire surface including the element isolation film 2, the first and second inspection gate insulating films 3a and 3b, and the first and second inspection gate electrodes 4a and 4b by a CVD method. To form. Next, a photoresist film (not shown) is applied on the interlayer insulating film 10, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the interlayer insulating film 10. Next, the interlayer insulating film 10 is etched using this resist pattern as a mask. Thus, two connection holes located on the first inspection gate electrode 4a and two connection holes located on the second inspection gate electrode 4b are formed in the interlayer insulating film 10.
Thereafter, the resist pattern is removed.

  Next, a tungsten film is formed on the interlayer insulating film 10 and in each connection hole by a CVD method. Next, the tungsten film located on the interlayer insulating film 10 is polished and removed by the CMP method. As a result, the tungsten plugs 11a and 11b located on the first inspection gate electrode 4a and the tungsten plugs 11c and 11d located on the second inspection gate electrode 4b are embedded in the interlayer insulating film 10.

  Next, an Al alloy film 12 is formed by sputtering on the entire surface including the interlayer insulating film 10 and each tungsten plug. Next, a photoresist film is applied on the Al alloy film 12, and this photoresist film is exposed and developed. As a result, a plurality of linear resist patterns 23a, rectangular resist patterns 23b and 24a, a plurality of linear resist patterns 24b, and a linear resist pattern 24c are formed on the Al alloy film 12.

  The plurality of resist patterns 23a are arranged substantially parallel and spaced apart from each other. One of the resist patterns 23a is positioned on the tungsten plug 11a. The resist patterns 23b and 24a are located on the tungsten plugs 11b and 11c, respectively. The plurality of resist patterns 24b are arranged substantially parallel and spaced apart from each other. The resist pattern 24c is disposed in a direction substantially orthogonal to the resist pattern 24b, and connects the ends of the plurality of resist patterns 24b to each other. A tungsten plug 11d is located under the resist pattern 24c.

The resist pattern 23a width _{L 3} and spacing _{S 3} of approximately equal to the width _{L 4} and spacing _{S 4} of the resist pattern 24b. These widths and mutual intervals are preferably the minimum values in the design rule. The spacing of the resist pattern 23a and the resist pattern 24b is wider than _{L 3.}

  Next, as shown in FIGS. 8 and 9, the Al alloy film 12 is etched using the resist patterns 23a, 23b, and 24a to 24c as masks. As a result, the Al alloy film 12 is patterned to form the first TEG pattern 12a located under the resist pattern 23a and the second TEG pattern 12d located under the resist patterns 24b and 24c. Further, by this processing, a pad 12b located under the resist pattern 23b, that is, on the tungsten plug 11b, and a pad 12c located under the resist pattern 24a, that is, on the tungsten plug 11c are formed.

  The first TEG pattern 12a has a shape in which a plurality of linear patterns are arranged in parallel. One of the linear patterns is connected to the first inspection gate electrode 4a through a tungsten plug 11a. The first inspection gate electrode 4a is also connected to the pad 12b via the tungsten plug 11b.

  The second TEG pattern 12d has a shape in which a plurality of linear patterns are arranged in parallel and ends of these linear patterns are connected to each other. The second TEG pattern 12d is connected to the second inspection gate electrode 4b through the tungsten plug 11d. The second inspection gate electrode 4b is connected to the pad 12c through the tungsten plug 11c.

  8 and 9 show a state just before the end of the dry etching. In this state, as shown in FIGS. 9A and 9B, the first TEG pattern 12a is shown. In the second TEG pattern 12d, the thin Al alloy film 12 remains between the plurality of linear patterns.

  Thereafter, as shown in FIGS. 10A and 10B, dry etching is continued to remove the remaining Al alloy film 12. In this process, the plasma charge generated in each of the plurality of linear patterns constituting the first TEG pattern 12a is applied to the first inspection gate electrode 4a via the portion where the Al alloy film 12 remains thin and the tungsten plug 11a. This is transmitted and damages the first inspection gate insulating film 3a.

  Similarly, plasma charges are also generated in each of the plurality of linear patterns constituting the second TEG pattern 12d. These plasma charges are transmitted to the second inspection gate electrode 4b through the tungsten plug 11d, and the second This damages the second inspection gate insulating film 3b located under the inspection gate electrode 4b.

  After the thin remaining Al alloy film 12 is removed, the plurality of linear patterns constituting the first TEG pattern 12a are separated from each other, so that the plasma damage applied to the first gate insulating film 3a for inspection Becomes smaller from the middle. On the other hand, since the plurality of linear patterns constituting the second TEG pattern 12d remain connected to each other, the plasma damage applied to the second inspection gate insulating film 3b remains large.

  Thereafter, each resist pattern is removed. Then, probe terminals are connected to the pads 12b and 12c, respectively. A voltage is applied to each of the first inspection gate electrode 4a and the second inspection gate electrode 4b via the tungsten plugs 11b and 11c, and a voltage at which the first inspection gate insulating film 3a breaks down. Each voltage at which the second inspection gate insulating film 3b breaks down is inspected.

  Thus, according to the present embodiment, the voltage at which the first inspection gate insulating film 3a breaks down and the voltage at which the second inspection gate insulating film 3b breaks down as in the first embodiment. By measuring the difference, it is possible to quantitatively evaluate the difference between the etching rate of the portion where the pattern is dense and the etching rate of the other portion when the Al alloy film is etched.

Therefore, a plurality of types of first TEG patterns 12a and second TEG patterns 12d having different widths L ₃ , L ₄ and intervals S ₃ , S ₄ are formed under the same conditions as the actual product forming process, By evaluating the pressure resistance of the second gate insulating films 3a and 3b for inspection, if the width and interval of the Al alloy wiring are set to any value under this condition, the etching rate of the portion where the pattern is dense, etc. It can be evaluated whether or not the difference from the etching rate of this portion is small.

Further, by changing the dry etching conditions of the Al alloy film 12 without changing the widths L ₁ and L ₂ and the distances S ₁ and S ₂ , the etching rate of the dense pattern portion when the Al alloy film is dry etched. And the etching conditions with a small difference with the etching rate of another part can be found.

  FIG. 11 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention. In the present embodiment, the gate insulating film and the gate electrode of the transistor are formed in the region to be the semiconductor chip, and at the same time, the dicing lines that separate the regions to be the semiconductor chip from each other are formed on the first and This is a method of forming a second TEG. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In a semiconductor device formed by this method, an element isolation film 2, a well 1c, an element gate insulating film 3c, and an element gate electrode 4h are formed in a region to be a semiconductor chip. These are formed in the same process as the wells 1a and 1b, the first and second inspection gate insulating films 3a and 3b, and the first and second inspection gate electrodes 4a and 4b, respectively. Note that a resist pattern 25 is formed on the element gate electrode 4h as a mask when the polysilicon film is dry-etched. The resist pattern 25 is formed in the same process as the resist patterns 21 and 22.

In the step of forming the element gate electrode 4h and the first and second inspection gate electrodes 4a and 4b, the first TEG pattern 4c, the second TEG pattern 4e, and the pads 4d and 4g are formed. Is done.
Therefore, according to the present embodiment, the device gate electrode 4h is formed by examining the breakdown voltage of the first and second inspection gate insulating films 3a and 3b by the same method as in the first embodiment. Under dry etching conditions, it can be determined whether or not the difference between the etching rate between the linear patterns and the etching rate of other portions is large.

  FIG. 12 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. In the present embodiment, the Al alloy wiring is formed in the region to be the semiconductor chip, and at the same time, the first and second TEGs shown in the second embodiment are formed in the dicing lines that separate the regions to be the semiconductor chip from each other. Is the method. The Al alloy wiring is connected to the gate electrode of the transistor shown in the third embodiment. Hereinafter, the same components as those in the second or third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the semiconductor device formed by this method, an element isolation film 2, a well 1c, an element gate insulating film 3c, an element gate electrode 4h, and impurity regions (not shown) to be a source and a drain are formed in a region to be a semiconductor chip. An interlayer insulating film 10, a tungsten plug 11e embedded in the interlayer insulating film 10, and an Al alloy wiring 12e are formed.

These include wells 1a and 1b, first and second inspection gate insulating films 3a and 3b, first and second inspection gate electrodes 4a and 4b, and tungsten plugs 11a to 11d, respectively, except for the impurity region. It is formed in the same process as the process of forming and the process of forming the first and second TEG patterns 12a and 12d. Impurity regions serving as a source and a drain are introduced into the silicon wafer 1 using the element isolation film 2 and the element gate electrode 4h as a mask after the element gate electrode 4h is formed and before the interlayer insulating film 10 is formed. It is formed by doing.
Note that a resist pattern 26 is formed on the Al alloy wiring 12e as a mask when the Al alloy film is dry-etched. The resist pattern 26 is formed in the same process as the resist patterns 23 and 24.

As described above, in the step of forming the Al alloy wiring 12e, the first TEG pattern 12a, the second TEG pattern 12d, and the pads 12b and 12c are formed.
Therefore, according to the present embodiment, by checking the breakdown voltage of the first and second inspection gate insulating films 3a and 3b by the same method as in the second embodiment, the dryness when the Al alloy wiring 12e is formed is measured. Under the etching conditions, it can be determined whether or not the difference between the etching rate between the linear patterns and the etching rate of other portions is large.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, instead of the polysilicon film 4, a stacked film of a polysilicon film and a molybdenum silicide film or a stacked film of a polysilicon film and a tungsten silicide film may be used in the first embodiment. In addition, by using a glass substrate instead of the silicon wafer 1, it is possible to perform an evaluation in a thin film transistor forming process for controlling display of liquid crystal.

(A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment, (B) is AA sectional drawing of (A). (A) is BB sectional drawing of FIG. 1 (A), (B) is CC sectional drawing of FIG. 1 (A). (A) is a top view for demonstrating the next process of FIG.1 and FIG.2, (B) is AA sectional drawing of (A). (A) is BB sectional drawing of FIG. 3 (A), (B) is CC sectional drawing of FIG. 3 (A). (A), (B) is sectional drawing for demonstrating the next process of FIG.3 and FIG.4. (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment, (B) is AA sectional drawing of (A). (A) is BB sectional drawing of FIG. 6 (A), (B) is CC sectional drawing of FIG. 6 (A). (A) is a top view for demonstrating the next process of FIG.6 and FIG.7, (B) is AA sectional drawing of (A). (A) is BB sectional drawing of FIG. 8 (A), (B) is CC sectional drawing of FIG. 8 (A). (A), (B) is sectional drawing for demonstrating the next process of FIG.8 and FIG.9. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. The top view for demonstrating an example of a structure of TEG which the conventional semiconductor device has. Each figure is a view for explaining a method of forming a wiring pattern on the insulating film 110.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon wafer, 1a, 1b, 1c ... Well, 2 ... Element isolation film, 3a ... 1st inspection gate insulating film, 3b ... 2nd inspection gate insulating film, 3c ... Element gate insulating film, 4 ... polysilicon film, 4a ... first inspection gate electrode, 4b ... second inspection gate electrode, 4c, 12a ... first TEG pattern, 4d, 4g, 12b, 12c ... pad, 4e, 12d ... first 2 TEG pattern, 4 h... Gate electrode for element, 10... Interlayer insulating film, 11 a, 11 b, 11 c, 11 d, 11 e ... tungsten plug, 12 ... Al alloy film, 12 e. , 25, 26 ... resist pattern

Claims (9)

Forming an insulating layer having a first opening pattern and a second opening pattern on a semiconductor substrate for monitoring;
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. Forming, and
Forming a conductive film on the insulating layer and on each of the first and second inspection gate insulating films;
A resist pattern is formed on the conductive film, and the conductive film is dry-etched using the resist pattern as a mask, whereby the first inspection gate electrode positioned on the first inspection gate insulating film, the first A second inspection gate electrode positioned on the second inspection gate insulating film; a first TEG pattern positioned on the insulating layer and connected to the first inspection gate electrode; and on the insulating layer Forming each of the second TEG patterns that are located at and connected to the second gate electrode for inspection;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns spaced apart and substantially parallel to each other, and a semiconductor having a third conductor pattern connecting the plurality of second conductor patterns to each other. Device manufacturing method. Forming a first insulating layer having a first opening pattern and a second opening pattern on a semiconductor substrate for monitoring;
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. Forming, and
Forming each of a first inspection gate electrode located on the first inspection gate insulating film and a second inspection gate electrode located on the second inspection gate insulating film;
Forming a second insulating layer on or above each of the first insulating layer, the first inspection gate electrode, and the second inspection gate electrode;
Forming a conductive film on the second insulating layer;
A first TEG connected to the first inspection gate electrode is formed on the second insulating layer by forming a resist pattern on the conductive film and dry-etching the conductive film using the resist pattern as a mask. Forming a pattern and a second TEG pattern connected to the second inspection gate electrode;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns spaced apart and substantially parallel to each other, and a semiconductor having a third conductor pattern connecting the plurality of second conductor patterns to each other. Device manufacturing method. Forming an element isolation film having a first opening pattern, a second opening pattern, and a third opening pattern on a semiconductor substrate;
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. And forming a gate insulating film for an element on the semiconductor substrate located in the third opening pattern;
Forming a conductive film on each of the element isolation film, the first and second inspection gate insulating films, and the element gate insulating film;
A resist pattern is formed on the conductive film, and the conductive film is dry-etched using the resist pattern as a mask, whereby the first inspection gate electrode positioned on the first inspection gate insulating film, the first A second test gate electrode positioned on the second test gate insulating film; a first TEG pattern positioned on the element isolation film and connected to the first test gate electrode; and the element isolation film Forming a second TEG pattern that is located above and connected to the second gate electrode for inspection, and an element gate electrode that is located on the element gate insulating film;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns spaced apart and substantially parallel to each other, and a semiconductor having a third conductor pattern connecting the plurality of second conductor patterns to each other. Device manufacturing method. Forming an element isolation film having a first opening pattern, a second opening pattern, and a third opening pattern on a semiconductor substrate;
A first inspection gate insulating film is formed on the semiconductor substrate located in the first opening pattern, and a second inspection gate insulating film is formed on the semiconductor substrate located in the second opening pattern. And forming a gate insulating film for an element on the semiconductor substrate located in the third opening pattern;
On the first inspection gate electrode positioned on the first inspection gate insulating film, the second inspection gate electrode positioned on the second inspection gate insulating film, and on the element gate insulating film Forming each of the device gate electrodes located in
Forming an interlayer insulating film on or above each of the element isolation film, the first inspection gate electrode, the second inspection gate electrode, and the element gate electrode;
Forming a conductive film on the interlayer insulating film;
A first TEG pattern connected to the first gate electrode for inspection on the interlayer insulating film by forming a resist pattern on the conductive film and dry-etching the conductive film using the resist pattern as a mask; Forming a second TEG pattern connected to the second inspection gate electrode and a wiring connected to the element gate electrode;
Inspecting the breakdown voltage characteristics of the first and second gate insulating films by applying a voltage to each of the first and second inspection gate electrodes;
Comprising
The first TEG pattern includes a plurality of first conductor patterns that are spaced apart and substantially parallel to each other and are electrically separated from each other, and any one of the first conductor patterns is the first conductor pattern. 1 connected to the gate electrode for inspection,
The second TEG pattern includes a plurality of second conductor patterns spaced apart and substantially parallel to each other, and a semiconductor having a third conductor pattern connecting the plurality of second conductor patterns to each other. Device manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 1, wherein an interval between the first conductor patterns is substantially equal to an interval between the second conductor patterns. 6.   The distance between the first TEG pattern and the second TEG pattern is wider than both the mutual distance between the first conductor patterns and the mutual distance between the third conductor patterns. A method for manufacturing a semiconductor device according to one item. A first TEG pattern having a plurality of first conductor patterns formed on an insulating film, spaced apart and substantially parallel to each other, and electrically separated from each other;
A plurality of second conductor patterns formed on the insulating film and arranged substantially parallel to each other and a third conductor pattern connecting the plurality of second conductor patterns to each other; 2 TEG patterns;
A first inspection gate electrode connected to any of the first conductor patterns;
A second inspection gate electrode connected to the second TEG pattern;
A first inspection gate insulating film located under the first inspection gate electrode;
A second inspection gate insulating film located under the second inspection gate electrode;
A semiconductor device comprising:   The semiconductor device according to claim 7, wherein the first TEG pattern and the second TEG pattern are formed on a semiconductor substrate for monitoring. The first TEG pattern and the second TEG pattern are formed on a semiconductor substrate having a plurality of regions to be semiconductor chips, and are located on dicing lines that separate the regions to be the plurality of semiconductor chips from each other. The semiconductor device according to claim 7.

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