JP2998832B2 - Semiconductor device pattern forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly to a method of forming a pattern on a silicon wafer by etching using a photoresist film as a mask.

[0002]

2. Description of the Related Art Conventionally, when manufacturing a semiconductor device, elements such as transistors formed on a semiconductor chip are connected to each other by wirings also formed on the semiconductor chip to realize a desired circuit. Taking a semiconductor device using MOS transistors as an example, as shown in FIG. 6, an element isolation oxide film 2 is formed on a semiconductor substrate 1 using a normal LOCOS technique, and then a gate oxide film 3 is formed. . Polycrystalline silicon is formed on the entire surface, and a pattern of the gate electrode 4 is formed by using a usual lithography technique and a dry etching technique. Then, for example, ion implantation of an n-type impurity is performed to form an impurity region 5 serving as a source and a drain. Thereafter, although not shown, an interlayer insulating film is formed, a gate electrode and an interlayer insulating film on the source and drain are partially opened to form a contact hole, and a wiring for connecting elements is formed. I do.

Incidentally, the density of gate electrode and wiring patterns formed on an actual semiconductor chip varies.
For example, in an outer peripheral portion of a semiconductor chip in which bonding pads are arranged, a free region where no circuit element is arranged exists in the bonding pad portion and the vicinity thereof, and the pattern density is smaller than other regions. .

Further, in order to monitor whether a circuit element such as a transistor formed on a semiconductor chip has desired characteristics, an original semiconductor chip (hereinafter referred to as the present chip) is formed on a silicon wafer. There is a case where a test chip called a TEG (abbreviation of Test Element Group) chip is arranged adjacent to the TEG chip, but the TEG chip has an extremely small pattern density. In general, the TEG chip is provided with a large number of pads to which a probe is applied at the time of measurement, and the portion occupies most of the area of the TEG chip. In the case of 4MDRAM, for example, the pattern density of polycrystalline silicon constituting the gate electrode is 20 to 30% in this chip, but the pattern density in a general TEG chip is less than 5%.
Further, a test pattern for monitoring a pattern formed on the present chip may be formed on a scribe line region between the semiconductor chips, and the pattern density in this region is extremely small as on the TEG chip. Become.

[0005] When the density of patterns formed on a silicon wafer varies as described above, the wiring layer is thinner than its original size in a region where the patterns are sparsely formed. The reason is considered as follows. When using a photoresist film as a mask to etch the underlying material (polysilicon, aluminum, etc.) using a dry method such as RIE (Reactive Ion Etching), the photoresist film reacts with the excited active species in the plasma. And adheres to the side wall formed by etching the material to be etched (polysilicon, aluminum, etc.) to form a side wall protective film. In the region where the pattern density is low, the amount of the reaction product of the photoresist is small, so that the thickness of the formed sidewall protective film is small, and the etching anisotropy is lower than that in the region where the pattern density is high. The pattern is formed thin. FIG. 7 is a plan view in the vicinity of a vacant region when there is a vacant region between wirings of an original pattern actually formed (hereinafter, referred to as an actual pattern).
FIG. 8 is a sectional view taken along line CC ′ of FIG. 7. As shown in FIGS. 7 and 8, the actual patterns 8 a to 8
d; When 8e to 8h are formed, the actual patterns 8c to 8f arranged on the side closer to the empty area become thin.

FIG. 9 is a plan view showing a case where a TEG chip is provided on a silicon wafer 10. The chip 13 is arranged so as to surround the TEG chip 12 having an extremely small pattern density. In this case, the finished size of the pattern in the TEG chip 12 and the pattern of the main chip 13 surrounding the TEG chip 12 varies. FIG. 10 is a plan view near the boundary between the present chip and the TEG chip, and FIG. 11 is a cross-sectional view taken along the line DD ′. The present chip and the TEG chip are arranged with the scribe line region 6 interposed therebetween. In the present chip, a plurality of gate electrodes 4 serving as word lines are formed in parallel, and in the TEG chip, the gate electrodes 4 having an isolated pattern are formed. You. TE
On both sides of the gate electrode 4 of the G chip, impurity regions 5 serving as a source and a drain are formed. As shown in FIGS. 10 and 11, the outermost pattern and T
The pattern on the EG chip is formed thinner than the pattern at the center in the chip.

According to the investigation by the present applicant, for example, in the case of a gate electrode of a 4 MDRAM having a gate length of 0.8 μm, an average of 0.02 to 2.0 in an isolated pattern surrounded by an empty area.
Thinning of the wiring layer of about 0.08 μm has been confirmed, and this value corresponds to 2.5 to 10% of the channel length. As an adverse effect of such a thinner wiring, for example, the threshold voltage of a gate electrode is lowered, and the wiring capacity and resistance of a general wiring are changed. Come. Further, in the worst case, there is a problem that the wiring itself is disconnected or short-circuited in a place where there is a step under the wiring layer due to the influence of the lower wiring and a sufficient manufacturing margin cannot be secured at the time of pattern formation. In the case of a test pattern on a TEG chip or a scribe line area for monitoring the characteristics of elements and the formation state of wiring on this chip, the pattern in these areas may be formed differently from the expected dimensions. This makes it impossible to accurately monitor the characteristics of the regular pattern.

As a method for solving such a problem,
Japanese Patent Application Laid-Open No. 4-130709 proposes a method of arranging a dummy pattern irrelevant to the circuit operation in an empty area in a chip. In this method, as shown in the cross-sectional view of FIG. 12, a dummy pattern 9 is formed in a sparse portion of the actual pattern 8 formed on the semiconductor substrate 1 to reduce the sparseness of the pattern and prevent thinning of the wiring. It is assumed that.

[0009]

However, FIG.
In the method of simply arranging a dummy pattern in an area having a small pattern density as in the above, it is difficult to make the pattern uniform by inserting the dummy pattern. Due to the difference in the shape of the pattern, there is a difference in the density of the pattern, and the adverse effect at the time of etching cannot be completely removed. For example, if there is a large gap between the patterns and a large area dummy pattern is inserted to fill this gap, the pattern density near the center of the actual pattern portion will be smaller than the pattern density near the dummy pattern,
Conversely, there is a risk that the actual pattern adjacent to the empty area may be made thicker.

Therefore, the problem to be solved by the present invention is:
An object of the present invention is to prevent a pattern formed on a silicon wafer including a semiconductor chip on which circuit elements are formed from undergoing dimensional fluctuations depending on the density of the pattern.

[0011]

SUMMARY OF THE INVENTION The above-mentioned problem is that when patterns formed on a wafer are sparse and dense, a line having a pattern density substantially equal to the line width of a typical pattern of the original pattern is added to a region having a sparse pattern density. This can be solved by forming the dummy pattern having a width so that the difference in density is substantially eliminated.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of forming a pattern of a semiconductor device according to the present invention, a photoresist film having a predetermined pattern is formed on a silicon wafer including an original semiconductor chip on which circuit elements are to be formed, and etching is performed using the photoresist film as a mask. in the pattern forming method of a semiconductor device to transfer the pattern on the silicon wafer by performing a representative of the original pattern on the original semiconductor chip to the pattern density is sparse portions of the original pattern to be formed on a silicon wafer By providing a dummy pattern having a line width substantially equal to the line width of the original pattern so as to have a pattern density equivalent to the average pattern density of the original pattern on the original semiconductor chip, and
In the peripheral area, the photoresist
The pattern is formed such that the pattern density of the strike film is substantially uniform .

The area in which the dummy pattern is provided is an area on the original semiconductor chip, an area on a test chip provided adjacent to the original semiconductor chip and on which a device for evaluating characteristics is formed, and an area on the original semiconductor chip. One or more of a region on the dummy chip, which is provided adjacent to the chip and is cut out integrally with the original semiconductor chip, and a region on the scribe line between the chips.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of the present invention, and shows a state where a dummy pattern is arranged on the present chip. FIG. 2 is a cross-sectional view taken along line AA 'of FIG. FIG. As shown in FIGS. 1 and 2, a real pattern 8 is formed on a semiconductor substrate 1 with a vacant area therebetween. Pattern 9 is formed. The difference from the conventional example shown in FIG. 12 is that the arranged dummy pattern is divided into a plurality of parts with dimensions close to the width of the actual pattern. This will be described in detail below.

First, the average pattern density of the actual pattern 8 on the chip is calculated. In this case, the average value of the entire chip may be obtained, but it is more preferable to obtain the average density in a portion excluding a vacant region such as a peripheral portion of the chip where the bonding pads are formed. In the case of a simple pattern, manual calculation is possible, but it can also be easily calculated by graphic processing using a computer. The dummy pattern 9 is arranged in a sparse part of the pattern so as to be as close as possible to the pattern density obtained in this way. At this time, the width of the dummy pattern is, for example, an average width of adjacent actual patterns, and the pattern density is adjusted by adjusting the interval.

Here, the width of the dummy pattern is defined by adjusting the surface area of the photoresist in the region and the area of the pattern side wall of the object to be etched so that the adhesion of the reaction product at the time of etching is made equal. This is for adjusting the anisotropy of the etching. The pattern density can be adjusted within a range of about 1/4 to 4 times the actual pattern density, but this range varies depending on the pattern width and the like. By arranging a dummy pattern with a similar density and a similar wiring shape in a vacant area where no actual pattern exists by such a method and patterning the dummy pattern on a silicon wafer, the dimension at the time of etching the wiring layer due to the density of the pattern is reduced. The change can be prevented, and a more reliable device with less characteristic variation can be formed. The same effect can be obtained by arranging such a dummy pattern in a scribe line region where a test pattern is formed or where a test pattern is not formed.

FIG. 3 is a plan view showing a second embodiment of the present invention, and FIG. 4 is a sectional view taken along line BB 'of FIG.
As shown in FIGS. 3 and 4, on a silicon wafer,
The present chip and the TEG chip are arranged adjacent to each other with a scribe line region 6 interposed therebetween. An element isolation oxide film 2 is formed in an element isolation region on the semiconductor substrate 1 in the chip region, and a gate oxide film 3 is formed in the element region. Are formed. And
In the element region, impurity regions 5 are formed on the surface of the semiconductor substrate on both sides of the gate electrode 4. In this embodiment, unlike the conventional example shown in FIGS. 10 and 11, the dummy pattern 9 having the same width as the gate electrode is formed on the element isolation oxide film 2 in the TEG chip.
Are formed. Dummy pattern 9 on TEG chip
According to the present embodiment, the outermost gate electrode 4 on this chip is different from that of the conventional example shown in FIGS.
And the gate electrode 4 on the TEG chip is not formed thin, and a gate electrode having a desired wiring width can be obtained over the entire surface as shown in FIGS. The density and shape of the dummy pattern may be determined in the same manner as in the first embodiment.

FIG. 5 is a plan view showing a third embodiment of the present invention. In the present embodiment, as shown in FIG. 5, a main chip 11 and a dummy chip 14 provided adjacent to each main chip are formed on a silicon wafer 10. If the aspect ratio of this chip is extremely large,
There is a possibility that the chip is broken when the chip is cut from the silicon wafer. The dummy chip 14 of the present embodiment is a semiconductor piece provided for cutting in a state attached to the chip having a desired function in order to prevent the crack. In this embodiment, a dummy pattern is arranged on the dummy chip 14.

In the case of the second and third embodiments, T
The dummy pattern may be arranged over the entire area of the EG chip or the dummy chip. However, the dummy pattern may be arranged only in the area close to the present chip or only in the area close to the present chip and the necessary test pattern. Further, in the above embodiments, a pattern formation method of a semiconductor device using a MOS transistor has been described as an example. However, the present invention is not limited to this, and a semiconductor device using a bipolar transistor, The present invention can be widely applied to pattern formation of general semiconductor devices such as a semiconductor device using both a transistor and a bipolar transistor.

[0020]

As described above, in the pattern forming method according to the present invention, a dummy pattern having a pattern width substantially equal to the actual pattern is provided in at least a part of a region having a low pattern density so that the pattern density is substantially equal. Therefore, even in the pattern portion which is originally adjacent to the empty region, the same pattern shape and the same pattern density as those of the actual pattern portion having no empty region are obtained. In the etching process, the phenomenon in which the photoresist reacts with the excited active species to be etched and the reaction product adheres to the side wall of the etched wiring layer uniformly occurs regardless of the presence or absence of the empty region. Therefore, according to the present invention, even in a pattern near a vacant area, an etching environment equivalent to the inside of the pattern without dimensional change due to the density of the pattern is realized, and the dimensional change of wiring is prevented over the entire wafer surface. As a result, a highly reliable device with little characteristic variation can be formed. Further, since a dimensional change in the test pattern can be prevented, highly reliable evaluation can be performed.

[Brief description of the drawings]

FIG. 1 is a plan view of a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1;

FIG. 3 is a plan view of a second embodiment of the present invention.

FIG. 4 is a sectional view taken along the line BB ′ of FIG. 3;

FIG. 5 is a plan view of a third embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a procedure for forming a semiconductor device.

FIG. 7 is a plan view of a conventional example.

FIG. 8 is a sectional view taken along the line CC ′ of FIG. 7;

FIG. 9 shows TE on a silicon wafer adjacent to this chip
FIG. 4 is a plan view showing a state where a G chip is provided.

FIG. 10 is a plan view of another conventional example.

FIG. 11 is a sectional view taken along the line DD ′ of FIG. 10;

FIG. 12 is a cross-sectional view of a conventional example in which a dummy pattern is provided in an empty area.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 element isolation oxide film 3 gate oxide film 4 gate electrode 5 impurity region 6 scribe line region 8, 8a to 8h actual pattern 9 dummy pattern 10 silicon wafer 11 semiconductor chip (this chip) 12 TEG chip 13 adjacent to TEG chip The present chip 14 A dummy chip adjacent to the semiconductor chip

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-291344 (JP, A) JP-A-4-101146 (JP, A) JP-A-5-190791 (JP, A) JP-A-6-106 275492 (JP, A) JP-A-4-100043 (JP, A) JP-A-6-242594 (JP, A) JP-A-9-288347 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G03F 1/08 H01L 21/027

Claims (4)

(57) [Claims] 1. A photoresist film having a predetermined pattern is formed on a silicon wafer including an original semiconductor chip on which circuit elements are to be formed, and the photoresist film is used as a mask to perform etching to transfer the pattern onto the silicon wafer. In a method for forming a pattern of a semiconductor device, a portion having a low pattern density of an original pattern to be formed on a silicon wafer has a line width substantially equal to a line width of a typical pattern of an original pattern on an original semiconductor chip. By providing the dummy pattern so as to have a pattern density equal to the average pattern density of the original pattern on the original semiconductor chip , at least on the original semiconductor chip and
In the peripheral area, the photoresist
The pattern formation method of a semiconductor device, characterized in that the pattern density of the strike layer performs to patterning so that a substantially uniform. 2. The semiconductor device according to claim 1, wherein the area where the dummy pattern is provided is an area on an original semiconductor chip, an area on a test chip provided adjacent to the original semiconductor chip and on which a characteristic evaluation device is formed, or an original semiconductor chip. A region on a dummy chip provided adjacent to the chip, which is cut out integrally with the original semiconductor chip, and a region on a scribe line between the chips, which is one or more of a plurality of regions. 2. The pattern forming method for a semiconductor device according to claim 1, wherein: 3. The dummy pattern provided on the test chip or the dummy chip is formed only in the vicinity of the original semiconductor chip, or only in the vicinity of the original semiconductor chip and the necessary test pattern. 3. The method for forming a pattern of a semiconductor device according to claim 2, wherein: 4. The method according to claim 1, wherein the density of the dummy pattern is one-fourth to four times the average density of the original pattern.