JP2551202B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate electrode group having a two-layer structure of polysilicon and silicide, and an etching time for forming a gate electrode group by a preliminary test. In order to improve the product yield by optimizing the product, a polysilicon film and a sidewall film are laminated in this order on the surface of the test wafer through an insulating film, and gates are divided into multiple areas that divide the entire surface of the test wafer. The silicide film and the polysilicon film are etched using a mask for forming the electrode group to form a test gate electrode group, an insulating film covering the side surface and the upper surface of the test gate electrode group is formed, and the test gate electrode is formed. After forming a hole to expose the test wafer in the insulating film between each element of the group, a conductive film is deposited on the entire surface and patterned. Form a test electrode group,
Measure the voltage / current characteristics between the test gate electrode group and the test electrode group for each area, set the voltage corresponding to the allowable limit current as the breakdown voltage, and create a map of the breakdown voltage over the entire surface of the wafer. Then, a map of the breakdown voltage of the test gate electrode group in which the etching time of the polysilicon film is variously changed is created. It is configured by a method of manufacturing a semiconductor device having a preliminary step of determining an etching time of a polysilicon film having a prescribed value or more.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a gate electrode group having a two-layer structure of polysilicon and silicide.

With the miniaturization of MOS transistors, polysilicide has been used as a gate electrode, but it has become difficult to optimize the etching of orisilicide as the gate length becomes shorter. In particular, in the formation of the gate electrode of the two-layer film of polysilicon and tungsten silicide (WSi), the side oxide of tungsten silicide is large due to the reduction of the gate oxide film due to overetching and the difference in the etching rate of polysilicon and tungsten silicide. However, there are problems such as an increase in wiring resistance and instability of the shape of the two-layer structure of polysilicon and tungsten silicide, and how to etch the two-layer film is a major issue.

[Conventional technology]

Conventionally, the cross-sectional shape of a gate electrode having a two-layer structure has been observed by a scanning electron microscope to determine the conditions for optimizing etching. However, with this method, it is impossible to observe the distribution by observing all the cross-sectional shapes of the gate electrode group formed on the entire surface of the wafer, and to see the difference in the distribution between manufacturing lots. It took too much time to determine, and as a result there were many problems from the viewpoint of improving product yield and shortening the process.

[Problems to be Solved by the Invention]

Therefore, 2 of polysilicon and tungsten silicide
The above problem also occurred in the manufacture of a MOS transistor having a layered gate electrode group.

According to the present invention, in order to optimize the etching conditions for forming a gate electrode group having a two-layer structure, a test wafer having a test element group is first prepared as a preliminary step, and a characteristic distribution corresponding to an actual product is obtained in a short time. The objective is to improve the product yield by seeking and feeding back to the product manufacturing at an early stage.

[Means for solving the problem]

The above problem is that when forming a gate electrode group in which polysilicon and silicide are laminated in this order on the wafer surface via an insulating film, a plurality of test wafers having test element groups are formed on the entire surface, and each test wafer is manufactured. Is a method of manufacturing a semiconductor device having a preliminary step of determining the manufacturing conditions of the gate electrode group from the measurement of the electrical characteristics of the semiconductor wafer, wherein a polysilicon film and a silicide film are laminated in this order on the entire surface of a test wafer through an insulating film. Then, the silicide film and the polysilicon film are selectively etched using a mask for forming a gate electrode group in a plurality of areas dividing the entire surface of the test wafer to form a test gate electrode group. A sidewall insulating film is formed to cover a side surface of the test gate electrode group, and then a test including the test gate electrode group and the sidewall insulating film is performed. After forming an insulating film on the entire surface of the wafer, the insulating film in each intermediate region of the test gate electrode group whose side surface is covered with the side surface insulating film is removed to form an electrode window exposing the test wafer. After depositing a conductive film on the entire surface, the conductive film is patterned to form a test electrode group, and the voltage / current characteristics between the test gate electrode group and the test electrode group are measured for each area. Then, the voltage corresponding to the allowable current is set as the breakdown voltage, a wafer map of the breakdown voltage is created on the entire surface of the test wafer, and test wafers with various etching times of the polysilicon film are similarly prepared. Then, a wafer map of the breakdown voltage is created for each of the test wafers, and the test maps are formed on the entire test wafer from the wafer maps of the plurality of breakdown voltages. It is solved by the method for manufacturing a semiconductor device having a preliminary step breakdown voltage of the gate electrode group to determine the etch time of the polysilicon film serving as the predetermined specified value or more.

[Action]

In the present invention, prior to the manufacture of a product having a gate electrode group having a two-layer structure of a polysilicon film and a silicide film, the gate electrode group is formed in an area dividing the entire surface of the test wafer into a plurality of areas.

Test wafers with various etching times of the polysilicon film are created, and the voltage / current characteristics of the gate electrode group are measured for each area on the entire surface of these test wafers to create a wafer map of breakdown voltage. It is possible to determine etching conditions in which the gate electrode has a breakdown voltage value that should be satisfied as a device.

 The measurement can be easily performed electrically in a short time.

In this way, by applying the etching conditions determined in the preliminary process to the actual production, the product yield can be improved.

〔Example〕

FIG. 1 is a schematic view of a test element group (TEG) formed on the entire surface of the test wafer 1. The TEG is formed for each chip.

FIG. 2 is a partial plan view of the TEG formed in the chip, where 5a to 5c are test gate electrode groups and 8a to 8c are test electrode groups.

FIG. 3 is a sectional view for explaining the manufacturing process of such a TEG, which is a sectional view taken along the line AA of FIG.

 Hereinafter, description will be given with reference to these figures.

See FIG. 3 (a). A Si wafer is used as the test wafer 1, and its surface is thermally oxidized to form a gate oxide film 2 having a thickness of 250 Å.

See FIG. 3B. A 0.15 μm thick first polysilicon film 3 and a 0.20 μm thick tungsten silicide film 4 are formed on the entire surface by a CVD method.

Furthermore, phosphorus (P ⁺ ) is ion-implanted on the entire surface. The acceleration voltage is 70 keV and the dose is 1E15 cm ^-2 .

See FIG. 3C. A mask for forming a gate electrode group having the same shape as that used for manufacturing the product is formed, and the tungsten suicide film 4 is first removed from the opening by dry etching. Then, the first polysilicon film 3 is removed by dry etching.

The dry etching of the first polysilicon film 3 was performed for 40 seconds as a reference etching time obtained from a reference etching rate with respect to the etching amount of the polysilicon 3 for obtaining a predetermined breakdown voltage.

Thus, test gate electrode groups 5a, 5b, 5c having a two-layer structure of the first polysilicon films 3a, 3b, 3c and the tungsten silicide films 4a, 4b, 4c were formed. If these gate electrode groups 5a, 5b, 5c are formed as designed for the mask, the gate length is 1.2 μm and the distance between the gates is 1,3 μm.

See Fig. 3 (d). After depositing a 0.4 µm thick SiO ₂ film on the entire surface by the CVD method, the SaO ₂ film is removed by etching by reactive ion etching, and the test gate electrode groups 5a, 5b, The SiO ₂ side wall 6 is formed on the side surface of 5c.

See FIG. 3 (e). After depositing a SiO ₂ film 7 having a thickness of 0.1 μm on the entire surface by the CVD method, Si in each intermediate region of the test gate electrode groups 5a, 5b, 5c
By removing the O ₂ film 7 and the gate oxide film 2, the wafer surface is exposed and an electrode window is provided.

See Fig. 3 (f). As a conductive film on the entire surface, a second film with a thickness of 0.2 μm was formed by the CVD method.
Forming a polysilicon film. This second polysilicon film is patterned to form test electrode groups 8a to 8c. The width of each electrode of the test electrode groups 8a to 8c is, for example,
2.3 μm, and the distance between the electrodes is, for example, 1.5 μm.

In this way, the test gate electrode groups 5a to 5c and the test electrode groups 8a to 8c were formed on the test wafer 1. These electrode groups are formed for each chip.

The measuring needle was set on the pad shown in FIG. 2 to measure the voltage / current characteristics between the test gate electrode groups 5a to 5c and the test electrode groups 8a to 8c for each chip. Then, the voltage when a current of 1 μA flows was defined as the breakdown voltage, and the breakdown voltage was written for each chip on the entire surface of the test wafer 1 to create a wafer map of the breakdown voltage.

The higher the breakdown voltage, the better from the standpoint of withstand voltage. However, the breakdown voltage of the allowable limit that must be guaranteed as a device is, for example, 14 V, and the region where the breakdown voltage is lower than this specified value is the test wafer. Shown above 1.

FIG. 4 shows an example of a breakdown voltage wafer map, and the shaded region is a region having a breakdown voltage lower than a specified value. In the case of the reference etching time of 40 seconds described above, about 50% of the chips of the entire test wafer 1 were contained in this area.

FIG. 6 shows a sectional view of a gate electrode having a low withstand voltage.
Due to insufficient etching of the first polysilicon film 3, the thickness of the insulating film between the first polysilicon film 3 and the second polysilicon film 8 is insufficient, and as a result, the withstand voltage is low. Even in the case of the standard etching time, about half is under-etched.

Therefore, dry etching of the first polysilicon film 3 is performed.
Overetching amount 3 against the standard etching time
%, That is, a test map that was overetched by extending the time by 3% and a test wafer that was overetched by 5% were created to create a wafer map of breakdown voltage.

The region where the breakdown voltage was lower than the specified value decreased as the amount of overetch increased.

FIG. 5 shows the relationship between the amount of over-etch and the yield rate of dielectric strength in the wafer. The non-defective rate is 50% when the overetch amount is 0, and 70% and 95% when the overetch amount is 3% and 5%. The non-defective rate seems to be saturated at 95%, but the remaining defective rate is considered not to be due to the etching mode, but due to the foreign matter mode due to the inclusion of foreign matter.
Therefore, it can be seen that if the overetching amount is 5%, defects due to the etching mode hardly occur.

In the actual manufacturing process, when the gate electrode group having the two-layer structure of the polysilicon film 3 and the tungsten silicide film 4 is manufactured, the etching of the polysilicon film 3 is referred to the reference etching by referring to the result obtained from the preliminary process. It is possible to improve the withstand voltage non-defective rate to nearly 100% by extending the time by 5% with respect to the time, and the method of determining the etching time by the preliminary step of the present invention is the withstand voltage in the actual manufacturing process. It was shown to be effective in improving the yield rate.

〔The invention's effect〕

As described above, according to the present invention, the gate electrode group having the two-layer structure of the polysilicon film and the silicide film is provided.
The product yield of MOS transistors can be improved.

The present invention largely contributes to miniaturization of MOS transistors.

[Brief description of drawings]

FIG. 1 is a schematic view of a TEG formed on the entire surface of the wafer, FIG. 2 is a partial cross-sectional view of the TEG, and FIGS. 3A to 3F are cross-sectional views for explaining the TEG manufacturing process, and FIG. Is an example of a wafer map of breakdown voltage, FIG. 5 is a diagram showing the relationship between the amount of over-etching and the withstand voltage non-defective rate, and FIG. In the figure, 1 is a test wafer and a Si wafer, 2 is an insulating film and a gate oxide film, 3,3a to 3c are polysilicon films, and a first polysilicon film and 4,4a to 4c are The silicide film is a tungsten silicide film, 5a, 5b, 5c are test gate electrode groups, 6 is an insulating film and SiO ₂ side wall, 7 is an insulating film, SiO ₂ film, and 8a, 8b, 8c are first The second polysilicon film represents a test electrode group.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 H01L 29/78 301T

Claims (1)

(57) [Claims] 1. When forming a gate electrode group in which polysilicon and silicide are laminated in this order on the wafer surface via an insulating film, a plurality of test wafers (1) having test element groups on the entire surface are prepared, Test wafers (1)
A method of manufacturing a semiconductor device, comprising a preliminary step of determining the manufacturing conditions of the gate electrode group from the measurement of the electrical characteristics of the semiconductor wafer, wherein a polysilicon film ( 3) and a silicide film (4) are stacked in this order, and the silicide film (4) and the polysilicon film are formed by using a mask for forming gate electrode groups in a plurality of areas dividing the entire surface of the test wafer (1). Group of test gate electrodes (5a to 5c) by selectively etching the film (3)
And forming a side wall insulating film (6) covering the side surfaces of the test gate electrode group (5a to 5c), and then forming the test gate electrode group (5a to 5c) and the side wall insulating film (6).
After the insulating film (7) is formed on the entire surface of the test wafer (1) including, the side surfaces of the test gate electrode group (5a to 5c) are covered with the side insulating film (6). The insulating film (7) and (2) are removed to form an electrode window exposing the test wafer (1), a conductive film is deposited on the entire surface, and then the conductive film is patterned to form a test electrode group. (8a to 8c) are formed, and the voltage-current characteristics between the test gate electrode group (5a to 5b) and the test electrode group (8a to 8c) are measured for each area to obtain an allowable current limit. A corresponding voltage is defined as a breakdown voltage, a wafer map of the breakdown voltage is created on the entire surface of the test wafer (1), and similarly, test wafers with various etching times of the polysilicon film (3) are created. And destroy those test wafers Create a wafer map of pressure, from the wafer map of the plurality of breakdown voltage, substantially over the entire surface of the test wafer, the test gate electrodes (5a to
5. A method for manufacturing a semiconductor device, which comprises a preliminary step of determining an etching time of a polysilicon film (3) having a breakdown voltage of 5c) which is equal to or higher than a predetermined specified value.