TW414972B - Antenna structure of wafer level - Google Patents

Antenna structure of wafer level Download PDF

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Publication number
TW414972B
TW414972B TW88115260A TW88115260A TW414972B TW 414972 B TW414972 B TW 414972B TW 88115260 A TW88115260 A TW 88115260A TW 88115260 A TW88115260 A TW 88115260A TW 414972 B TW414972 B TW 414972B
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Taiwan
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region
polycrystalline silicon
antenna
tunneling
charge
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TW88115260A
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Chinese (zh)
Inventor
Chung-Rung Lin
Shin-Ming Chen
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Taiwan Semiconductor Mfg
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Abstract

An antenna structure formed on a semiconductor substrate and a method of collecting plasma charge quantitatively for detecting antenna effect are provided. The antenna structure includes an EEPROM structure and an antenna having a plurality of metal lines formed on an inter-line dielectric layer. A plug connects to tunnel region of the EEPROM structure for collecting plasma charge. The method of the present invention comprises: collecting plasma charge in a plasma etching process by the antenna having a plurality of metal lines; storing the plasma charge in a polysilicon gate of the EEPROM structure; measuring the variation or shifting of the threshold voltage rVt of a single polysilicon gate of the EEPROM structure, and measuring the gate coupling ratio aG and total capacitance Ctotal of the EEPROM structure for calculating the collected plasma charge QF.

Description

A7 B7 414972 五、發明説明() 發明領域: 本發明係有關於半導體製程中 控’特别是指-種利用可電抹除程式唯 碁之品質監 及附加之天線結構收集電裝触刻之二'•憶體(EEPROW 到損傷之程度。 何Μ監蜊氧化層遭 1 .發明背景: 在超大型積體電路的製程中, 到數十萬個甚至數百萬個的數量級,因:―:元件數“ 步驟可達到數百甚至千餘次 片晶囬的” d? - ..I Λ ^ ^ ^母—步碟不管是微篆 或姓刻或者是况積都關係著最後 不管是: 人爲的菇技〇怂护k 7门他。因此,除了 人爲的嚴格管監控之外,經常仍需藉A7 B7 414972 V. Description of the invention () Field of the invention: The present invention relates to the control of semiconductor manufacturing processes, and in particular refers to the use of a quality monitor that can erase the program, and an additional antenna structure to collect electrical equipment touch marks. '• Memory body (EEPROW to the extent of damage. He Mian clam oxide layer suffered 1. Background of the invention: In the process of ultra-large integrated circuit, to the order of hundreds of thousands or even millions, because:-: The number of components "steps can reach hundreds or even thousands of wafers back" d?-..I Λ ^ ^ ^ ^ Mother-step disc whether it is micro 篆 or last name engraving or conditional product is related in the end no matter whether: For the skill of the mushroom 0 to protect him. Therefore, in addition to the strict control of artificial control, often still need to borrow

監視品質,更可许沾& w _丄 势輔助没備W 文了他的話係在疋件形成的同時s + , « 的空白居诚$在非元神匿 ::白£域同時形成一些£測元件’當 製程中損壤了,即可立即反映製程的疏失,=在J名 的製程參數調整,< 儀器,钵^ 而即刻作必要 儀調整。苍則在元件的晶片製程完 , 可能因爲-環節的疏失’導致元件是铋的非养 期性失敗。 义件最後的非《 舉例而T,氧化層對蝕刻用電敢 i 止忐s舌士电何*極爲敏感’勒 重氡化屬損傷,特别是次微米製程(sub-fflicr process) 至深次微米製程^卜^^。^^ess 元件儿成並等待進行内連線介電層及内連線時的情況更扣 iIT線* (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消旁合作社印製Monitor the quality, but also allow Zhan & w _ 丄 potential auxiliary did not prepare W. His words are at the same time as the formation of the file s +, «The blank Jucheng $ in the non-primordial hidden :: White £ field at the same time formed some When the measuring element is damaged in the manufacturing process, the fault of the process can be immediately reflected, = the process parameter adjustment in the J name, < instrument, bowl ^, and the necessary instrument adjustment is made immediately. Cang finished the wafer process of the device, which may cause the non-nutritional failure of the device to be bismuth because of the omission of the link. The last part of the manuscript is "For example, T, the oxide layer is very sensitive to the electric power used for etching. It is extremely sensitive. It is a serious damage, especially the sub-fflicr process. Micron process ^ 卜 ^^. ^^ ess Components are waiting for the interconnection dielectric layer and the situation when the interconnection is deducted from the iIT line * (Please read the precautions on the back before filling this page) system

414972 A7 B7 五、發明説明() (請先閲讀背面之注意事項再填寫本頁} 需要特别注意。因此,就以積體電路晶片之製程而言,經 常的做法是在製程的過程中於晶圓之非元件的空白區同時 形成複數個金屬天線結構元件,用以監視蚀刻用電漿電荷 量的大小情形。 如圖一 A及B分别示的元件即爲傳統金屬天線監視結 構的橫截面示意囷及俯視囷,本結構利用大片的導體面積 1,例如金屬天線,形成在厚氧化層2處,再連接至相對較 小面積之閘極電極上,該處具有薄氧化層4而金屬天線* 上則有光阻圖案5 » 天線結構隨著曝露於電漿的時間所收集之心或rf電 流在薄氧化層4處增加F〇wler_N〇rdheim穿隧電流密度。 在天線結構之薄氧化層4受到收第之Fowler-N〇rdheim穿 隧黾流之施壓(stressed)後將收禁之電荷流出.,再進行電 性測試,用以量度此電荷流過氧化層所造成損傷的程度, 例如斜坡電壓VBI)(ramped-voltage)或電荷對崩潰測試 (charge-to-breakdown)QBD等,藉以了解電漿電荷對氧化 層損傷的情況’也即傳統方法係屬於電荷陷阱機制(charge trapping)的一種。 經濟部智慧財產局員工消費合作社印製 然而’傳統天線結構通常只能疋性的了解電聚電荷, 經常需要至氧化層崩潰了才知道電漿電荷量的嚴重性,囡 爲電衆電荷量致氧化層崩潰可能是因一次姓刻大量的電衆 電荷即已產生,也可能係長期累積每次少量的電衆電荷所 致,致使那一蝕刻製程最易造成的判定有不確定性,其次, 對於收集之電漿電荷的極性也是不可知的。 本紙張尺度遙用中國國家榡準(CNS ) A4規格(210X297公釐) 414972 A7 B7 五、發明説明() 本發明將提供一可以定量 佳的蝕刻製程。 的解決方法’並藉此提供最 發明目的及概述: 經濟部智慧財產局員工消費合作社印製 本發明之一目的係提供一餅u 祈天線結構可用以定量得 監視電漿損傷以解決傳統方法之夭给4士 〇 $ π 疋天線結構只能定性不能 定量所衍生之問題。 本發明之另一目的係解決值姑、、丄 Τw得統万法之天士 知道致使氧化層崩潰之主要電級指 ^ … 戈哥戒損傷在那一製程產生的 問題β 本發明之再一目的係可以綠士 τ π Μ 、 2由不同蝕刻製程所造成 之電衆電荷量作比較以提供一較佳的蝕刻製程a 本發明係一種形成於半導體基板上之天線結構並同 時提供定量收集電漿電荷的方法,該天線結構包含一單一 複晶矽EEPROM結構,及一内連線介電層形成於單一複晶 矽EEPROM結構上及一具有複數支金展線之天線形成於内 連線介電層上,天線經由一插塞和該單—複晶矽EEpR〇M 結構之穿隧區相連接’用以收集電漿蝕刻過程中之電娘電 荷,本發明提供之方法至少包含:以該複數支金屬線之天 線接收電漿蝕刻製程中之電漿電荷,並存入單一複晶矽 EEPROM結構之該複晶矽閘極之中;接著,經由量度單一複 晶矽EEPROM結構之啓始電壓位移量AV,、閘極耦合比〇u, 及該單一複晶矽EEPROM部分之總電容量C嫌以關係式AVt = (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家揉隼(CMS ) A4规格(210X297公釐) 414972 A7 -------B7 五、發明説明() ac Qp/C *計算電漿電荷收禁的量QF。 4· 8式簡單説明: 本發明的較佳實施例將於往後之説明文字中輔以下 列圖形做更詳細的闡述: 圏一 A及B分别顯示傳統之天線結構的橫截面示意圖 及俯視圖。 圖一顯示本發明之天線結構之製造E EPROM部分進行 穿随氧化層形成步驟後之橫截面圈; 圖二類示本發明之天線結構之製造EEPROM部分進行. 懸浮閘極圉案化後之橫截面示意圖; 圏四顯示本發明之天線結構之製造EEPROM部分進行 至圖二之步骤後之俯視示意圖; 圖五顯示本發明之天線結構之製造EEPR〇h(部分的横 截面示意圖; 囷六顯示本發明之天線結構俯視示意圖; 阁七顯示利用本發明之新天線結構量測及極電流對 源没極電壓量取啓始電壓移位的範例圖;及 圖八顯示利用本發明之新天線結構依據不同之製程A 和B和收集之電漿電荷量作圈以了解何種製程較佳的範例 圖。 5 ·發明詳細説明: -5- 本紙張尺度遴用中固阐家標率(CNS ) Μ規格(2t〇X297公釐) t請先聞讀背面之注^^項存填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 414972 、發明説明( (請先聞讀背面之注意事項再填寫本頁) —如前述,俵紡尤& 荷,婉私 平純天線結構通常只能定性的了解電漿電 7 經吊需要至菌办a 性,牲θ 礼化層崩潰了才知道電漿電荷量的嚴重 符别是如果不圭 佳時,情況更_幸傳轭天線結構中之氧化廣品質特别不 不可知的…:即:次’對於收集之電製電荷的極性也是 了解電萊損傷情形傳统方法也可以用啓始電壓變化差異 現場,I & $ # β但任往那時氧化層已崩潰,一如災後 續株决率確反峡眞實情況。 佳的ϋέΐ 2將提供—可以定量的解決方法,並藉此提供最 住的蝕刻製程。 業1 μ發月(方法係藉由傳統之單一複晶矽EEPR〇M在覆 : 内連線介電廣上再形成金屬天線,並以插塞連接 木:〈穿隧區’藉由儲存之電漿電荷量定量得選擇最恰 H β τ將先説明傳統之單_複晶梦EEpRQM的製 造万法’再説明本發明之憤側原理。 經濟部智慧財產局員工消費合作社印製 製程步骤如下’如圖二所示’在半導體基板上之非元 :以習知技術定義淺溝渠隔離區(簡稱st[ ) 8,而在淺 溝渠隔離區8之兩外側則以高能量離子佈植以分别形成L 穿随h〇A及控制開極區1〇B,接著,以熱氧化製程形成 -層軋化| 15。隨後,再以光阻圖案及蝕刻技術蝕刻去除 部分之穿隧區上之氧化層15 ’用以曝露出矽基材5。隨後 以熱氧化製程再形成品質較佳之薄穿隧氧化層2〇以使電 荷能透過此薄氡化屠穿随而達到貯存或抹除電荷的能 力。 & -6- 本紙張Λ度通用中國國家標準(CNS ) A4規格(2[OX 297公釐) A7 414972 B7 五、發明説明() (請先閲讀背面之注意事項再填寫本頁) 請參考如圖三的示意圖,以LPCVD法首先形成一複晶 矽層2 5,接著再以光阻圖案3 0及蝕刻技術圖案化複晶矽層 2 5以定義懸浮閘極。 圖四係複晶矽層25經圖案化後之傳統EEPROM製程過 程之投影視圖。其中區域3 5係保留爲元件之源/汲極區。 圖五顯示EEPROM結構之橫截面示意圖。在去除光阻 圖案30之後一 CVD氧化層40作爲内連線介電層接著形成 於上述結果之上表面。 在形成控制閘極之接觸洞4 5以連接控制閘極區1 0 B 及穿隧區10A,及源/汲極區35的接觸洞(請同時參考圖六 之俯視圖,所有之接觸洞以”区表示)最後,再形成金屬 層50於内連線介電層40之上並利用光阻圖索48定義天線 並予以蝕刻成天線5 0即完成本發明之新天線結構=在天線 蝕刻之同時即可監測電漿電荷量。 圖七示利用本發明之新天線結構量測汲極電流對源 汲極電壓量取啓始電壓移位,藉此而獲得電漿電荷的量。 經濟部智慧財產局員工消资合作社印製 例如,囷中之曲線100係未接收電漿電荷前之電壓-電流曲線而曲線1 1 0係收集的電漿電荷爲正電荷所造成啓 始電壓移位的情形,當收隼的電漿電荷爲負電荷所造成啓 始電壓移位AVt的情形則如曲線1 2 0所示。收集的電荷量和 啓始電壓移位則有如下關係:Δν,= cu*Qp/C* 其中 OU係指閘極耦合比;414972 A7 B7 V. Description of the invention () (Please read the notes on the back before filling out this page} Special attention is needed. Therefore, as far as the manufacturing process of integrated circuit chips is concerned, it is common practice to use crystals during the process. A plurality of metal antenna structural elements are simultaneously formed in the blank area of the round non-element, which is used to monitor the amount of electric charge in the plasma. The elements shown in Figures A and B are schematic cross-sectional views of the traditional metal antenna monitoring structure.囷 and looking down, this structure uses a large area of conductor area 1, such as a metal antenna, formed at a thick oxide layer 2, and then connected to a relatively small area gate electrode, which has a thin oxide layer 4 and a metal antenna * There is a photoresist pattern on the top 5 »The antenna structure collects the heart or rf current with the exposure time to the plasma to increase the Föwler_Nórdheim tunneling current density at the thin oxide layer 4. The thin oxide layer of the antenna structure 4 After being stressed by the Fowler-N0rdheim tunneling flow, the banned charge flows out. Then, an electrical test is performed to measure the damage caused by this charge flowing through the oxide layer. Degrees, such as ramped-voltage (VBI) or charge-to-breakdown (QBD), to understand the damage of the plasma charge to the oxide layer, that is, the traditional method belongs to the charge trap mechanism (charge trapping). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, the traditional antenna structure usually only understands the electric charge accumulation, and it is often necessary to know the severity of the plasma charge amount until the oxide layer collapses. The breakdown of the oxide layer may be caused by a large number of electric charges that have been engraved at one time, or it may be caused by the accumulation of a small amount of electric charges every time for a long time, which makes the determination most likely to be caused by that etching process uncertain. The polarity of the collected plasma charge is also unknown. This paper uses China National Standard (CNS) A4 (210X297 mm) 414972 A7 B7. 5. Description of the invention () The invention will provide an etching process that can be quantitatively optimized. The solution of this problem is to provide the most inventive purpose and overview: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, one of the purposes of the present invention is to provide a pie antenna structure that can be used to quantitatively monitor the damage of plasma to solve the traditional method.夭 给 4 士 〇 $ π 疋 The antenna structure can only be qualitative but not quantitative. Another object of the present invention is to solve the problem of the main electrical level indicators that cause the oxide layer to collapse due to the fact that Tianshi knows that the system has collapsed....... The purpose is to compare the amount of electric charges caused by different etching processes to provide a better etching process. The present invention is an antenna structure formed on a semiconductor substrate and simultaneously provides a quantitative collection of electricity. In the method of slurry charge, the antenna structure includes a single polycrystalline silicon EEPROM structure, an interconnect dielectric layer is formed on the single polycrystalline silicon EEPROM structure, and an antenna with a plurality of gold spread lines is formed on the interconnect dielectric. On the electrical layer, the antenna is connected through a plug to the tunneling region of the single-crystal EEPROM structure to collect the electrical charge of the plasma during the etching process. The method provided by the present invention includes at least: The antennas of the plurality of metal wires receive the plasma charges in the plasma etching process and store them in the multiple silicon gates of the single polycrystalline silicon EEPROM structure; The voltage displacement AV, gate coupling ratio 0u, and the total capacitance C of the single polycrystalline silicon EEPROM part are related by the relationship AVt = (Please read the precautions on the back before filling this page) This paper size is applicable to China National Crush (CMS) A4 specification (210X297 mm) 414972 A7 ------- B7 V. Description of the invention () ac Qp / C * Calculate the amount of plasma charge prohibition QF. Brief description of formula 4.8: The preferred embodiment of the present invention will be explained in more detail in the following explanatory texts: 圏 A and B respectively show a schematic cross-sectional view and a top view of a conventional antenna structure. Figure 1 shows the cross section of the antenna structure of the present invention after the E EPROM part passes through the formation step of the oxide layer; Figure 2 shows the manufacturing of the EEPROM part of the antenna structure of the present invention. Sectional schematic diagrams; 24 shows a schematic plan view of the EEPROM part of the antenna structure of the present invention after proceeding to the step of FIG. 2; FIG. 5 shows the manufacturing of the antenna structure of the present invention EEPR0h (partial cross-sectional schematic diagram; Top view of the antenna structure of the invention; Geqi shows an example diagram using the new antenna structure measurement of the present invention and the initial voltage shift of the source current to the source and terminal voltage measurement; and FIG. 8 shows the basis of using the new antenna structure of the present invention. Different processes A and B and collected plasma charge amounts are used as a circle to understand which process is the best example. 5 · Detailed description of the invention: -5- This paper uses the Chinese solid standard (CNS) M Specifications (2t〇X297mm) t Please read the note on the back ^^ to save this page and fill in this page) Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 414972, invention description ((Please read first Note on the back, please fill in this page again) —As mentioned above, the pure antenna structure of Chifangyou & Holland, Wansuiping can only understand the plasma and electricity qualitatively. Only after the collapse did I know the serious difference in the amount of plasma charge. If it is not good, the situation is even better. Fortunately, the quality of the oxidized antenna in the yoke antenna structure is particularly unknown ... The polarity is also the traditional method to understand the damage situation of Dian Lai. The initial voltage change field can also be used. I & $ # β However, the oxide layer has collapsed at that time, as the subsequent plant disaster rate is indeed against the actual situation of the isthmus. 2 will provide—quantitative solutions, and provide the most efficient etching process. Industry 1 μ hair month (method is based on the traditional single polycrystalline silicon EEPR〇M overlay: Interconnect dielectric wide Form a metal antenna and connect the plug with a plug: "Tunneling area 'uses the amount of stored plasma charge to quantify and select the most accurate H β τ will first explain the traditional single _ compound crystal dream EepRQM manufacturing method' and then explain The indignation principle of the present invention. The steps of the printing process of the bureau ’s consumer cooperatives are as shown in Figure 2. The non-elements on the semiconductor substrate: Define the shallow trench isolation zone (referred to as st [) 8 by conventional techniques, and on both sides of the shallow trench isolation zone 8 High-energy ions were implanted to form the L-passage hOA and the control open-pole region 10B, respectively, and then formed by thermal oxidation-layer rolling. 15. Then, it was etched by photoresist pattern and etching technology. The oxide layer 15 'on the part of the tunneling region is removed to expose the silicon substrate 5. Then, a thin tunneling oxide layer 20 with better quality is formed by a thermal oxidation process so that the charges can pass through the thinned and pass through. To achieve the ability to store or erase charge. &Amp; -6- The paper Λ degree is common Chinese National Standard (CNS) A4 specification (2 [OX 297 mm) A7 414972 B7 V. Description of the invention () (Please read the back first Please refer to the diagram on this page for details. Please refer to the schematic diagram in Figure 3. First, a crystalline silicon layer 25 is formed by LPCVD, and then the polycrystalline silicon layer 25 is patterned with photoresist pattern 30 and etching technology to define. Suspension gate. FIG. 4 is a projection view of a conventional EEPROM process process after the polycrystalline silicon layer 25 is patterned. The region 35 is reserved as the source / drain region of the device. Figure 5 shows a schematic cross-sectional view of the EEPROM structure. After the photoresist pattern 30 is removed, a CVD oxide layer 40 as an interconnect dielectric layer is then formed on the above surface. The contact holes 45 of the control gate are formed to connect the contact holes of the control gate region 10B and the tunneling region 10A, and the source / drain region 35 (please also refer to the top view of FIG. 6, all contact holes start with " Area indication) Finally, a metal layer 50 is formed on the interconnecting dielectric layer 40 and the antenna is defined by a photoresist cable 48 and etched into the antenna 50 to complete the new antenna structure of the present invention = while the antenna is being etched The amount of plasma charge can be monitored. Figure 7 shows the use of the new antenna structure of the present invention to measure the drain current and shift the source-drain voltage to the starting voltage, thereby obtaining the amount of plasma charge. Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperative, for example, the curve 100 in Langzhong is the voltage-current curve before receiving the plasma charge and the curve 1 10 is the initial voltage shift caused by the collected plasma charge being a positive charge. The initial voltage shift AVt caused by the negatively charged plasma charge is shown in the curve 1 2 0. The amount of charge collected and the initial voltage shift have the following relationship: Δν, = cu * Qp / C * where OU refers to the gate coupling ratio;

Qp係指電漿電荷收隼的量; 本紙張尺度適用中國國家揉準(CNS ) A4規格(210X297公釐) 414972 五、 發明説明() A7 B7 而 c *係EEPROM部分之總電容量 :上=可以輕易的計算收集之電漿電荷量。 量作圏以了解何種製程較佳,例如和 ::收集之…荷 收集之電衆電荷量較低,因此”製二:之B製程顯然因 *•程.沈比A製程佳。 由以上之論述可知本發明具有以下之優點 ⑴ ㈣㈣構所用之咖顧部分 以毫不困難的和一般邏輯電路或相當之元件 (logic-compatible Drη广。 'Qp refers to the amount of charge collected in the plasma; This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 414972 V. Description of the invention () A7 B7 and c * is the total capacitance of the EEPROM part: above = Can easily calculate the amount of plasma charge collected. Measure to understand what kind of process is better, for example, and :: Collect ... The amount of electric charge collected by the charge is low, so the "B" process of "Second: The process is obviously better than the" A "process. From the above From the discussion, it can be seen that the present invention has the following advantages: 咖 The structure of the client is based on logic and compatible components that are not difficult and general (logic-compatible).

Pr〇CeSs )—起製作,囡此實 施容易。 (2 )纟發明之新天線結構可用以監視電漿損傷, 特别是在小尺寸之薄閘極氧化屬。 (3)本發明之新天線結構所用之EEPROM部分且有 比傳統之MOS(金氧半)元件更靈敏,因此即使少量 之電漿損傷也可以很容易知道β (〇 依據不同之製程和分别收篥之電漿電荷量作 圖,可用以了解何種製程較佳。 (請先聞讀背面之注意事項再填寫本頁) ,ιτ 镍丨· 經濟部智慧財產局員工消費合作社印t 限之請 以示申 用揭之 非所述 並明下 ,發在 已冬含 而離包 例脱應 施未均 實它 ’ 佳其飾 較凡修 之;或 明圍變 發範改 本利效 爲專等 僅請之 述申成。 所之完内 上明所圍 以發下範 本神利 定精專 本紙張尺度遑用中國國家標準(CNS >Α4規格(210x297公* )Pr〇CeSs) —produced from the beginning, so it is easy to implement. (2) The new antenna structure invented by 纟 can be used to monitor plasma damage, especially in small-sized thin gate oxides. (3) The EEPROM part used in the new antenna structure of the present invention is more sensitive than the traditional MOS (metal-oxide-semiconductor) element, so even a small amount of plasma damage can be easily known β (0 according to different processes and separately Plot the amount of charge in the plasma, which can be used to understand which process is better. (Please read the notes on the back before filling this page), ιτ Nickel In order to show the application of the uncovered and unexplained, issued in the winter has been removed from the package and should not be applied evenly, 'Jiaqi decorative than Fan Xiu's; Only the description is requested. The end of the paper is enclosed in the form of a copy of the Shenliding fine paper. The Chinese standard (CNS > A4 size (210x297) *)

Claims (1)

經濟部智慧財產局員工消費合作社印製 414972 六、申請專利範圍 至少包含: 一半導體基板上具有一單一複晶矽(single ροΐ7)·ϊ 電抹除程式唯讀記憶體(EEPR0M)結構; 一内連線介電層形成於該單一複晶矽EEPROM結構i 上;及 具有複數支金屬線之天線形成於該内連線介電j 上並經由一插塞和該單_複晶ί夕EEPROM結構之穿隧區才| 碑.舞’用以收禁電衆独刻過程中之電聚電荷。 2 如^1項之天線結構’其中上迷之EEpR⑽乡 構至少包含: 兩個淺溝渠隔離區位於該半導體基板之中; 一第一雜質摻雜區位於該半導體基板之中且位於令 兩個淺溝渠隔離區其中一個之一外側邊,用作爲電荷吳 隧區; 一第二雜質摻雜區位於該半導體基板之中 〜T且位於I 兩個淺溝渠隔離區其餘一個之一外側邊,用以作皮k W Λ邛馬控制R 極,該兩個淺溝渠隔離區之兩個内側邊爲源/访V %蚀區所夕 隔; 一第一氧化層形成於該半導體基板之上,玆笛 嗥第一氧ί 層具有'穿隧接觸洞形成於其中且該穿隧接觸祠和該冥 隧區域速接; -9- :張尺度適財關研準(CNS)A4規格⑽x 297公釐> --------- ---I------I I ^ · ----If— 訂-----I ---線 1 f請先閱讀背面之注意事項再填寫本頁) ^4972 A8 B8 C8 ------------- 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 —穿随氧化層形成於該穿隧接觸洞之中該穿隧區域 之上;及 一複晶梦閘極,形成於穿隧氧化層與第一氧化層上, 並且由該穿随區至該控制閘極區,該複晶矽閘極並且分隔 該源/ >及極區,且該複晶矽閘極在控制閘極區之面積大於 在該穿随區之面積’且該複晶矽閛極在該穿隧區之面積大 於該源/汲極區的部分。 3.—種形成於半導體基板上之天線結構用以定量收集電 衆電荷的方法’該天缘結構包含—單一複晶矽EEPR01A結 構’及一内連線介電層形成於該單一複晶矽eEPR〇m結構 上及一具有複數支金屬線之天線形成於該内連線介電層 上並經由一插塞和該單—複晶矽EEPR0M結構之穿隧區相 連接,用以收隼電漿蝕刻過程十之電漿電荷,該方法至少 包含: 以該複數支金屬線之天線接收電漿蝕刻製程中之電 聚電荷’並存入該單一複晶矽EEpR〇M結構之該複晶梦閘 極之中; 量度該單一複晶矽ΕΕΡβ0Μ結構之啓始電壓位移量 Δν,;及 利用該啓始電壓位移量Δν,、一閘極耦合比,及該單 一複晶矽EEPROM部分之總電容量c *以關係式Δν,:= 〇c,Qr/C *計算收集的該電漿電荷量qf。 -10- 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐> (請先閱讀背面之注意事項再填寫本頁) ---- LSJ ---------線 414972 A8 B8 C8 D8 申請專利範圍Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 414972 6. The scope of the patent application includes at least: a semiconductor substrate with a single polycrystalline silicon (single ροΐ7) · ϊ electric erase program read-only memory (EEPR0M) structure; A connection dielectric layer is formed on the single polycrystalline silicon EEPROM structure i; and an antenna having a plurality of metal lines is formed on the interconnect dielectric j and passes through a plug and the single_multicrystalline EEPROM structure. Only in the tunneling area | Stele. Dance 'is used to collect electric charges in the process of banning electricity. 2 The antenna structure of item ^ 1, wherein the above-mentioned EEpR⑽ rural structure includes at least: two shallow trench isolation regions are located in the semiconductor substrate; a first impurity-doped region is located in the semiconductor substrate and is located in two An outer side of one of the shallow trench isolation regions is used as a charge tunnel region; a second impurity-doped region is located in the semiconductor substrate ~ T and is located on one of the remaining one of the two shallow trench isolation regions. It is used to control the k W Λ 邛 horse control R pole. The two inner sides of the two shallow trench isolation areas are separated by the source / visit V% etch area. A first oxide layer is formed on the semiconductor substrate. In the above, the first oxygen layer of Zidi 嗥 has a 'tunneling contact hole formed therein and the tunneling contact temple and the tunnel area are quickly connected; -9-: Zhang Jiji Shicai Guan Yanquan (CNS) A4 specification⑽x 297 mm > --------- --- I ------ II ^ · ---- If— Order ----- I --- Line 1 f Please read the back first Please pay attention to this page before filling in this page) ^ 4972 A8 B8 C8 ------------- VI. Application for Patent Formed on the tunneling area in the tunneling contact hole; and a polycrystalline dream gate formed on the tunneling oxide layer and the first oxide layer, and from the through region to the control gate region, The polycrystalline silicon gate and separates the source and the electrode region, and the area of the polycrystalline silicon gate in the control gate region is larger than the area of the penetrating region 'and the polycrystalline silicon gate is in the penetrating region. The area of the tunnel region is larger than that of the source / drain region. 3. A method of antenna structure formed on a semiconductor substrate to quantitatively collect electric charges 'The sky edge structure includes-a single polycrystalline silicon EEPR01A structure' and an interconnect dielectric layer is formed on the single polycrystalline silicon The eEPR0m structure and an antenna with a plurality of metal wires are formed on the interconnect dielectric layer and connected to the tunneling region of the single-complex silicon EEPR0M structure through a plug for receiving electricity. Plasma charge during the plasma etching process, the method at least includes: receiving the poly-charges in the plasma etching process with the antennas of the plurality of metal wires and depositing the multiple crystal dreams into the single crystal silicon EEPROM structure of the multiple crystal dream. Among the gates; Measure the starting voltage displacement Δν of the single polycrystalline silicon EEPβ0M structure; and use the starting voltage displacement Δν, a gate coupling ratio, and the total power of the single polycrystalline silicon EEPROM portion The capacity c * is calculated by the relationship Δν, == 0c, Qr / C *, and the collected plasma charge qf is calculated. -10- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page) ---- LSJ -------- -Line 414972 A8 B8 C8 D8 patent application scope (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐)(Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the national standard (CNS) A4 specification (210 X 297 mm)
TW88115260A 1999-09-03 1999-09-03 Antenna structure of wafer level TW414972B (en)

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