JP3232569B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, a MIS for monitoring characteristics in a semiconductor integrated circuit
It is suitable for application to a transistor.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit such as a MOS LSI, in order to monitor whether or not desired transistor characteristics are obtained after a wafer process is completed, a single characteristic monitoring MOS transistor is provided inside the semiconductor integrated circuit body. Free space or TEG (test element grou
p) formed in the region.

FIGS. 3 and 4 show an example of a characteristic monitoring MOS transistor conventionally used in a MOS LSI. As shown in FIGS. 3 and 4, for example, p
A field insulating film 102 is formed on the surface of a mold silicon (Si) substrate 101, thereby separating elements. A gate insulating film 103 is formed on the surface of the active region surrounded by the field insulating film 102. Reference numeral 104 denotes a gate electrode formed of a polycrystalline Si film doped with an impurity.

A gate electrode 10 is provided in a p-type Si substrate 101.
An n ⁺ -type source region 105 and a drain region 106 are formed in a self-alignment manner with reference to FIG.

Reference numeral 107 denotes an interlayer insulating film. Reference numerals 108, 109, and 110 indicate aluminum (Al) wiring. Here, the Al wiring 108 is connected to one end portion 104a where the width of the gate electrode 104 is increased through a contact hole 107a formed in the interlayer insulating film 107. Further, the Al wiring 109 is formed by contact holes 107b, 107c, 10c formed in the interlayer insulating film 107.
7d, it is connected to the source region 105. Further, the Al wiring 110 is connected to the drain region 106 through contact holes 107e, 107f, and 107g formed in the interlayer insulating film 107.

[0006]

As described above, the characteristic monitoring MOS transistor is formed in an empty space or the like in the main body of the semiconductor integrated circuit. Therefore, the characteristic monitoring MOS transistor is formed around the gate electrode 104 of the characteristic monitoring MOS transistor. Has no other gate electrode. That is, it can be said that the gate electrode 104 of the characteristic monitoring MOS transistor is sparse. On the other hand, M of the semiconductor integrated circuit itself
The gate electrode of the OS transistor is formed densely.

When a resist pattern is formed by photolithography, a sparse resist pattern has a larger pattern width than a dense resist pattern, even if the pattern width on a photomask (or reticle) is the same. There is nature. For this reason, even if the gate electrode 104 of the characteristic monitoring MOS transistor is designed to have the same width as the gate electrode of the MOS transistor of the semiconductor integrated circuit itself, as described above,
Since the gate electrode 104 of the transistor is sparser than the gate electrode of the MOS transistor of the semiconductor integrated circuit itself, the width of the gate electrode 104 of the MOS transistor for characteristic monitoring actually formed is smaller than that of the MOS transistor of the semiconductor integrated circuit itself. Becomes larger than the width of the gate electrode. As a result, there has been a problem that even if the characteristics of the characteristic monitoring MOS transistor are measured, the characteristics of the MOS transistor of the semiconductor integrated circuit itself cannot be accurately monitored.

Accordingly, an object of the present invention is to provide a semiconductor device which can accurately monitor the characteristics of the MIS transistor of the semiconductor integrated circuit itself by measuring the characteristics of the MIS transistor as a MIS transistor for monitoring characteristics. It is in.

[0009]

In order to achieve the above-mentioned object, according to the present invention, a gate electrode (4) is formed on a semiconductor substrate (1) via a gate insulating film (3). In a semiconductor device in which a source region (5) and a drain region (6) are formed in (1), dummy layers (7, 8) made of the same material as the gate electrode (4) are formed on the gate electrode (4). Extending over the semiconductor substrate (1) along the gap between the gate electrode (4) and the dummy layers (7, 8).
The interval is the gate of the MIS transistor of the semiconductor integrated circuit itself.
The distance is set to be substantially the same as the distance between the source electrodes (5) and the drain region (6) via the dummy layers (7, 8) on the source region (5) and the drain region (6). (11, 12) are connected.

[0010]

According to the semiconductor device of the present invention configured as described above, the distance between the gate electrode (4) and the dummy layers (7, 8) extending along the gate electrode (4) is increased. For example, the resist pattern for forming the gate electrode (4) of the semiconductor device and the gate electrode of the MIS transistor of the semiconductor integrated circuit are set to be substantially the same as the distance between the gate electrodes of the MIS transistor of the semiconductor integrated circuit itself. A difference in density from a resist pattern to be formed can be eliminated. Therefore, the width of the gate electrode (4) of the semiconductor device can be made substantially the same as the width of the gate electrode of the MIS transistor of the semiconductor integrated circuit itself. Thus, the characteristics of the MIS transistor of the semiconductor integrated circuit itself can be accurately monitored by using the semiconductor device as a characteristic monitoring MIS transistor and measuring the characteristics.

In addition, wirings (1) are formed on the source region (5) and the drain region (6) via the dummy layers (7, 8) to the source region (5) and the drain region (6), respectively.
1, 12), the parasitic resistance of the source and the drain can be sufficiently reduced.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a characteristic monitoring MOS transistor according to an embodiment of the present invention, and FIG.
2 is a sectional view taken along line 2-2 of FIG.

As shown in FIGS. 1 and 2, in this embodiment, a field insulating film 2 such as an SiO ₂ film is formed on a surface of a semiconductor substrate 1 such as a p-type Si substrate. Element isolation is performed. On the surface of the active region surrounded by the field insulating film 2, a gate insulating film 3 such as a SiO ₂ film is formed.
Reference numeral 4 indicates a gate electrode. The gate electrode 4 is made of polycrystalline doped with an n-type impurity such as phosphorus (P).
It is formed by a Si film.

In the semiconductor substrate 1, for example, an n ⁺ -type source region 5 and a drain region 6 are formed in self-alignment with the gate electrode 4.

In this embodiment, dummy layers 7 and 8 extend on both sides of the gate electrode 4 along the gate electrode 4. These dummy layers 7 and 8 are made of the same material as the gate electrode 4. Both ends of these dummy layers 7 and 8 are on the field insulating film 2, and portions between them are in contact with the source region 5 and the drain region 6 by buried contacts. Here, the interval between the gate electrode 4 and these dummy layers 7 and 8 is set substantially equal to the interval between the gate electrodes of the MOS transistors of the semiconductor integrated circuit itself, for example, its peripheral circuits. When there are a plurality of intervals between the gate electrodes of the MOS transistors of the semiconductor integrated circuit itself, the interval is set to, for example, the largest of these intervals.

These dummy layers 7 and 8 serve as gate electrodes (not shown) of MOS transistors of the semiconductor integrated circuit itself.
And in the step of forming the gate electrode 4 of the characteristic monitoring MOS transistor. That is,
After forming the field insulating film 2 and the gate insulating film 3, a polycrystalline Si film for forming a gate electrode is formed on the entire surface by a CVD method. Next, the polycrystalline Si film is doped with an n-type impurity such as P to reduce the resistance. Next, a resist pattern (not shown) having a shape corresponding to the gate electrode of the MOS transistor of the semiconductor integrated circuit itself, the gate electrode 4 of the characteristic monitoring MOS transistor, and the dummy layers 7 and 8 is formed on the polycrystalline Si film. It is formed by photolithography. Thereafter, the polycrystalline Si film is subjected to, for example, reactive ion etching (R
Etching is performed by the IE) method. Thereby, the dummy layers 7 and 8 are formed together with the gate electrode of the MOS transistor of the semiconductor integrated circuit itself and the gate electrode 4 of the characteristic monitoring MOS transistor.

Reference numeral 9 denotes, for example, phosphorus silicate glass (P
SG) and an interlayer insulating film such as a SiO ₂ film. Also,
Reference numerals 10, 11, and 12 indicate, for example, Al wiring. here,
The Al wiring 10 is connected through a contact hole 9 a formed in the interlayer insulating film 9 to one end 4 a where the width of the gate electrode 4 is increased. Further, the Al wiring 11 is connected to the dummy layer 7 through the contact holes 9b, 9c, 9d formed in the interlayer insulating film 9 on the source region 5. As described above, since the dummy layer 7 is in contact with the source region 5, the Al wiring 11 is connected to the source region 5 via the dummy layer 7. Further, the Al wiring 12 has a contact hole 9 e formed in the interlayer insulating film 9 on the drain region 6,
It is connected to the dummy layer 8 through 9f and 9g. Since the dummy layer 8 is in contact with the drain region 6, the Al wiring 11 is connected to the drain region 6 via the dummy layer 8.

The characteristic monitoring MOS transistor according to this embodiment having the above-described structure is formed in an empty space in a semiconductor integrated circuit body, for example, in an empty space between pads in a peripheral portion of a semiconductor integrated circuit chip.

As described above, according to this embodiment, the dummy layers 7, 8 made of the same material as the gate electrode 4 extend along the gate electrode 4, and the gate electrode 4 and the dummy layers Since the distance between the gate electrodes 7 and 8 is set substantially equal to the distance between the gate electrodes of the MOS transistors of the semiconductor integrated circuit itself, the gate electrodes of the MOS transistors of the semiconductor integrated circuit itself and the gates of the characteristic monitoring MOS transistors are provided. In a photolithography process for forming a resist pattern for forming the electrode 4, a resist pattern for forming the gate electrode 4 of the characteristic monitoring MOS transistor and a gate electrode of the MOS transistor of the semiconductor integrated circuit itself are formed. The difference in density from the resist pattern can be eliminated. Thus, the width of the gate electrode 4 of the characteristic monitoring MOS transistor can be made equal to the width of the gate electrode of the MOS transistor of the semiconductor integrated circuit itself. Therefore, by measuring the characteristics of the characteristic monitoring MOS transistor, the MOS of the semiconductor integrated circuit itself is measured.
The characteristics of the transistor can be accurately monitored.

On the source region 5, the wiring 11 is connected to the dummy layer 7 through the contact holes 9b, 9c and 9d.
And the wiring 12 is in contact with the dummy layer 8 through the contact holes 9e, 9f, and 9g on the drain region 6, so that the parasitic resistance of the source and the drain can be sufficiently reduced.

The MOS transistor for characteristic monitoring according to this embodiment is a bipolar CM in addition to a MOS LSI.
It is suitable for application to a characteristic monitoring MOS transistor in OSLSI and the like.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible.

For example, as the material of the gate electrode 4 described above, that is, the material of the dummy layers 7 and 8, for example, in addition to the polycrystalline Si film doped with impurities, for example, It is also possible to use a polycide film in which a refractory metal silicide film such as a tungsten silicide film is stacked.

Further, the MO for characteristic monitoring of the above-described embodiment is used.
The S transistor is an n-channel type.
The same can be applied to the case where the characteristic monitoring MOS transistor is a p-channel type.

[0026]

As described above, according to the present invention, a semiconductor device of the present invention, a dummy layer made of the same material as the gate electrode extends on the semiconductor substrate along the gate electrode, the gate
The distance between the electrode and the dummy layer is equal to M of the semiconductor integrated circuit itself.
Almost the same as the distance between the gate electrodes of IS transistors
Since the wirings are respectively connected to the source region and the drain region via the dummy layer on the source region and the drain region, the characteristics are measured by using this semiconductor device as a characteristic monitoring MIS transistor. In addition, the characteristics of the MIS transistor of the semiconductor integrated circuit itself can be accurately monitored.

[Brief description of the drawings]

FIG. 1 is an MO for characteristic monitoring according to an embodiment of the present invention.
FIG. 3 is a plan view showing an S transistor.

FIG. 2 is a sectional view taken along line 2-2 of FIG.

FIG. 3 is a plan view showing an example of a conventional MOS transistor for monitoring characteristics.

FIG. 4 is a sectional view taken along line 4-4 in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Gate insulating film 4 Gate electrode 5 Source region 6 Drain region 7 Dummy layer 8 Dummy layer 11 Wiring 12 Wiring

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/66 H01L 29/78

Claims (5)

(57) [Claims] 1. A semiconductor device in which a gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween and a source region and a drain region are formed in the semiconductor substrate, wherein the same material as the gate electrode is used. A dummy layer extending on the semiconductor substrate along the gate electrode, and the distance between the gate electrode and the dummy layer is
The distance between the gate electrodes of the MIS transistors of the integrated circuit itself and
A semiconductor device, wherein the wirings are set to be substantially the same, and wirings are respectively connected to the source region and the drain region via the dummy layer on the source region and the drain region. 2. The method according to claim 1, further comprising: a step between the gate electrode and the dummy layer.
The interval is the gate of the MIS transistor of the semiconductor integrated circuit itself.
When the distance between the electrodes is
2. The method according to claim 1, wherein the two are set to be the same.
Semiconductor device. Wherein between the gate electrode and the dummy layer
The interval is the MIS transistor of the peripheral circuit of the semiconductor integrated circuit.
That the distance between the gate electrodes
The semiconductor device according to claim 1, wherein: Wherein between the gate electrode and the dummy layer
The interval is the MIS transistor of the peripheral circuit of the semiconductor integrated circuit.
The most when there are multiple gate electrode intervals
Claims characterized by being set substantially the same as
2. The semiconductor device according to 1. 5. The width of said dummy layer is equal to the width of said gate electrode.
2. The semiconductor device according to claim 1, wherein the semiconductor device is substantially identical to the semiconductor device.
Body device.