JP2701828B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention, miniaturization can be half
A semiconductor device having a connection portion between a conductive substrate and a wiring layer , and
The present invention relates to the manufacturing method. 2. Description of the Related Art FIGS. 6 and 7 are explanatory views of a structure and a connection portion of a conventional MOS type semiconductor device, and FIGS. 8A to 8C are explanatory views of a manufacturing process of a semiconductor having an LDD structure. e). In the figure, 1 is a Si substrate, 2 is a diffusion layer,
2a is a region of low concentration diffusion layer, 2b are areas of high concentration of the diffusion layer, 3 is a gate electrode, 4 denotes a gate insulating film, the interlayer insulating film 5, the side walls 6, the first layer wiring layer 7 , 8
Denotes a second wiring layer, and 9 denotes a connection part (contact part). In general, an LDD structure is, as shown in FIG.
The diffusion layer 2 has a low concentration region 2a and a high concentration region 2b.
Since the concentration of the region 2a is low, the diffusion does not spread to a region where a channel is to be formed, that is, below the gate insulating film 4, and a channel length can be secured. In the LDD structure, the electric field generated in the vicinity of the drain is relaxed because the resistance of this region is higher than that of the region 2b by the region 2a, and carriers are injected and captured in the gate insulating film 4 near the drain by the electric field. This suppresses deterioration of the characteristics of an insulated field effect transistor (hereinafter, referred to as a MISFET) such as a threshold, which is caused by the phenomenon, that is, a so-called hot carrier phenomenon. [0008] A semiconductor manufacturing process having an LDD structure will be described below with reference to FIGS. 8 (a) to 8 (e). First, as shown in FIG. 8A, a gate electrode 3 is formed on a gate insulating film 4 by a conventional method.
8B, a low concentration diffusion region 2a is formed, and further, as shown in FIG. 8C, an interlayer insulating film 6a for forming a sidewall is formed, and then, FIG. As shown in FIG. 8D, the side wall 6 is formed, and finally, as shown in FIG. 8E, a high concentration diffusion region 2b is formed. By employing the LDD structure as described above, the breakdown voltage is improved, and the variation in the threshold value by the bias stress test is reduced by about two orders of magnitude as compared with the element having the normal structure, thereby realizing a highly reliable transistor. JP-A-51-68776 discloses a field effect transistor (hereinafter referred to as M) having a source region and a drain region of opposite conductivity type formed on a semiconductor substrate of one conductivity type.
A field effect transistor in which the drain region includes a central portion having a high surface impurity concentration and a low impurity concentration portion surrounding the central portion. This adopts a double drain structure in order to alleviate an electric field generated in the vicinity of the drain region and to prevent fluctuation of threshold voltage due to hot carriers. [0010] Further, JP-A-60-194568 discloses that
In an IC provided with an MlsFET, different impurities of the same conductivity type are used for the purpose of securing a sufficient effective channel length of the MISFET, preventing a short channel effect, improving the integration degree of the IC, and shortening the operation time. By introducing respective impurities for forming a drain region or a source region composed of two semiconductor regions having a high concentration into a semiconductor substrate through a gate electrode and sidewalls provided on both sides thereof, a channel is formed. Discloses that the squeeze into a source region or a drain region into a region in which is to be formed can be suppressed and an effective channel length can be sufficiently ensured. Japanese Patent Application Laid-Open No. 61-20369 discloses LDD.
Are disclosed. That is, in this method, a step of forming a gate electrode on a semiconductor substrate surrounded by an element isolation region via a gate insulating film, and introducing an impurity into the substrate by using the gate electrode as a mask to form a second conductive layer. Forming a first impurity layer of a mold, depositing an insulating film over the entire surface, removing the insulating film by reactive etching and leaving the insulating film on the side surface of the gate electrode and in the vicinity thereof, and forming a gate on the substrate. A step of forming a second impurity layer of the second conductivity type by introducing impurities using the electrode and the remaining insulating film as a mask, forming source and drain regions, and a mask having a selective etching property with respect to the insulating film over the entire surface After forming the material layer, selectively removing the mask material layer until a part of the remaining insulating film on the side surface of the gate electrode is exposed; and using the remaining mask material layer to remove the remaining insulating material. And forming a gap between the gate electrode and the gate electrode, and introducing an impurity into the substrate from the gap to form a third impurity layer of the first conductivity type. A method for manufacturing a semiconductor device, comprising: According to this method, a third impurity layer of a first conductivity type (for example, a P ⁻ -type layer) for suppressing the extension of a depletion layer due to a drain voltage is provided by a semiconductor of a first conductivity type near a side wall of a gate electrode. By partially forming only the substrate, the contact portion of the P ⁻ -type layer with the source and drain regions is reduced as compared with the related art. [0014] The conventional MO as described above
Problems with the S-type semiconductor device include the following. (1) As shown in FIG. 7, a connecting portion 9 between two layers
In the prior art, a hole-shaped opening was formed. However, a combination a of photolithography was required so that the opening 9 and the metal of the first wiring layer 7 were not short-circuited. This has been a bottleneck in high integration because the margin a cannot be simply reduced because it is determined by the capability of the exposure apparatus. (2) For the same reason as in the preceding paragraph, the length of the second wiring layer 8 cannot be reduced due to the combination allowance a, and the speed cannot be increased due to the propagation delay due to the resistance. (3) For the same reason as in the above item (1), the parasitic diffusion capacitance is not reduced due to the combination allowance a, and the speed cannot be increased. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same which solve the above problems. According to the present invention, there is provided a semiconductor device comprising:
Installed above the semiconductor substrate via a gate insulating film,
A gate electrode having a first insulating film;
An impurity layer provided in the adjacent semiconductor substrate;
A gate electrode and a second insulating layer provided on a side wall of the first insulating film.
An edge film, and installed so as to cover the first and second insulating films.
And a part of the first insulating film from the impurity layer
Insulation with contact holes with opening widths up to
Contacting the film with the impurity layer in the contact hole
In the contact hole.
The thickness of the first insulating film is such that the first insulating film is covered with the third insulating film.
The first insulating film is thinner than the first insulating film.
You. Further, a space between the gate electrode and the wiring layer is provided.
The thickness of the first and second insulating films is 5 at the thinnest part.
It is characterized by being not less than 00 °. The method of manufacturing a semiconductor device according to the present invention
Gate electrode formed above the substrate with a gate insulating film interposed
And the semiconductor using at least the gate electrode as a mask.
MIS type semiconductor device having an impurity layer formed in a body substrate.
A method of manufacturing a conductor device , comprising:
Forming an insulating film, the gate electrode and the first insulating film;
Forming the second insulating film on the side wall with the film, at least before
Above the impurity layer, above the first insulating film, and above the second insulating film
Forming a third insulating film on the third insulating film;
Opening from the impurity layer to a part of the gate electrode
In order to form a contact hole having a width,
3 part of the insulating film, part of the first insulating film, and part of the second
Etching a part of the insulating film;
Forming a wiring layer in the contact hole;
Contacting the wiring layer.
You. Further , in the etching step,
The first and second insulation between a gate electrode and the wiring layer
The thickness of the rim should be 500 mm or more at the thinnest part
Is characterized by being etched. In the conventional method, the interval between the first-layer polysilicon wirings is 1 + 2a as shown in FIG. Here, l: the size of the opening between the polysilicons, a: the alignment margin However, in the method of the present invention, it is not necessary to have the alignment margin, and the minimum wiring interval which is limited by processing as shown in FIG. For example, the line width and interval of the first-layer polysilicon are 1.2 μm and 1.2 μm, respectively, and the alignment margin a is 1.
Assuming that 0 μm and l are 1.2 μm, the conventional method: l + 2a = (1.2 + 1.0 × 2) μm = 3.2 μm The method of the present invention: 1.2 μm Becomes Since the semiconductor device of the present invention is configured as described above, the chip area can be reduced, and the diffusion area of the source or drain diffusion layer is reduced accordingly, and the parasitic capacitance is reduced. Similarly, the wiring length of the second-layer polysilicon is shortened by this amount, the wiring resistance is reduced, the propagation delay can be reduced, and the speed and cost can be reduced. In the semiconductor device of the present invention, when the gate electrode is made of polysilicon, a refractory metal or a combination of two layers of polycide, dielectric breakdown easily occurs due to the unevenness of the surface. Become. Therefore, the above 2
By setting the thickness of the insulating film between the layers to 500 ° or more at the thinnest portion, dielectric breakdown can be prevented. Next, an embodiment of the present invention will be described. (Embodiment 1) An embodiment of a semiconductor device according to the present invention will be described with reference to an example in which the present invention is applied to an IC having an N-channel MISFET. FIG. 1 and FIG. 2 are explanatory views of a semiconductor device of the present invention and a connection portion thereof, respectively. In the drawings, the same reference numerals as those in FIGS. 6 to 8 denote the same or corresponding parts, and a description thereof will not be repeated. In the figure, reference numeral 10 denotes an interlayer insulating film, and 11 denotes a side wall insulating film. [0032] In FIG. 1, 1 P consists same silicon single crystal as 6 ^- -type semiconductor substrate or N ^- P formed on a semiconductor substrate ^- an area constitutes a lC. 2 is a diffusion layer, 2a is a low concentration diffusion layer, 2b
Is a high concentration diffusion layer, 3 is an insulating film 4 (gate insulating
A first-layer wiring layer provided on a predetermined upper surface portion of the film 1 and mainly used as a gate electrode; 4, an insulating film provided on the substrate 1 mainly used as a gate insulating film; Is an interlayer insulating film (first insulating film) provided so as to cover the semiconductor element, and mainly electrically isolates the semiconductor element from the second wiring layer provided thereon. Reference numeral 6 denotes an insulating sidewall (second insulating film) mainly provided on the gate insulating film 4 at both ends of the gate electrode portion 3 of the first wiring layer by anisotropic etching. In order to further isolate the pair of semiconductor regions used as the source region and to secure a sufficient effective channel length, the semiconductor device is formed by the low concentration diffusion layer 2a formed at this time. Reference numeral 11 denotes an insulating film (second insulating film) on the side wall of the gate electrode 3 in the opening for making contact between the first wiring layer 7 and the second wiring layer 8. Is a sidewall insulating film formed by anisotropic etching on the upper surface of the substrate. The sidewall insulating film is firstly formed by sidewalls having an LDD structure, and secondly, by forming an interlayer insulating film 10 (third insulating film) by anisotropic etching. A sidewall insulating film formed by the same mechanism as the sidewall when forming the opening (9 in FIG. 2); thirdly, a sidewall insulating film formed by the combination of the first and second sidewalls. These differences are in the interlayer insulating film 1
At 0, the film thickness and over-etching time when the film is etched will be described. In other words, if the re-over etching time is long, the interlayer insulating film 10 is entirely etched even on the side surfaces of the gate electrode, and the side wall insulating film 6 becomes only the side wall of the LDD. Conversely, if the etching amount is reduced, the third state is attained. The second state is a state when the image is created in the process described in the third embodiment described later. As shown in FIG. 1, the semiconductor device of the present invention has the following features. (1) The second wiring layer 8 is self-aligned by the side wall or side wall insulating film 6 at the tangent portion with the diffusion layer 2 on the substrate. It is electrically separated from the first wiring layer 7 (gate electrode 3). (2) The opening 9 is larger than the boundary between the Si surface of the source or drain diffusion layer and the side wall or the side wall insulating film 6 and has no allowance. (3) First and second wiring layers 7 and 8
Are separated by an insulating film 5 in addition to the conventional interlayer insulating film 10. This is different from the conventional apparatus. (Embodiment 2) Next, FIGS. 3 (a) to 3 (l)
An embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In FIG. 12, reference numeral 12 denotes a photoresist pattern. The method of manufacturing a semiconductor device according to the present invention comprises the following steps: (1) First, as shown in FIG. 3A, a gate insulating film 4 is formed on the surface of a p-type semiconductor substrate 1, and then an oxide polycrystalline silicon is formed. A gate electrode layer (first wiring layer 7) of a layer, a refractory metal layer, or a polycide layer composed of a combination of the two is formed. (2) Next, as shown in FIG. 3B, an insulating film 5 is formed on the gate electrode layer 7 by CVD. (In this case, or by oxidation heat treatment of the gate electrode 7 layer, etc.) (3) As shown in FIG. 3C, a photoresist pattern 12 is formed on the insulating film 5. (4) As shown in FIG. 3D, the insulating film 5 is removed by reactive etching (RIE). Next, as shown in FIG. 3E, the gate electrode 3 is similarly formed by reactive etching, and the photoresist pattern 12 is removed. (5) As shown in FIG. 3F, an n ^~ layer (a low concentration diffusion layer 2a) is formed in the substrate 1 by ion implantation of ³¹ P ^{+ using} the gate electrode 3 as a mask. (6) As shown in FIG. 3G, an interlayer insulating film 6a is formed on the entire surface of the gate electrode 3 by CVD. (7) As shown in FIG. 3H, the entire surface is removed by reactive etching to form a sidewall 6 on the side wall of the gate electrode 3. (8) Next, as shown in FIG. 3I, an n ⁺ layer (dense diffusion layer 2b) is formed on the substrate 1 by ion implantation of ³¹ P ⁺ or As. (9) As shown in FIG. 3J, an interlayer insulating film 10 is formed by CVD. (10) As shown in FIG. 3 (k), the interlayer insulating film 5 and a part of the side wall 6 under a predetermined portion of the interlayer insulating film 10 are removed by etching, and the side wall 11 and the opening of the connection part are removed. 9 is formed. At this time, by optimizing the amount of over-etching when forming the interlayer insulating film 5 and the sidewalls 6 and the etching condition of the interlayer insulating film 10 and the opening 9 of the connection portion, the first wiring layer 7 By adjusting the thickness of the insulating film 5 or 11 between the second wiring layers 8 to at least 500 ° or more, leakage between them is prevented, and the withstand voltage is ensured. (11) Finally, as shown in FIG.
Hereinafter, a second-layer wiring metal layer 8 is formed by a conventional method. By performing the above 12 steps, the structure of the semiconductor device of the present invention was realized. (Embodiment 3) On the other hand, FIGS. 4 (a) to 4 (c)
The following describes another method. (1) First, as shown in FIG. 4A, after a gate insulating film is formed on the surface of a p-type semiconductor substrate, a polysilicon layer, a refractory metal layer, or a polycide layer composed of a combination of the two is used. A gate electrode layer is formed on a gate film on a semiconductor substrate. (2) Next, as shown in FIG. 4B, an n ^- layer (a low-concentration diffusion layer 2a) is formed in the substrate 1 by ion implantation of ³¹ P ^{+ using} the gate electrode layer 3 as a mask. (3) As shown in FIG. 4C, the periphery of the gate electrode 3 is considerably larger than that of the Si substrate 1 by performing the oxidation treatment in a humid atmosphere at a temperature of 950 ° C. or less (5 to 10 depending on the temperature condition). (A film about twice as large) 6a can be formed. (4) Hereinafter, the manufacturing process (6) of the second embodiment.
The following seven steps {FIG. 3 (f) and below} are performed. The structure of the semiconductor device of the present invention can be realized by the present method including the above 10 steps. (Embodiment 4) FIGS. 5 (a) to 5 (d)
Another method will be described. (1) As shown in FIG.
After a gate insulating film is formed on the surface of the semiconductor substrate, a gate electrode layer of a polysilicon layer or a refractory metal layer or a polycide layer composed of a combination of the two is formed. Then, using the gate electrode 3 as a mask, an n ⁻ layer (low diffusion layer 2a) is formed on the substrate 1 by implanting ³¹ P ⁺ ions. (2) As shown in FIG.
An oxidation heat treatment is performed in a humid atmosphere at a temperature of 50 ° C. or less. At this time, many insulating films 5 can be formed only on the gate electrode 3 for the reason of the third embodiment. [0064] (3) As shown in FIG. 5 (c), the substrate 1 ³¹
An n ⁺ layer (dense diffusion layer 2b) is formed by ion implantation of P ⁺ or As. (4) Hereinafter, the manufacturing process (9) of the second embodiment.
The following four steps (FIG. 3 (j) and below) are performed. The structure of the semiconductor device of the present invention was realized by the present method including the above seven steps. The method of manufacturing a semiconductor device according to the present invention includes the following steps: (1) Before forming the sidewalls 6 of the second and third embodiments or after forming the sidewalls 6 of the fourth embodiment, at least before forming the interlayer insulating film 10; An insulating film 5 having a predetermined thickness is formed on the first-layer wiring. (2) In the second and third embodiments, when the sidewall 6 is formed and when the interlayer insulating film 10 is etched, in the fourth embodiment, when the interlayer insulating film 10 is etched, Etching is performed so that the insulating film 5 on the first-layer wiring remains, and finally, 500 ° or more is left. This is different from the conventional method in the points described above. Although the embodiments of the present invention have been described with reference to an n-channel transistor formed on a p-type substrate, it is needless to say that the present invention can be applied to an n-channel transistor formed on an n-type substrate. The semiconductor device of the present invention and the fabrication of the semiconductor device
According to the fabrication method, (1) the alignment margin can be eliminated, so that the space between the first-layer wirings is reduced, and high density can be realized. (2) Since the wiring length of the second layer can be reduced, the wiring resistance can be reduced and the wiring delay can be reduced. (3) Since the area of the diffusion layer was reduced, the capacitance of the diffusion layer was reduced, and the parasitic capacitance of the second-layer wiring was reduced, thereby realizing high-speed operation. (4) The overall chip area was reduced, the number of effective chips in the same wafer was increased, and the cost was reduced. (5) For forming contact holes
In an etching process, a first insulating film and a second insulating film
(Side wall) may be over-etched
Simple precise etching end point
A semiconductor device can be manufactured by the process. Further
The first insulating film may be over-etched.
Combined with the effect of
Increases the contact area between the impurity layer and the wiring layer.
be able to. Also, a part of the first insulating film and the second insulating film
(Sidewall)
The gate electrode and the wiring layer are formed by the first and second insulating films.
At least 500 ° apart, ensuring sufficient withstand voltage
it can.

BRIEF DESCRIPTION OF THE DRAWINGS illustration of a semiconductor equipment of the present invention; FIG. FIG. 2 is an explanatory view of the connecting portion of the semiconductor equipment of the present invention. FIGS. 3 (a) to (l) are process explanatory views of a manufacturing method in Examples 2, 3, and 4 of the present invention. FIGS. 4A to 4C are process explanatory diagrams of a manufacturing method in Examples 2, 3, and 4 of the present invention. 5 (a) to 5 (c) are process explanatory views of the manufacturing method in Examples 2, 3, and 4 of the present invention. FIG. 6 is an explanatory view of a structure of a conventional semiconductor device and an explanatory view of a connection portion thereof. FIG. 7 is an explanatory view of a structure of a conventional semiconductor device and an explanatory view of a connection portion thereof. 8 (a) to 8 (e) are explanatory views of a manufacturing process of an LDD structure semiconductor. [Description of Signs] 1 ... Si substrate 2 ... Diffusion layer 2a ... Diffusion layer 2b with low concentration ... Dense diffusion layer 3.7 ... Gate electrode (first layer wiring layer) 4 ... Gate insulation Film 5.10 interlayer insulating film 6 sidewall 6a insulating film 8 for forming sidewall 8 second wiring layer 9 connection part (contact part) 11 sidewall The insulating film 12 is a photoresist pattern. In the drawings, the same symbols indicate the same or corresponding parts.

Claims (1)

(57) [Claims] Installed above the semiconductor substrate via a gate insulating film,
A gate electrode having a first insulating film thereon; an impurity layer provided in the semiconductor substrate adjacent to the gate electrode; a second electrode provided on a side wall of the gate electrode and the first insulating film.
An insulating film, a third insulating film provided so as to cover the first and second insulating films, and having a contact hole having an opening width from the impurity layer to a portion on the first insulating film. And a wiring layer in contact with the impurity layer in the contact hole, wherein the thickness of the first insulating film in the contact hole is equal to the thickness of the first insulating film covered by the third insulating film. A semiconductor device having a thickness smaller than a thickness of an insulating film. 2. 2. The semiconductor device according to claim 1, wherein the thickness of the first and second insulating films between the gate electrode and the wiring layer is 500 [deg.] Or more at a thinnest portion. 3. A method for manufacturing a MIS type semiconductor device, comprising: a gate electrode formed above a semiconductor substrate via a gate insulating film; and an impurity layer formed in the semiconductor substrate using at least the gate electrode as a mask. Forming a first insulating film on a gate electrode; forming a second insulating film on sidewalls of the gate electrode and the first insulating film; at least above the impurity layer, on the first insulating film, and (2) forming a third insulating film on the insulating film; forming a contact hole having an opening width from the impurity layer to a portion on the gate electrode in the third insulating film; (3) a step of etching a part of the insulating film, a part of the first insulating film, and a part of the second insulating film; forming a wiring layer at least in the contact hole;
Contacting the impurity layer and the wiring layer. 4. In the etching step, the thickness of the first and second insulating films between the gate electrode and the wiring layer is:
4. The method according to claim 3, wherein the thinnest portion is etched so as to have a thickness of 500 [deg.] Or more.