JPS61207057A - Manufacture of semiconductor integrated device - Google Patents

Abstract

PURPOSE:To micro-miniaturize the peripheral parts of the contact hole and to obtain a manufacturing method to contribute to the micro-miniaturization of a semiconductor integrated device by a method wherein the forming method of the contact hole based on a specially novel idea is adopted. CONSTITUTION:A first insulating film 2 is provided on a P-type silicon substrate 20, and moreover, a first conductive film 22 and a second insulating film 23, and furthermore, a buffer film 24 are stacked, resist patterns 25 are formed, the resist patterns 25 are removed by performing an anisoptropic etching using an RIE technique and patterns 26, which are polymeric films, are formed. Then, N-type dopant is buried in using the patterns 26 as masks, an insulator film of the same kind as the second insulator film 23 is annexed on the whole surface as shown by broken lines 28 and an etching is performed on the insulator film using an RIE technique. As a result, a third insulating film 29 can be annexed on each side surface of the polymeric films, patterns 26. Then, the buffer film 24 is removed by performing an etching, an interlayer insulating film 30 is formed, resist patterns 31 are formed on the interlayer insulating film 30, the interlayer insulating film 30 is selectively removed by performing an etching, and moreover, the interlayer insulating film between the pattern elements and part of the first insulating film 21 are removed by performing an etching.

Description

[Detailed Description of the Invention] Field of Industrial Application The present invention relates to a method for manufacturing highly integrated semiconductor integrated devices, and in particular to a method for forming contact holes.
- have.

- Conventional Technology Semiconductor Integrated Devices and Partitions In memory such as dynamic RAM, there is a marked trend toward high pit performance.Recently, prototypes of 1-megabit DRAMs and announcements of 1-megabit DRAMs have been made one after another. For example, the IEDM held in December 1984
In the digest of 84, Kunio Nakamu
ra ez al (Q Paper r Buried Capacitor (BIO) for Megabit MOS Dynamic RAM SEA/
J (@ Buriea l5Olation 0a
paoit, or (bIo) Cell for Meg
abit; :MOS D7namia RAM”)
is introduced and told. Figure S is the iFLg of this paper,
This is a partial cutout of the typical layout pattern of the BICt cell array shown in Figure 1. In the figure, (1) (21 is two adjacent word lines, (3) is one pin), (4) is an element isolation pattern, and (5) is a contact hole. In this case, bit line (3) and word line (1) (2) connected to the active layer of the semiconductor substrate.
To avoid electrical connection with +, contact hole (
5) and the word line (1) (21).
61(7) t- is provided. Since the width (8) of the word line and the entire center (9) of the contact hole (5) require a predetermined size determined by the design rules, the pitch of the word line (101) is There was a limit to further miniaturization of the memory cell.In this way, there was a limit to further miniaturization of the memory cell because the current manufacturing level has reached the cutting edge with the above-mentioned space (6) ()). There is.

(c) Problems to be Solved by the Invention The present invention has been made to solve the above problems, and in particular, employs a contact hole forming method based on a new concept to miniaturize the area around the contact hole. The present invention aims to provide a manufacturing method that contributes to miniaturization of semiconductor integrated devices.

B) Means for Solving the Problems The present invention provides a contact hole for connecting an external wiring to an active layer provided in a semiconductor substrate.

Two adjacent 18th! This method is characterized in that an insulating film is provided on each of the opposing surfaces of the film and is used as a mask. a step of sequentially attaching an IE1 conductive film having conductivity and a second insulating film made of a second insulating material different from the first insulating material; and polymerization of the fourteenth insulating film and the second insulating film. selectively removing a film to form a pattern of the polymerized film; forming the pattern in the semiconductor substrate between two adjacent pattern elements forming the second step; a step of attaching a third insulating film made of the second insulating material on at least the first conductive film on opposing sides of two pattern elements, and then attaching an interlayer insulating film over the pattern and the third insulating film; A contact hole t- and a contact hole t- reaching the active layer are formed in the interlayer insulating film and the first insulating film.
manufacturing a semiconductor integrated device comprising the steps of: opening a pattern element and the third insulating film attached thereto as a mask; and attaching a second conductive film on the interlayer insulating film and in the contact hole. It's a method.

(e) Function In the present invention, an insulating film is provided on the outside of two adjacent first conductive films, and a contact hole is opened using this as a mask. If the width is wider than the gap between the films, a part of the contact hole can be left so as to overlap the first conductive film, and the contact hole can be connected to the active layer inside the semiconductor substrate through the hole. This prevents the second conductive film from being electrically connected to the equivalent conductive film, thereby ensuring prevention of short-circuit accidents.

f) Embodiment FIG. 1 is a plan view of the vicinity of a contact hole of a semiconductor integrated device constructed by the method of the present invention, and FIGS. I-■ in Figure 1
A cross section is shown.

In FIG. 1, the same components as those in the conventional example shown in FIG. 3 are given the same reference numerals to avoid redundant explanation.

The only substantial difference between the parts represented in the two figures is that the pitch (it) of the two word lines (1) (2+) is significantly smaller in that of Figure 1;
This is achieved by arranging the area occupied by the contact hole (5) so that a portion thereof overlaps the word line (1) (21).
This will be explained with reference to the process diagram of G. In this example, BrO
Although the description will be made with reference to a DRAM constituting a cell array, the technical idea of the present invention is not limited to this, but can also be applied to SRAM, random logic, or a floating diffusion portion for increasing the output of OOD.

A WL1 insulator (e.g. 8102) which becomes a gate insulating film is placed on a semiconductor substrate (P type) (a) made of silicon single crystal.
12 nt of the first insulating film made of the above-mentioned first insulating film Q1 are formed, and on this first insulating film, a first conductive film made of polysilicon having conductivity, which is the gate electrode material, is sequentially formed.
) A second insulator (for example, 31gN4) different from the film composition of
A second insulating film (c) made of 8102 and a buffer film Q4 made of υ are further stacked. Then, on this buffer film (goods), the first conductive film is applied! ! A resist pattern (c) is formed by a well-known method to selectively remove the polymer film and the second insulating film (Fig. 2g).
. Next, using this resist pattern (2) as a mask, the buffer film C24), the second insulating film (2), and the first conductive film @ are sequentially removed by anisotropic etching using RIE (reactive ion etching) technology to form the polymer film. form a pattern (to). Next, operation 6G to form a drain region (or source region) on the semiconductor substrate Ca! Using the above pattern as a mask, an N-type dopant is buried so as to form η (FIG. 2b). Next.

OV the same type of insulator (315N4) as the second insulator on the entire surface.
Attach it as shown by the broken line ■ using the D method, then RIB
The insulator is etched using the OVD method until the first insulating film Q1) and the buffer film are exposed. As a result, a third insulating film 1291 made of a second insulating material (ElisNa) can be attached to each side surface of the pattern elements (26A) and (26B) constituting the pattern (to) of the polymer film (Fig. 2). g). Next, buffer film c! 4 was removed by etching.

A second insulator is attached to the outside of the first conductive film constituting each pattern element (26A) (26B).
Figure 2 d). After that, a 1-layer insulating film OI made of Pa() or 8102 is formed on the semiconductor substrate having this pattern.
A resist pattern C311 is formed on this interlayer insulating film to open a contact hole (FIG. 2g). Next, using this resist pattern 611 as a mask, the interlayer insulating film (7) is selectively etched away, and using the pattern elements (26A) and (26B) as masks, the interlayer insulating film and the first insulating film between the pattern elements are removed. Remove by etching. At this time, since the contact hole Q is opened using the pattern elements (26A) (26B) as a mask, it is opened in alignment with the operation man formed using the pattern @ of the polymeric film (w
c2 figure). Finally, a second conductive film made of Al is formed by evaporating p and l over the entire surface and patterning it. This calculation 2 conductivity 1! ! :I33 is buried in the contact hole C4 and is electrically connected to the operation e127), but is not electrically connected to the first conductive film circle because the voltage is divided between the third insulating film and the first conductive film circle (see Fig. 2). g). In this embodiment, the contour of the area sandwiched by two pattern elements (26A) (26B).

Acthole r: Mainly shows the area around 37J, and operation a on the opposite side (the capacitor element connected to 2Bm is omitted from the illustration. Furthermore, in this embodiment, operation 1
In this example, the formation of @ is performed before the formation of the third insulating film, but in this process, low-concentration ion implantation is performed, and then the necessary high-concentration ion implantation is performed after the formation of the third insulating film. By doing so, the so-called LDD (Ligbt)
1y Dopel Dral, n) structure.

(G) Effects of the Invention Since the present invention is configured as described above, even if the line widths of two adjacent first conductive films (two word lines) are made to the same scale as that of the conventional example, two The distance between both outer sides of the word line is smaller than the conventional example.
can.

The area occupied by the cell can be miniaturized. Also.

Two adjacent pattern elements can also be usefully used as masks for forming an active layer within a semiconductor substrate and for opening contact holes in the active layer.

[Brief explanation of drawings]

The first factor is a plan view of the periphery of a hole in a semiconductor integrated device constructed by the method of the present invention, and FIGS. 2A to 2G are process explanatory diagrams of one embodiment of the method of the present invention. FIG. 3 is a partial plan view of a conventional device. Circle...semiconductor substrate, 12n...first insulating film,
...first conductive film, c! 3.-12 insulating film, (1)...
Polymer film pattern. (b)...Operation 11. (26A) (2,6B)...
Two pattern elements, wire...Third insulating film, (to)...
・Interlayer insulating film, 4...contact hole, (to)・
...Second conductive film.

Claims (1)

[Claims] (1) A first insulating film made of a first insulating material is provided on a semiconductor substrate, and a first electrically conductive film having conductivity and a second electrically conductive film different from the first insulating material are sequentially formed on the first insulating film. a step of attaching a second insulating film made of an insulating material; a step of selectively removing a polymer film of the first conductive film and the second insulating film to form a pattern of the polymer film; and forming the pattern. forming an active layer in the semiconductor substrate between two adjacent pattern elements; a step of attaching a third insulating film, then a step of attaching an interlayer insulating film from above the pattern and the third insulating film, and forming a contact hole reaching the active layer in the interlayer insulating film and the first insulating film. A semiconductor integrated device comprising: a step of opening the two pattern elements and the third insulating film attached thereto as a mask; and a step of attaching a second conductive film on the interlayer insulating film and in the contact hole. manufacturing method.