JP3203776B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a capacitor having a small cell area and a large storage capacitance.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become finer and larger in capacity, for example, a typical semiconductor LSI memory such as DR
In the AM, as the cell area is reduced, it becomes difficult to secure the area of the capacitor storage node, and it is difficult to form a capacitor having a desired capacitance on a semiconductor substrate. Recently, DRAM memory cells in which a storage node for a capacitor is formed in a ring shape have been developed (1).
989 VLSI Symposium 69-70).
As described above, by forming the storage node for the capacitor in a ring shape, the area of the storage node constituting the capacitor can be increased, and a capacitor having a small cell area and a large storage capacity can be formed on the semiconductor substrate.

[0003]

However, when such a semiconductor device is manufactured by a conventional manufacturing method, additional CVD and RIE are required as compared with a case where the storage node for the capacitor is not formed in a ring shape. There is a problem that the number of steps for manufacturing a semiconductor device increases. Therefore, the manufacturing cost has increased, and it has been difficult to manufacture a highly integrated and inexpensive semiconductor device. The present invention has been made in view of such a problem of the related art, and an object of the present invention is to form a fine ring-shaped storage node without causing a significant increase in the number of processes as compared with the conventional process. It is another object of the present invention to provide a method of manufacturing a semiconductor device which can manufacture a semiconductor device having a large-capacity capacitor at low cost.

[0004]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention comprises the steps of:
An interlayer insulating layer is stacked, a conductive layer serving as a storage node for a capacitor is stacked on the surface of the interlayer insulating layer, a dummy layer is stacked on the surface of the conductive layer, and the transmitted light phase of a predetermined pattern is formed. By exposure using a shifter-equipped exposure reticle having an inversion portion, processed into a ring-shaped pattern having a pattern corresponding to a boundary portion between the transmitted light phase inversion portion and the other portion, the ring-shaped dummy layer Conductive sidewalls are formed on the inner circumference and the outer circumference, the dummy layer is removed by etching, and a double-ring capacitor storage node is formed.

[0005]

In the method of manufacturing a semiconductor device according to the present invention, since the exposure is performed using the above-described exposure reticle with a shifter, the phase of the exposure light that has passed through the transmitted light phase inversion portion is different from the exposure light that has passed through the other portions. Since the phase is inverted with respect to the phase of light, light interference occurs at these boundaries and cancel each other out, and only the boundary is shielded. As a result, a fine pattern corresponding to the boundary portion can be transferred to a resist or the like, and a fine pattern accumulation node can be formed using this fine pattern. The line width of the fine pattern can be adjusted by changing the exposure amount of the stepper. For example, even with a line stepper, a line width of about 0.15 μm, which exceeds the normal resolution limit, can be processed.

By using such a method, a ring-shaped storage node can be easily obtained without incurring a large increase in the number of steps as compared with the conventional steps, and the area of the storage node constituting a capacitor is increased. be able to. Therefore, an increase in manufacturing cost can be prevented, and a highly integrated and inexpensive semiconductor device can be manufactured.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, in this embodiment, first, an inter-element isolation region 5 is formed in a predetermined pattern on the surface of a semiconductor substrate 4 made of single crystal silicon or the like by a LOCOS method or the like. A gate oxide film 18 is formed on the surface of the semiconductor substrate 4 between 5 by a thermal oxidation method or the like. Thereafter, word lines 7a and 7b serving as gate electrodes are formed in a predetermined pattern on gate oxide film 9. The word lines 7a and 7b are made of, for example, a polysilicon film formed by a CVD method, and are doped with an impurity such as phosphorus to increase conductivity.

An interlayer insulating layer 8 is stacked on the word lines 7a and 7b. The interlayer insulating layer 8 is composed of, for example, a silicon oxide film formed by a CVD method. A bit line contact hole is formed in the interlayer insulating layer 8, and a bit line 6 is formed in a predetermined pattern on the interlayer insulating layer 8 so as to enter the contact hole.

As shown in FIG. 2, an interlayer insulating layer 11 is formed on the surface of the bit line 6. The interlayer insulating layer 11 is formed of, for example, a silicon oxide film formed by a CVD method. The surface of the interlayer insulating layer 11 is flattened. Contact holes 10 facing the surface of semiconductor substrate 4 are formed in interlayer insulating layers 11 and 8.

Next, as shown in FIG. 3, a conductive layer 12 for forming a storage node is laminated so as to enter the contact hole 10. The conductive layer 12 is, for example, CV
It is composed of a polysilicon film formed by the method D. The thickness of the polysilicon film is not particularly limited, but is, for example, about 600 nm. The polysilicon film that has entered contact hole 10 becomes conductive plug 12b. A resist film 14 is formed on the surface of the conductive layer 12,
This is processed into a processing pattern of the storage node.

In this embodiment, an exposing reticle 40 with a shifter as shown in FIG. This exposure reticle 40 includes:
The transmitted light phase inversion portion 42 is formed in a predetermined pattern. The transmitted light phase inversion portion 42 can be formed by changing the thickness of the transparent plate constituting the exposure reticle 40 as compared with other portions. For example, in a pattern corresponding to the transmitted light phase inversion portion 42, a portion having a larger thickness may be formed by other portions.

By using such a reticle 40,
As shown in FIG. 6B, the resist film 14 can be patterned in a ring shape with a fine pattern corresponding to the boundary between the transmitted light phase inversion portion 42 and another portion. The pattern width of the fine pattern can be adjusted by changing the exposure amount. For example, even with an i-line stepper, a line width of about 0.15 μm, which exceeds the normal resolution limit, can be processed.

The fact that such a fine pattern can be formed can be explained as follows. That is, if the exposure reticle 40 with a shifter is used, the exposure light passing through the transmitted light phase inversion portion is inverted with respect to the phase of the light passing through the other portions. This is because light interference causes a portion to be a shadow of light.
This shadow corresponds to a fine pattern.

Next, as shown in FIG. 4, the conductive layer 12 is patterned using an etching means such as RIE using the predetermined pattern 14 to obtain a fine ring-shaped storage node 12a. In FIG. 4, the storage node 12a does not appear to be connected to the conductive plug 12b. However, as shown in FIG. 7, one side of the storage node 12a having a square ring shape is actually connected to the conductive plug 12b. To each other. That is, the storage node 12a in the form of a square ring has a conductive plug 12b on each side.
They are arranged in a matrix in such a pattern as to be connected above.

Next, as shown in FIG. 5, by laminating the capacitor insulating thin film layer 15 and then laminating the capacitor cell plate layer 16 by the CVD method or the like, the DRAM memory cell 2 is obtained. The capacitor insulating thin film layer 15
The insulating film is not particularly limited as long as it is insulative. The capacitor cell plate layer 16 is not particularly limited as long as it has conductivity, and is made of, for example, polysilicon.

The DRAM memory cell 2 manufactured by the above process has a ring-shaped storage node 12a,
Since the inner and outer walls are used as capacitor surfaces, a large storage capacity can be obtained. Moreover, compared to the conventional process, only the reticle needs to be changed, so that the manufacturing steps and manufacturing costs hardly increase.

Hereinafter, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 8, in the same process as in the first embodiment,
After forming the word lines 7a and 7b and the bit line 6 on the semiconductor substrate 4, an interlayer insulating layer 11 'made of SiO ₂ or the like is formed on the surface of the bit line 6 by a CVD method or the like. Is flattened. Then, an etching stopper layer 22 which also functions as a second interlayer insulating layer is formed on the surface. The etching stopper layer 22 is formed of, for example, a silicon nitride film formed by a CVD method, and functions as an etching stopper for protecting a lower layer when a dummy layer 26 described later is etched. Etching stopper layer 22
A contact hole 10 facing the surface of the semiconductor substrate 4 is formed in the interlayer insulating layers 8 and 11 '. Next, a part of the storage node and a conductive layer 24 for forming a conductive plug are laminated on the surface of the etching stopper layer 22 so as to enter the contact hole 10. This conductive layer 24 is formed of, for example, a polysilicon film formed by a CVD method. The thickness is not particularly limited,
For example, it is about 100 nm.

Next, as shown in FIG. 9, a dummy layer 26 is laminated on the surface of the conductive layer 24. The dummy layer 26 is made of a material having an etching rate different from that of the etching stopper layer 24, and is made of, for example, a silicon oxide film formed by a CVD method. The thickness is not particularly limited, but is, for example, 600 nm.

In this embodiment, the dummy layer 26 is finely processed into a ring-shaped fine pattern by the exposure reticle 40 as shown in FIG. This fine pattern becomes a dummy pattern of the storage node.

Next, in this embodiment, as shown in FIG. 10, a conductive layer for forming a double ring-shaped storage node is laminated on the dummy layer 26 having a predetermined pattern. This conductive layer is formed of, for example, a polysilicon film formed by a CVD method, and its thickness is not particularly limited, but is, for example, about 100 nm. This polysilicon film is made of RI
Etch back by anisotropic etching such as E.
As a result, the side wall 2
8 are formed. At the same time, the lower conductive layer 24 is also etched, so that the sidewalls 28 and the dummy layers 26 are formed.
Storage node bottom wall portion 24 in a predetermined pattern only immediately below
b is formed. Although the storage node bottom wall portion 24b and the conductive plug 24a appear to be cut off in FIG. 10, they are actually connected as viewed from the plane side, as in the above-described embodiment. I have.

Next, the dummy layer 2 is formed by hydrofluoric acid treatment or the like.
By removing 6, as shown in FIG. 11, it is possible to form a double ring-shaped storage node 30 composed of the sidewalls 28, 28 and the storage node bottom wall portion 24 b. Thereafter, as in the above-described embodiment, by laminating the capacitor insulating thin film layer and the capacitor cell plate layer, D
The RAM memory cell 20 is obtained.

In this embodiment, the storage node is formed in a double ring shape, and the inner circumference and the outer circumference form a capacitor. Therefore, the storage capacity can be further increased as compared with the first embodiment. Becomes Therefore, the future 256MD
It is possible to cope with miniaturization when forming a RAM or the like and a reduction in voltage such as 1.5 V.

The present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the present invention. For example, the method of manufacturing a semiconductor device according to the present invention is not used only for a DRAM,
The present invention can be used for a method of manufacturing another semiconductor device having a storage node, such as an ASIC device having an AM.

[0024]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a ring-shaped storage node can be easily obtained without incurring a large increase in the number of steps as compared with the conventional steps. , The area of the capacitor of the storage node can be increased. Therefore, an increase in manufacturing cost can be prevented, and a highly integrated and inexpensive semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method for manufacturing a DRAM according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

FIG. 3 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

FIG. 4 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

FIG. 5 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

FIG. 6 is a plan view of an exposure reticle used in the embodiment and a fine pattern diagram obtained by using the reticle.

FIG. 7 is a plan view showing a pattern of a storage node obtained by the manufacturing method of the embodiment.

FIG. 8 is a schematic sectional view showing a method for manufacturing a DRAM according to a second embodiment of the present invention.

FIG. 9 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

FIG. 10 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

FIG. 11 is a schematic sectional view showing a manufacturing process of the DRAM according to the embodiment.

[Explanation of symbols]

 2, 20 DRAM memory cell 4 Semiconductor substrate 6 Bit line 7a, 7b Word line 8, 11, 11 'Interlayer insulating layer 9 Gate oxide film 10 Contact hole 12 Conductive layer 12a Storage node 12b Conductive plug 14 Resist film 15 Capacitor Insulating thin film layer 16 Capacitor cell plate layer 22 Etching stopper layer 24 Conductive layer 24a Conductive plug 24b Storage node bottom wall portion 26 Dummy layer 28 Side wall 30 Storage node 40 Exposure reticle 42 Transmitted light phase inversion portion

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/04 (56) References JP-A-4-99373 (JP, A) JP-A-5-190791 (JP, A) 1992 Symposium on V LSI Technology, Digest of Technical Papers, (June 2-4, 1992) pp. 10-11 Technical Digest of International Electron Devices Meeting, (1991) pp. 10-29. 63−66

Claims (2)

(57) [Claims] An interlayer insulating layer on a semiconductor substrate; a conductive layer serving as a storage node for a capacitor on a surface of the interlayer insulating layer; a dummy layer on a surface of the conductive layer; Is processed into a ring-shaped pattern having a pattern corresponding to a boundary between the transmitted light phase-inverted portion and the other portions by exposure using a shifter-equipped exposure reticle having a transmitted light phase-inverted portion of a predetermined pattern. Forming conductive sidewalls on the inner and outer peripheries of the ring-shaped dummy layer, removing the dummy layer by etching, and forming a storage node for a double ring-shaped capacitor. A method for manufacturing a semiconductor device. 2. A method according to claim 1, wherein a plurality of storage nodes for capacitors are arranged in a matrix above the semiconductor substrate so as to be respectively connected to conductive plug layers located below. A method for manufacturing a semiconductor device according to claim 1.