JP3135316B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure centered on an electrode portion in a semiconductor device and a method of manufacturing the same, and more particularly to a flattening structure centered on a storage electrode in a semiconductor device having a memory cell. is there.

[0002]

2. Description of the Related Art In response to demands for high integration of conventional LSIs, it has become essential to form circuit patterns having functions and characteristics equal to or higher than those of current LSIs and occupying a smaller area. I have. Since a large number of memory cells, which are basic and representative circuit patterns of LSI, are formed repeatedly, it is very important how the area occupied by one unit memory cell can be reduced. I have.

FIGS. 3 and 4 show actual examples of a conventional memory cell pattern having a stack structure. The region indicated by 31 is an element region formed on the surface of the silicon substrate,
32 is an element isolation region, for example, 3000 to 8000
A field oxide film of about Å and a substrate (not shown) immediately below it are formed with element isolation impurity diffusion regions (channel stoppers). 33 is, for example, 1500 to 4
A polysilicon film having a thickness of about 2,000 mm, a refractory metal film such as tungsten (W), molybdenum (Mo), titanium (Ti), etc .;
i) is a gate electrode pattern formed by the eutectic film, and is not shown, for example, 100 to 300 °
An extremely thin oxide film (SiO ₂ film) is formed between the element region 31 and the gate electrode 33 as a gate insulating film. Further, the gate electrode 33 is also formed on the field oxide film 32, and is not shown in the figure. In the memory cell, it is formed on the element region 31 to form a gate circuit.

Reference numeral 33 'denotes a sidewall formed on the side surface of the gate electrode 33, which is made of, for example, an oxide film formed by a CVD (chemical vapor deposition) method.
Side walls 33 'are generally LDD (Lightly
-Doped-Drain), which is used as a mask when an impurity diffusion region is formed in an element region, although not shown, although not shown. Reference numeral 34 denotes a first interlayer insulating film formed of, for example, an oxide film having a thickness of about 1000 to 4000 °, and a contact pattern (hereinafter referred to as a cell contact) is formed as shown at 35. 36 is, for example, 50
This is a storage electrode formed of a polysilicon film having a film thickness of about 0 to 4000 °, and is electrically connected to the element region 31 via the cell contact 35.

In general, the storage electrode 36 has a function of storing electric charge. The larger the pattern area, the larger the amount of electric charge that can be stored, and the frequency of occurrence of a soft error that causes a failure in circuit operation can be suppressed. Further, it is known that an operation margin in a sense amplifier circuit which should receive a signal on a circuit operation is increased, and it is required that the storage electrode 36 be formed as large as possible. However, the storage electrode 36 is formed on the step of the gate electrode 33 formed in the lower layer, and has the following problems in a photolithography process when forming the storage electrode 36.

[0006]

FIG. 3B is a plan view of the memory cell as viewed from above.

[0009] Steps are formed in the portions indicated by the portions A and B in FIG. 1 due to the gate electrode 33, and in the lower portion of the step, separation from the storage electrode 36 to be formed in the adjacent element region is performed. Becomes difficult. In order to realize sufficient separation and resolution when forming the storage electrode 36 at the low steps shown in the portions A and B in the photolithography process, it is absolutely necessary to perform an over-exposure process. Will be. The overexposure process
Although it is desired to form the pattern area of the storage electrode 36 to be larger, it is actually unavoidable to be smaller.

In order to facilitate separation when forming the pattern of the storage electrode 36 at the portions indicated by A and B in FIG. 3B, and to increase the pattern area of the storage electrode 36. If the distance between the individual element regions is set to be large, the degree of integration is remarkably reduced, and this cannot be performed in practice. That is, it is very difficult and important to form only the storage electrode pattern area without reducing the integration degree of the memory cells.

[0009] Even after the storage electrode 36 is formed, there is another important problem.

FIG. 4 is a diagram for explaining another problem, and is a cross-sectional view of a joint portion between the memory cell portion and the periphery of the memory cell portion.

FIG. 4A shows a memory cell area, C shows a memory cell peripheral area, and B shows a connection area.

Although not shown, a very thin oxide film of, for example, about 50 to 300 °, or an oxide film and a nitride film (Si
₃ N ₄ film) and the insulating film is formed by, its on the insulating film plate electrode 37 formed of a polysilicon layer, for example, of about 500~4000Å are formed. The storage electrode 36 and the plate electrode 37 are interposed via a thin insulating film.
Has an electrical function as a capacitor and can store electric charge.

Further, a second interlayer insulating film 38 formed of an oxide film having a thickness of, for example, about 2000 to 8000 ° is formed on the entire surface.

A contact pattern 39 is formed on the first interlayer insulating film 34 and the second interlayer insulating film, and electrical conduction with the element region 31 should be established via the contact pattern 39, for example, about 1500 to 4000 °. A wiring pattern 40 called a bit line formed by a polysilicon film having a film thickness of, or a high melting point metal film or an eutectic film of the high melting point metal film and silicon is formed.

Further, a third interlayer insulating film 41 made of an oxide film having a thickness of, for example, about 2000 to 8000 ° is formed.

Although not shown in the state shown in FIG. 4, a contact pattern and a wiring pattern to be formed of, for example, a film containing aluminum as a main component are further formed.

However, in the memory cell A, the storage electrode 36 pattern, the plate electrode 37 pattern and the bit line 40 pattern are repeated with a very high degree of integration. No complicated repeated pattern such as the storage electrode 36 and the plate electrode 37 is formed in the joint portion B.

In general, the degree of collection / reduction of the bit line pattern 40 in the memory cell peripheral portion C is lower than that in the memory cell A portion. Therefore, as shown in FIG. And a step in the structure occurs between them. For example, the memory cell A portion becomes higher than the memory cell peripheral portion C portion by about 6000 to 20000 °.

The step caused by this structure causes a difference in an optimum focus setting value in an exposure process in a photolithography process in a subsequent wiring pattern to be formed of, for example, a film mainly composed of aluminum. In particular, when the dimension of the wiring pattern is in a submicron region from about 1.0 μm to 0.8 μm or less, this becomes remarkable and causes a serious problem.

In other words, a defocus phenomenon due to a partially different optimum value of focus is apt to occur, and a fatal defect such as a poor resolution of a wiring pattern frequently occurs.

In the present invention, since it is difficult to separate the lower part of the underlying step when the storage electrode pattern is formed as described above, it is unavoidable to perform an over-exposure process in order to realize a sufficient separation and resolution in the photolithography process. At the same time, the memory cell A part has a structural step difference compared to the memory cell peripheral part C part, and the exposure time in the photolithography process at the time of forming the wiring pattern is increased. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can also solve the problem of poor resolution caused by the difference in the optimal setting value of focus in the semiconductor device.

[0022]

According to the present invention, in forming a storage electrode in forming a memory cell of an LSI, an interlayer insulating film is formed until the surface of the storage electrode has a thickness enough to be sufficiently planarized. Etching is applied only to the region where the is to be formed, then the storage electrode forming material is also formed to a considerably thick film, and the entire surface is subjected to an etch-back process to form the storage electrode. Only the interlayer insulating film in the region where the storage electrode is not formed is selectively removed by, for example, wet etching.

[0023]

According to the present invention, since the first interlayer insulating film has a large thickness, the photolithography step required for forming the storage electrode can be used in the present invention.
The effect of the steps is reduced because the underlayer is flattened, and the photoresist pattern formed in the photolithography process is the reverse of the conventional method, that is, the reverse of the relationship between the negative and the positive of the mask pattern. ), The area of the storage electrode pattern can be increased, contrary to the prior art, even if the exposure processing is excessively performed.

Further, in the step of removing unnecessary portions of the first interlayer insulating film by etching after forming the storage electrodes, the portions are not removed at the peripheral portions of the memory cells. It is formed higher than in the memory cell, and can significantly reduce structural steps which have been a problem in the past.

[0025]

FIG. 1 is a sectional view showing a manufacturing process according to an embodiment of the present invention, and FIG. 2 is a view showing a final structure of the embodiment. The process of FIG. 1 focuses on the memory cell portion, that is, the storage electrode formation region.

FIG. 1A shows a state in which a first interlayer insulating film 4 has been formed, and the element region 1, element isolation region 2, gate electrode 3 and sidewall 3 'of the silicon substrate are the same as in the prior art. Is formed.

In this embodiment, the first interlayer insulating film 4
Has a very large thickness of, for example, about 6000 to 30,000, and its surface is almost flat due to the effect of the thickness.

Next, as shown in FIG. 1B, a resist pattern 5 is formed by a photolithography process so that only a portion where a storage electrode is to be formed in the future is exposed.

In this case, as described above, the base is flattened because the first interlayer insulating film 4 is formed thick, and furthermore, a positive type photoresist is used as in the prior art, and the exposure processing is performed. In this example, the over-exposure is performed. In this embodiment, however, the area to be the storage electrode is exposed because the part to be the storage electrode is exposed, that is, the photoresist pattern 5 has a reverse river stone. The opposite is true.

Next, as shown in FIG.
And dry etching called ECR,
For example, the first interlayer insulating film 4 of about 2000 to 20000 °
Is etched, and then the photoresist pattern 5 is removed.

Next, as shown in FIG. 1D, a cell contact 5 is formed in the same manner as in the prior art, and as shown in FIG. It is also formed very thick, about 30,000 °. Also in this case, since the film thickness is large, the surface is considerably formed flat.

Further, as shown in FIG. 1F, the entire surface of the polysilicon film 6 is etched back. In this case, when attention is paid to the shape of the polysilicon film 6 'after the etch back, the shape of the polysilicon film 6' is improved by slightly changing the ratio of the anisotropic etching component and the isotropic etching component as the etching condition. Things can be expected.

Next, as shown in FIG. 1 (g), the storage electrode 6 'is applied to the portion of the first interlayer insulating film 4 which has become unnecessary.
Is removed by using, for example, a wet etching process or the like as a mask material, as shown in this figure, the etched first interlayer insulating film 4 has a slightly concave shape.

Thereafter, as shown in FIG. 1 (h), although not shown, after forming a thin insulating film, a polysilicon film 7 of, for example, about 500 to 4000.degree.

Here, when the first interlayer insulating film 4 is subjected to the wet etching process, for example, the region around the memory cell is not etched with the portion shown in FIG. 2A as a boundary. By performing photolithography once, the thick first interlayer insulating film 4 can be left as it is.

That is, as shown in FIG. 2, since the thickness of the first interlayer insulating film 4 is left large in the peripheral region of the memory cell, the conventional memory shown in FIG. A step between the cell section A and the memory cell peripheral section C can also be solved. In FIG. 2, after the process up to FIG. 1 (h), a second interlayer insulating film 8 is formed, a contact pattern 9 is formed, and a wiring pattern 10 and a third interlayer insulating film 11 are formed thereon. It is the structural drawing which was formed. The fact that these films (8, 9, 10, 11) are flattened as a whole as a whole shows the solution of the above-mentioned step.

The above-described method is not limited to the storage electrode of the memory cell, but it is needless to say that the method can be generally applied to other electrode patterns having many complicated repetitive patterns.

[0038]

As described above in detail, according to the present invention, the thickness of the first interlayer insulating film 4 is formed to be large, and in the photolithography step required for forming the storage electrode, the underlayer is formed. Because the surface is flattened, the effect of the steps is reduced, and the photoresist pattern formed in the photolithography process is formed with a reverse stone, which is the reverse of the conventional method. Even so, the area of the storage electrode pattern becomes larger contrary to the conventional one.

Further, in the step of removing unnecessary portions of the first interlayer insulating film by etching after the formation of the storage electrodes, the photoresist is once subjected to a photolithography step so as not to be removed around the memory cells. Since the area is covered with a pattern and the peripheral portion of the memory cell is formed higher than the inside of the memory cell, it is possible to significantly reduce the structural step, which has been a problem in the past, and, in particular, in particular, the wiring It is also possible to simultaneously solve the problem that the resolution is poor due to the difference in the optimum focus setting value in the exposure processing in the photolithography process at the time of pattern formation.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a structural diagram of an embodiment of the present invention.

FIG. 3 is an explanatory view of a conventional example (part 1).

FIG. 4 is an explanatory view of a conventional example (part 2).

[Explanation of symbols]

 4 First interlayer insulating film 5 Resist pattern 6 Polysilicon film (storage electrode)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (2)

(57) [Claims] A step of preparing a semiconductor substrate having a memory cell region in which a memory cell for storing data is formed and a peripheral region around the memory cell region; and forming a semiconductor substrate on the semiconductor substrate from the memory cell region. Forming an insulating film extending in a peripheral region; etching the insulating film formed in the memory cell region so as to be lower than the insulating film formed in the peripheral region; A step of forming a storage electrode on the applied insulating film in the memory cell region; and a step of forming a plate electrode on the storage electrode via a dielectric film. Production method. A semiconductor substrate having a memory cell region in which a memory cell for storing data is formed and a peripheral region around the memory cell region; and a semiconductor substrate extending from the memory cell region to the peripheral region; An insulating film formed on the memory cell region to be thinner than the peripheral region, a storage electrode formed on the insulating film in the memory cell region, and formed on the storage electrode via a dielectric film A semiconductor device, comprising: