JPS63318152A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To contrive the augmentation of the charge storage capacitance of the title memory even when the integration of the memory is increased by a method wherein the size of charge storage electrodes is enlarged larger than a size which is limited by the resolution limit dimension of the interval between conductor layer patterns. CONSTITUTION:A DRAM cell is formed by patterning by photolithography, wherein a reactive ion etching treatment method is used, and sidewall-shaped second conductor layers 9, which are each connected ohmically to first conductor layer patterns 7A and 7B and so on, are formed by coating on the end surfaces of the whole peripheries if such poly B layer patterns as the patterns 7A and 7B, each having an almost vertical end surface. Thereby, the external sizes of charge storage electrodes SE-1 and SE-2 and so on are enlarged. By enlarging the size of the charge storage electrodes in such a way, the augmentation of the charge storage capacitance of a DRAM is contrived even when the integration of the DRAM is increased and the reliability of the information of the DRAM is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding the structure of a stacked capacitor that aims to increase the charge storage capacity, the size of the charge storage electrode is made smaller than the size limited by the pattern spacing, which is the resolution limit in photolithography. In order to increase the number of charge storage electrodes by expanding the number of charge storage electrodes, a first electrode extending from the impurity diffusion region formed in the semiconductor substrate to the word line and having a substantially vertical end surface is used.
a conductor layer pattern, and a sidewall-shaped second conductor layer selectively deposited on the end face of the first conductor layer pattern and ohmically connected to the first conductor layer pattern. A storage capacitor having a stacked structure comprising a charge storage electrode, a dielectric film formed on the entire surface of the charge storage electrode, and a counter electrode covering the charge storage electrode with the dielectric film interposed therebetween. Equip and configure.

[Industrial application field]

The present invention relates to a dynamic random access memory (DRAM) having a stacked capacitor, and more particularly to a structure of a stacked capacitor that increases charge storage capacity.

In a DRAM, a capacitor is extended above adjacent word lines to increase the effective area of the capacitor including the uneven step portion formed by the word line, thereby increasing storage capacitance and improving read accuracy and α. A storage capacitor with a stacked structure is used, which improves line soft error resistance and increases the reliability of stored information.

In such a stacked capacitor structured DRAM,
As higher integration progresses and the cell area is further reduced, it will be especially necessary to suppress the reduction in the effective area of the capacitor as much as possible to prevent deterioration in readout accuracy and α-ray soft error resistance. In highly integrated DRAMs where the cell area is reduced and the cells are arranged at high density, the size of the capacitor electrode is limited to the required pattern spacing due to the pattern resolution limit in photolithography. There is a problem in that it cannot be expanded and therefore a satisfactory storage capacity cannot be obtained, and an improvement is desired.

[Conventional technology]

Conventionally, the storage capacitor in the above DRAM is as follows:
It was formed by the method shown with reference to Figures (a) to (C).

Refer to FIG. 3. First, a gate insulating film 3 is formed on a p-type silicon (St) M plate 1, and a first
The word line (gate electrode) 48, 4B, 4 is made of an n9 type polycrystalline silicon (poly-Si) layer, and has a first silicon dioxide (SiO□) film 68, which serves as an insulating film between the eyebrows, on the upper part.
C140, etc., and using the word line as a mask, impurity ions are implanted into the substrate surface to form the first and third n" type S/D regions 5A, 5C connected to the storage electrode of the capacitor and the bit line. A second n-type S/D region 5B etc. to be connected is formed, and then, for example, a second
A 5T (h film) is grown in a vapor phase, and the second SiO□ film is selectively etched away using a conventional planar etching method using reactive ion etching (RIE) to form word lines 48, 4B, and 4G. , 4D, etc., are formed with Si0g sidewalls 6B made of a second SiO□ film.Here, the field insulating film (not shown) that separates the front and back directions with respect to the plane of the paper and the 5i02 sidewalls 6B provide insulation. Membrane openings 51A, 51C and 51B are formed.

FIG. 3 (see bl) Next, an n° type second polySt layer is formed on the substrate,
Patterning is performed by ordinary photolithography using RIB processing as an etching means, and charge storage electrodes 52A and 52B made of the second n+ type polySt are connected to the openings 51A and 51C, and the bit line is connected to the opening 51B. electrodes 53 are formed respectively.

FIG. 4 is a plan view when this process is completed, and each object is indicated by the same reference numeral.

In addition, during the above patterning, the shortest distance D1 between each electrode
is usually limited to a value of about 1.5 μm or more due to the resolution limit of the aligner in photolithography.

Referring to FIG. 3(C), a silicon nitride (SiJ) dielectric film 10 is then formed on the substrate including the surfaces of the electrodes 52A, 52B, and 53 by, for example, chemical vapor deposition (CVD). A third n-type poly-St layer is formed on the substrate and patterned using a conventional method, and the upper portions of the charge storage electrodes 52A, 52B, etc. made of the third poly-St layer are formed through a dielectric film IO. A cell plate 54 is formed from an integrated opposing electrode portion that is selectively covered.

As mentioned above, the conventional stacked capacitor structure DRA
The charge storage electrodes 52A, 52B, etc. in M are RIE
The pattern is formed by photolithography using processing, and therefore the distance between the adjacent pattern, for example, the bit line connection electrode 53, which is patterned from the same conductor layer (second polySt layer) is as described above. At least, it was formed to have a thickness of about 1.5 μm or more, which is the resolution limit of an aligner in lithography.

For this reason, in conventional stacked capacitor structured DRAMs, when the cell area is reduced due to higher integration, the size of the charge storage electrode is restricted by the required pattern spacing due to the resolution limit in patterning. As a result, the storage capacity of the capacitor is significantly reduced, resulting in a problem that alpha ray soft error resistance and information read accuracy deteriorate, resulting in a decrease in the reliability of the DRAM information.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention is that, as described above, in the conventional stacked capacitor structured DRAM, as the degree of integration increases, the storage capacity of the capacitor decreases extremely, and the reliability of the DRAM information decreases. This is a problem that has arisen.

[Means for solving problems]

The above-mentioned problem is caused by the first impurity diffusion region formed in the semiconductor substrate extending from above the word line and having a substantially vertical end surface.
a conductor layer pattern, and a sidewall-shaped second conductor layer pattern that is selectively deposited on the end face of the first conductor layer pattern and ohmically connected to the first conductor layer. A storage capacitor having a stacked structure comprising a charge storage electrode, a dielectric film formed on the entire surface of the charge storage electrode, and a counter electrode covering the charge storage electrode with the dielectric film interposed therebetween. The problem is solved by a DRAM according to the present invention.

[For production]

That is, the stacked capacitor structure DRAM according to the present invention
In this method, a charge storage electrode constituting a capacitor is formed by a first conductor layer pattern formed by photolithography with a size limited by the minimum pattern spacing required due to the pattern resolution limit in photolithography; A second conductive layer is formed on the end face of the entire circumference in the form of a sidewall, and the size of the charge storage electrode is expanded beyond the size limited by the resolution limit dimension of the pattern spacing. do.

As a result, the charge storage capacity can be increased even when the device is highly integrated, and the reliability of the DRAM information can be improved.

〔Example〕

The present invention will be specifically described below with reference to the drawings and examples.

FIG. 1 is a perspective plan view (a) and an A-A sectional view (b) schematically showing an embodiment of a DRAM according to the present invention, and FIG.
a> to (e) are process cross-sectional views showing the manufacturing method.

Identical objects are indicated by the same reference numerals throughout the figures.

In FIGS. 1(a) and (b), 1 is p-type silicon (S
t) Substrate, 2 is a field insulating film, 3 is a gate insulating film,
4^, 4B, 4C, 4D are the first n0 type poly 5i (P
Word line (gate electrode) consisting of oly^) layer, 5A
, 5B, and 5C are first, second, and third n'' type source/drain (S/D) regions, and 6^ and 6B are Sin serving as the first interlayer insulating film.

Membranes 7A and 7B are the second layer with a thickness of about 2,000 to 3,000 people.
n.

A first conductor layer pattern that becomes a part of a charge storage electrode patterned from a polySi (PolyB) layer, 8 is the same bit line connection electrode patterned from a PolyB layer, 9 is a thickness A third N9 type polySt (PolyC) layer of approximately 2,000 to 3,000 layers is formed in the form of a sidewall and is adhered to the first conductor layer pattern and the end face of the VI-7T wire connection electrode. 10 is a dielectric film formed on the exposed surface of at least the first conductor layer pattern and the second conductor layer, and 11 is a dielectric film made of a Si3N film having a thickness of about 200 layers. A counter electrode (cell plate) made of an n-type poly 5T (PolyD) layer, 12 a hole in the counter electrode, 13 a second glabella insulating film made of phosphosilicate glass (PSG), 14 made of aluminum, etc. Shows bit lines.

That is, the DRAM cell according to the present invention has PolyB layer patterns such as first conductive layer patterns 7A and 7B, which are patterned by photolithography using RIE processing and have substantially vertical end faces, as shown in the figure, for example. A second conductive layer 9 in the form of a sidewall is deposited on the entire circumferential end surface of the electrode by a method to be described later, and is ohmically connected to the first conductive layer patterns 7A, 7B, etc., thereby forming a charge storage electrode. The external dimensions of SR-1, 5E-2, etc. will be expanded. This enlarged size is controlled by the thickness of the PolyC layer when forming the sidewall-shaped second conductor layer 9, but in this example, the enlarged size corresponds to the conventional size formed by patterning from the PolyB layer. When the outer dimensions of the conductor layer patterns 7A and 7b of No. 1 are 3 μm square, that is, an area of 9 μm2, and the thickness of the PolyC layer forming the sidewall is 0.2 μm, the charge storage electrodes 5E-1 and 5E -2nd magnification area is 2゜5
It becomes about 6 μm2, and the increase rate of the accumulated charge is about 28%.

A method of forming the DRAM cell shown in the above embodiment will be explained below with reference to the drawings.

FIG. 2 (see al) In other words, a gate insulating film 3 is formed on a p-type Si substrate 1 by a method similar to the conventional method. It is made of n-type polyA R of about 1.5 μm and has a thickness of 300 mm on the top.
Approximately 0 people 0 First SiO□ film 6A Total 6A word line 4A
, 4B, 4C14D, etc., and then the word line 4A
, 4B, 4C14D, etc. as a mask and apply arsenic (^s
+) is ion-implanted to connect the first electrode to the charge storage electrode.
1. Form a second S/D region 5B connected to the third source/drain (S/D) regions 5A and 5C and the pinto line.

Then, as in the conventional method, a second SiO□ film with a thickness of about 3000 g, for example, is formed as an interlayer insulating film on the substrate by the CVD method, and the second 330 g film is selected by plane etching means using RIE processing. Then, a second SiO□ film 6B in the form of a sidewall is formed on the side surfaces of the word lines 4A, 4B, 4C140, etc.

Then, a PolyB layer with a thickness of about 2,000 to 3,000 layers is formed on the substrate by the CVD method as in the conventional method, and the PolyB layer is made into an n+ type by an ion implantation method. By patterning by lithography, the first and second layers are formed of the current PoyB layer and have a pattern interval between adjacent patterns of, for example, about 1.5 μm, which is the resolution limit dimension of the pattern in the photolithography. 3 S/D area 5A,
first conductor layer patterns 7^, each in contact with 5C;
7B and the bit line connection electrode 8 in contact with the second S/Diil region 5B is formed.

Refer to FIG. 2(b) Next, in the method of the present invention, a PolyC layer with a thickness of about 2,000 to 3,000 layers is formed on the substrate by CVO method, and then the PolyC layer is made into an n-type by ion implantation method or the like. After that, the Polyc layer is selectively removed by planar etching (etch pack) using RIE processing, and side surfaces made of the PolyC layer are formed on the entire peripheral end surfaces of the first conductor layer patterns 7A, 7B and the bit line connection electrode 8 pattern. A wall-shaped second conductor layer 9 is left to form.

Note that, as described above, the first conductor layer patterns 7A, 7 corresponding to the conventional size are formed by patterning.
The charge storage electrode SE~1 has an outer dimension larger by about 0.4 μm than B by the sidewall-like second conductor N9.
and 5E-2 are formed.

FIG. 2 (see C1) Next, as in the conventional case, the charge storage electrode S[!-
For example, a thickness of 20
A dielectric film 10 made of PoSi3N is formed on the substrate to a thickness of 2000 to 300 nm by CVO method.
After forming approximately 00 PolyD eyebrows and making the PolyD layer into an n-type by ion implantation or the like, the PolyD layer is patterned using the same conventional photolithography technique to form the bit line connection electrode 8. The dielectric film 1 has an opening 12 that exposes the entire surface with a margin, and at least the upper part of the charge storage electrodes SB-1 and 5E-2 is covered with the dielectric film 1.
Integral poly-Si counter electrode (cell play) covering through 0
) 11 is formed.

Refer to FIG. 1. Next, a PSG interlayer insulating film 13 is formed on the substrate by a conventional method, a contact window is formed in the interlayer insulating film 13, and the contact window is in contact with the bit line connecting electrode 8. A bit line (4) extending in a direction perpendicular to the word line is formed on the PSG interlayer insulating film 13, and a cover insulating film (not shown) is then formed, thereby completing the DRAM according to the present invention.
The cell is completed.

As is clear from the above description, according to the present invention, DRA
The distance between the charge storage electrode of the stacked information storage capacitor of M and the conductive pattern formed using the same poly-Si layer is the minimum pattern that is limited by the resolution limit of the analyzer in the lithography process. It is possible to make the distance closer than the interval. Therefore, at the same degree of integration, the surface area of the charge storage electrode increases as described above, and the storage capacity can be increased. Note that the rate of increase in storage capacity can be adjusted to a certain degree by changing the thickness of the sidewall-shaped second conductor layer.

Further, according to the present invention, other electrode patterns such as bit line connection electrodes formed by patterning from a poly-Si layer of the same layer as the first conductor layer pattern from the manufacturing process also have the same pattern as the first conductor layer pattern, that is, charge storage. Since they are enlarged in the same way as the electrodes, there is more margin for alignment when forming wiring connection windows to those electrodes, which simplifies the manufacturing process and improves the manufacturing yield.

Furthermore, in the present invention, a high melting point metal, a high melting point metal silicide, or the like may be used for the first and second conductor layers and the word line in addition to the poly-Si layer shown in the embodiment.

〔Effect of the invention〕

As described above, according to the present invention, the area of the charge storage electrode of the stacked storage capacitor constituting the DRAM cell can be further reduced by the pattern spacing without being limited by the resolution limit of the analyzer in the photolithography process. ,
It can be further expanded.

Therefore, according to the present invention, since the charge storage capacity of a highly integrated DRAM cell is increased, the read accuracy and α-ray soft error resistance of the DRAM cell are improved, and the reliability of the information is improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a plane (al and A-A cross section (b)) of an embodiment of the present invention, and FIGS. 2(a) to (C1 are DRAMs shown in the above embodiment)
A process cross-sectional view showing an example of a cell manufacturing method, FIG.
FIG. 4 is a process plan view of the conventional manufacturing method. In the figure, 1 is a p-type Si substrate, 2 is a field insulating film, 3 is a gate insulating film, 4A, 4 [1, 4C, 4D are word lines, 9, 5B, 5
C is the 11th second and third S/D regions, 6A and 6B are Si
7A, 7B are first conductor layer patterns, 8 is a bit line connection electrode, 9 is a sidewall-shaped second conductor layer, 10 is 5i3
11 is a counter electrode (cell plate); 12 is a flowering of the counter electrode that completely exposes a bit line connection electrode; 13 is a PSG interlayer insulating film; and 14 is a bit line. (b) A-A back rib diagram 6 ri 4;

Claims (1)

[Scope of Claims] A first conductor layer pattern extending from an impurity diffusion region formed in a semiconductor substrate onto a word line and having a substantially vertical end surface; a charge storage electrode consisting of a sidewall-shaped second conductor layer that is deposited on the substrate and ohmically connected to the first conductor layer pattern; and a dielectric formed on the entire surface of the charge storage electrode. 1. A dynamic random access memory comprising a storage capacitor having a stacked structure, the storage capacitor having a stacked structure having a film and a counter electrode covering the charge storage electrode with the dielectric film interposed therebetween.