JP3204215B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a capacitor electrode of a memory cell array and a method of forming the same.

[0002]

2. Description of the Related Art A DRAM is a semiconductor device capable of arbitrarily inputting and outputting stored information. Here, this DRA
The M memory cell, which includes one transfer transistor and one capacitor, is structurally simple and is widely used as the most suitable for high integration of a semiconductor device.

In such a memory cell capacitor,
With the high integration of semiconductor devices, those having a three-dimensional structure have been developed and used. The three-dimensional structure of the capacitor is based on the following reasons. 2. Description of the Related Art With miniaturization and higher density of semiconductor elements, it is essential to reduce the area occupied by capacitors. However, in order to ensure stable operation and reliability of the DRAM, a capacitance value equal to or more than a certain value is required. Therefore,
Change the electrode of the capacitor from a planar structure to a three-dimensional structure,
It is necessary to increase the surface area of the capacitor electrode within the reduced occupied area.

The three-dimensional structure of the DRAM memory cell includes a stack structure and a trench structure. Each of these structures has advantages and disadvantages, but the stacked structure has high resistance to the incidence of alpha rays or noise from circuits and the like, and operates stably even when the capacitance value is relatively small. For this reason, it is considered that a stacked capacitor is effective even in a 4 gigabit DRAM in which the design standard of the semiconductor element is about 0.13 μm.

[0005] However, even in such a capacitor having a stacked structure (hereinafter, referred to as a stacked capacitor), it is necessary to devise a method of enlarging the surface area of the lower electrode (called a storage electrode) of the capacitor. Therefore, various studies have been made to form the storage electrode into a cylinder structure or to form surface irregularities.

Here, a memory cell having a basic stacked capacitor will be described with reference to FIG.
FIG. 5 is a cross-sectional view of two memory cells.

As shown in FIG. 5, a field oxide film 102, which is an element isolation insulating film, is formed on the surface of a silicon substrate 101, and a transfer transistor forming a memory cell is formed in an element active region where the field oxide film 102 is not formed. A capacitor is formed. Hereinafter, the main part will be described.

[0008] Word lines 103 and 103a serving as gate electrodes of transfer transistors of a memory cell are formed on a silicon substrate in a predetermined region via a gate oxide film. The word lines 103b and 103c are formed on the field oxide film 102. This word line 103
Reference characters b and 103c serve as gate electrodes of transfer transistors of adjacent memory cells.

[0009] A diffusion layer 104 for a capacity and a diffusion layer 105 for a bit line are formed as source / drain regions of a transfer transistor of one memory cell. Further, a diffusion layer 104a for a capacity and a diffusion layer 105a for a bit line which are to be source / drain regions of a transfer transistor of another memory cell are also formed. Further, a first interlayer insulating film 106 is formed so as to cover the word lines 103, 103a, 103b, and 103c.

A storage electrode 107 electrically connected to the capacitance diffusion layer 104 through a capacitance contact hole provided in the first interlayer insulating film 106 and a storage electrode 107a electrically connected to the capacitance diffusion layer 104a are formed. ing. A capacitance insulating film 108 is formed on the surfaces of the storage electrodes 107 and 107a, and a plate electrode 109 is formed so as to cover the capacitance insulating film 108.

Then, a second interlayer insulating film 110 is formed so as to cover the entire surface.
A bit line contact hole is provided in a predetermined region of the bit line diffusion layer 10 through the bit line contact hole.
A bit line 111 electrically connected to the first and the fifth 105a is provided. Thus, two memory cells are formed.

Further, in order to reduce the area of the memory cell, a method of vertically stacking the storage electrodes 107 and 107a of the capacitors of adjacent memory cells in the memory cell described with reference to FIG. 5 has been proposed. As such a conventional technique, for example, there is a technique described in JP-A-6-13569.

[0013]

However, in the memory cell having the structure as shown in FIG. 5, there is a limit in reducing the area of the memory cell, and it is difficult to increase the density of the memory cell.
It will be difficult to support next-generation semiconductor devices such as gigabit DRAMs.

Therefore, a technique for stacking the storage electrodes of the above-mentioned capacitors has been proposed. In the above-mentioned conventional technique, at least six photolithography steps are required to form such a capacitor. The number of steps increases.

When such a technique is applied to a memory cell having a capacitor over bit line (COB) structure, in order to form an upper layer pattern, a large number of lower layer patterns must be exposed in an exposure process using a stepper or the like. Matching becomes indispensable. For example, in order to form a capacitor contact hole, it is necessary to perform aligning exposure on the pattern of the lower layer word line, bit line, and lower layer capacitor. For this reason, it is necessary to increase the margin for alignment (margin), which is an obstacle to miniaturization of memory cells.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can facilitate the reduction in size of a memory cell having a stacked capacitor and can simplify the method for manufacturing the same.

[0017]

[0018]

For this purpose, the semiconductor device according to the present invention is used.
In the body device, in an array of memory cells formed by one transfer transistor and one capacitor,
In the memory cell array, storage electrodes of capacitors of predetermined memory cells are arranged in a first layer, and storage electrodes of capacitors of other memory cells are arranged in a second layer.

Here, the storage electrodes arranged in the first layer and the storage electrodes arranged in the second layer are formed in the same pattern. The storage electrodes of the first layer are arranged at a predetermined pitch, and the storage electrodes of the second layer are arranged at another predetermined pitch.

Furthermore, a first plate electrode is formed on the storage electrode of the first layer via a capacitor insulating film, and an opening is formed in a predetermined region of the first plate electrode.
A sidewall insulating film is formed on a side wall of the opening,
The second-layer storage electrode is connected to the source / drain region of the transfer transistor through a gap between the sidewall insulating films and a capacitor contact hole thereunder.

Furthermore, a second plate electrode is formed on the storage electrode of the second layer via a capacitance insulating film, and the second plate electrode is provided between the storage electrodes of the second layer. It is connected to the first plate electrode.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a transfer transistor forming a memory cell, forming a first interlayer insulating film having a flat surface, and forming a first capacitor contact hole in a predetermined region of the first interlayer insulating film Filling the first capacitor contact hole and forming a first layer storage electrode; and forming a first opening in a predetermined region on the first layer storage electrode. Forming a first plate electrode having a portion and having a second interlayer insulating film thereon; forming a sidewall insulating film on a side wall of the first opening; Fill the gap and the second
Forming a storage electrode of the layer.

Then , the second interlayer insulating film is selectively etched using the second-layer storage electrode as a mask to form a second opening, and the first opening is formed through the second opening. A second plate electrode is formed so as to be connected to the plate electrode.

According to the present invention, the capacitors of the memory cell array are formed in two layers. This makes it very easy to reduce the memory cell area.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a memory cell array section in the case of the present invention. FIG.
FIG. 4 is a plan view for explaining features of the present invention in a capacitor structure of a memory cell. Further, FIG.
FIG. 14 is a cross-sectional view of the memory cell structure of FIG.

As shown in FIG. 1, a field oxide film 2 is formed on the surface of a silicon substrate 1, and a plurality of transfer transistors and capacitors forming a memory cell are formed in an element active region where the field oxide film 2 is not formed. Thus, a memory cell array is formed.

In the same manner as in the prior art, word lines 3, 3a, 3
b and 3c are formed on the silicon substrate in a predetermined region via a gate oxide film. The word lines 3d, 3e and the like are formed on the field oxide film 2. These word lines 3d, 3e and the like serve as gate electrodes of transfer transistors of adjacent memory cells.

Further, a diffusion layer 4 for a capacity and a diffusion layer 5 for a bit line to be source / drain regions of a transfer transistor of the first memory cell are formed. Also, the source of the transfer transistor of the second memory cell
A diffusion layer 4a for a capacity and a diffusion layer 5 for a bit line to be a drain region are also formed. Further, a diffusion layer 4b for a capacity and a diffusion layer 5a for a bit line which are to be the source / drain regions of the transfer transistor of the third memory cell are formed. Then, the capacity diffusion layer 4c serving as the source / drain region of the transfer transistor of the fourth memory cell
And a bit line diffusion layer 5a are also formed.

The word lines 3, 3a, 3b, 3c,
A first protective insulating film 6 is formed so as to cover the surfaces of 3d, 3e and the like. Further, a first interlayer insulating film 7 is formed so as to cover the entire surface. Further, a second protective insulating film 8 is formed on the surface of the first interlayer insulating film 7. Here, the etching rate of the first protective insulating film 6 and the second protective insulating film 8 is set to be lower than the etching rate of the first interlayer insulating film 7. Although not shown, the bit lines are electrically connected to the bit line diffusion layers 5 and 5a, and are disposed in the first interlayer insulating film.

Then, the first-layer storage electrode 10 electrically connected to the capacitance diffusion layer 4 or 4b through the capacitance contact hole 9 provided in the second protective insulating film 8 and the first interlayer insulating film 7, respectively. 10a are formed. Further, a first capacitance insulating film 11 is formed on the surfaces of the first-layer storage electrodes 10 and 10a.

Further, a first layer plate electrode 12 is formed so as to cover the first capacitance insulating film 11. Then, a second interlayer insulating film 13 is formed on the first layer plate electrode 12, and a sidewall insulating film 14 is provided on a side wall of the first layer plate electrode 12.

As described above, the second capacitance is formed by the capacitance contact hole 9 a provided in the second protective insulating film 8 and the first interlayer insulating film 7 and the gap provided between the sidewall insulating films 14. Contact hole 15 is formed.

Then, the second capacitance contact hole 1
The storage electrodes 16 and 16a of the second layer are formed so as to be electrically connected to the capacitance diffusion layers 4a and 4c through the respective layers 5. Further, a second capacitance insulating film 17 is provided on the surfaces of the storage electrodes 16 and 16a of the second layer. Further, the second capacitor insulating film 17 is covered so as to cover the second capacitor insulating film 17.
A layer of plate electrode 18 is formed.

As described above, the feature of the memory cell of the present invention resides in that the storage electrodes constituting the capacitor of the memory cell are arranged in two layers by the memory cell. At the same time, the plate electrode as the counter electrode is formed over two layers.

Next, the features of the present invention in the capacitor structure of the memory cell will be described with reference to FIG. FIG.
FIG. 4 is a plan view showing an arrangement of the storage electrodes in an example.

As shown in FIG. 2A, in the first example, the storage electrodes 21a and 21a of the first layer having the same pattern dimensions are used.
1b, 21c, 21d, 21e, 21f, and 21g are arranged so as to be densest. In this case, the first-layer storage electrodes 21c, 21d, and 21e are arranged so that the phase is shifted with respect to the arrangement position of the first-layer storage electrodes 21a, 21b, 21f, and 21g. These first-layer storage electrodes are electrically connected to the above-described capacitance diffusion layer through the first capacitance contact hole 22.

Further, the storage electrodes 23a, 23b, 23c, and 2 of the second layer are formed on the storage electrodes of the first layer via the first plate electrode and the second interlayer insulating film as described above.
3d, 23e, 23f, 23g and 23h are formed. Here, the pattern of the storage electrodes of the second layer is arranged so as to be the same as the pattern of the storage electrodes of the first layer, and to be the densest. These second-layer storage electrodes are also electrically connected to the above-mentioned capacitance diffusion layers through the second capacitance contact holes 24. The second capacitor contact hole 24 is provided in the gap between the storage electrode patterns of the first layer.

As shown in FIG. 2B, the basic method of arranging the storage electrodes of the first layer and the second layer is the same in the second example. However, in this case, there is no such phase shift in the arrangement of the storage electrodes in the first layer. The same applies to the arrangement of the storage electrodes in the second layer. Thus, in the second example, the first-layer storage electrodes 25a, 25b, 2
The storage electrodes 26 of the second layer are arranged between the patterns 5c and 25d. Then, through the second capacitor contact holes 27 provided at the corners of the four first-layer storage electrode patterns, electrical connection is made to the above-described capacitor diffusion layer.

Next, a method of manufacturing a memory cell array according to the present invention will be described below with reference to FIG. here,
The same components as those described in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 3A, a field oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1 by a known method. Then, the field oxide film 2
A transfer transistor and a capacitor constituting a memory cell are formed in an element active region where no
It is formed as follows.

The surface of the silicon substrate 1 is thermally oxidized to form a gate oxide film. Then, word lines 3, 3a, 3b, 3c serving as gate electrodes of the transfer transistor are formed with a tungsten polycide film or the like. Also,
Word lines 3d, 3e, etc. are formed on field oxide film 2.

By implanting impurity ions such as phosphorus and a subsequent heat treatment, the diffusion layers for capacitors 4, 4a, 4 are self-aligned (self-aligned) with the word lines 3, 3a, 3b, 3c.
b, 4c and bit line diffusion layers 5, 5a are formed.

Next, a first protective insulating film 6 is formed on the surfaces of the word lines 3, 3a, 3b, 3c, 3d, 3e by depositing a silicon oxide film by normal pressure CVD (chemical vapor deposition) and etching back. Is formed. Then, an insulating film is formed,
Although not shown, bit lines connected to the bit line diffusion layers 5 and 5a are formed.

Then, a BPSG film (a silicon oxide film containing boron glass and phosphorus glass) having a thickness of about 600 nm.
Is deposited on the entire surface by the CVD method. Furthermore, this BPSG
The surface of the film is planarized by a CMP (chemical mechanical polishing) method.
Thus, the first interlayer insulating film 7 is formed, a silicon oxynitride film having a thickness of about 100 nm is deposited on the surface of the first interlayer insulating film 7 by the CVD method, and the second protective insulating film 8 is formed. Is formed.

Next, the first photolithography technique and the dry etching technique are used to reach the first diffusion layers 4 and 4b for the capacitors.
The capacitor contact hole 9 and the first capacitor contact hole 9a reaching the capacitor diffusion layers 4a and 4c are simultaneously formed. Here, the size of these first capacitance contact holes is about 0.2 μm.

Next, a polysilicon film having a thickness of about 500 nm is deposited on the entire surface by the CVD method. Then, an impurity such as phosphorus is doped and patterned. Here, the protective insulating film 8 serves as the first interlayer insulating film 7 during the above patterning.
Mask that protects Thus, the first-layer storage electrodes 10 and 10a having a predetermined pattern are formed. At the same time, a plug 19 is formed in the first capacitor contact hole 9a in this step.

Next, a first capacitor insulating film 11 is formed of a silicon nitride film or the like on the surfaces of the first-layer storage electrodes 10 and 10a.

Next, a tungsten polycide film or the like having a thickness of about 200 nm is deposited on the entire surface. Then, a patterned second interlayer insulating film 13 is formed. Here, the thickness of the second interlayer insulating film 13 is set to about 200 nm. As shown in FIG. 3B, the second interlayer insulating film 13 is used as an etching mask, and the above-mentioned tungsten polycide film or the like is dry-etched, so that a first opening 20 is formed. Thus, the first plate electrode 12 is formed.

Next, a silicon oxide film having a thickness of about 100 nm is deposited on the entire surface by the CVD method. Then, etch back is performed, and as shown in FIG. 3C, the sidewall insulating film 14 is formed on the side wall of the first opening 20. Thus, the second capacitance contact hole 15 is formed.

Next, as shown in FIG.
A polysilicon film is deposited on the entire surface by the CVD method.
Then, an impurity such as phosphorus is doped and patterned. Thus, the storage electrodes 16 and 16a of the second layer having a predetermined pattern are formed.

Then, a second capacitor insulating film 17 is formed on the surfaces of the storage electrodes 16 and 16a of the second layer. This second capacitance insulating film 17 is formed of the same film as the first capacitance insulating film. Next, a second-layer plate electrode 18 is formed so as to cover the second capacitance insulating film 17. Here, the second plate electrode 18 is formed of a tungsten polycide film having a thickness of about 200 nm. As described above, the memory cell structure described in FIG. 1 is completed.

As described above, in the present invention, the capacitors of the memory cells are formed in two layers. This makes it very easy to reduce the memory cell area. Alternatively, since the storage electrode area of the capacitor can be doubled as compared with the conventional case, the capacitance value is set to 2 correspondingly.
And the reliability of the semiconductor device is greatly improved.

In the present invention, since the second capacitor contact hole is formed in a self-aligned manner in the first opening 20 provided in a predetermined region of the first plate electrode, a registration margin is provided. Is unnecessary, and miniaturization of the memory cell is further facilitated.

Next, a second embodiment of the present invention will be briefly described with reference to FIG. FIG. 4 is a cross-sectional view of another memory cell array portion in the case of the present invention. In the second embodiment, the first plate electrode and the second plate electrode are electrically connected inside the memory cell. Otherwise, the configuration is the same as that of the first embodiment. Hereinafter, the same components are denoted by the same reference numerals. Then, the differences will be mainly described.

As shown in FIG. 4, a second interlayer insulating film 13 is formed on a first plate electrode 12 formed in the same manner as in the first embodiment. Then, the second interlayer insulating film 13 between the storage electrodes 16 and 16a of the second layer is selectively removed to form a second opening 28. The second plate electrode 18 is electrically connected to the first plate electrode 12 through the second opening 28.

In the second embodiment, the first plate electrode can be formed of a conductor film having a relatively high resistance, for example, a polysilicon film containing a phosphorus impurity. This polysilicon film has good electrical stability with the capacitance insulating film formed of the silicon nitride film, and a highly reliable capacitor can be formed. Alternatively, the thickness of the first plate electrode can be made extremely thin, the aspect ratio of the second capacitor contact hole is reduced, and the formation of the second capacitor contact hole becomes easy. In this case, the second plate electrode 18 is formed of a conductive film having a low resistance.

In the above embodiment, the case where the storage electrode of the capacitor is formed in two layers has been described. The present invention can be similarly applied to a case where storage electrodes are formed in three or more layers.

Also, the memory cell according to the present invention has a DR
The present invention can be similarly applied to semiconductor devices other than AM.

[0059]

According to the semiconductor device of the present invention, in the memory cell array of the semiconductor device, the storage electrodes of the capacitors of the adjacent memory cells are formed in the same shape and stacked on each other. For example, in a memory cell array, storage electrodes of capacitors of predetermined memory cells are arranged in a first layer, and storage electrodes of capacitors of other memory cells are arranged in a second layer. Here, the storage electrodes arranged in the first layer and the storage electrodes arranged in the second layer are formed in the same pattern shape. The storage electrodes of the first layer are arranged at a predetermined pitch, and the storage electrodes of the second layer are arranged at another predetermined pitch.

Therefore, it is very easy to reduce the area of the memory cell. Alternatively, the reliability of the semiconductor device is greatly improved.

Further, according to the present invention, the capacitor contact hole for connecting the second-layer storage electrode to the source / drain region of the transfer transistor is provided in the opening provided in the predetermined region of the first plate electrode. Since it is formed in a self-aligned part, the alignment margin is unnecessary,
The miniaturization of the memory cell is further facilitated.

As described above, according to the present invention, ultra-high integration and high density of a semiconductor device such as a DRAM are further promoted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a memory cell array section for describing a first embodiment of the present invention.

FIG. 2 is a plan view of a memory cell array section for explaining features of the present invention.

FIG. 3 is a cross-sectional view of a memory cell array portion according to the embodiment in the order of manufacturing steps.

FIG. 4 is a cross-sectional view of a memory cell array section for describing a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a memory cell array section for explaining a conventional technique.

[Explanation of symbols]

1,101 silicon substrate 2,102 field oxide film 3,3a, 3b, 3c, 3d, 3e word line 4,4a, 4b, 4c, 104,104a capacitance diffusion layer 5,5a, 105,105a bit line diffusion Layer 6 First protective insulating film 7, 106 First interlayer insulating film 8 Second protective insulating film 9, 9a, 22 First capacitance contact hole 10, 10a, 21a, 21b, 21c, 21d, 21
e, 21f, 21g, 25a, 25b, 25c, 25d
Storage electrode of first layer 11, 17, 108 Capacitive insulating film 12 First plate electrode 13, 110 Second interlayer insulating film 14 Sidewall insulating film 15, 24, 27 Second capacitor contact hole 16, 16a, 23a, 23b, 23c, 23d, 23
e, 23f, 23g, 23h Storage electrode of second layer 18 Second plate electrode 19 Plug 20 First opening 28 Second opening 107 Storage electrode 109 Plate electrode 111 Bit line

Claims (4)

(57) [Claims] 1. In an array of memory cells formed by one transfer transistor and one capacitor, storage electrodes of capacitors of a predetermined memory cell in the memory cell array are arranged in a first layer, A storage electrode of a capacitor of the memory cell is arranged in a second layer, a first plate electrode is formed on the storage electrode of the first layer via a capacitor insulating film, and a predetermined electrode of the first plate electrode is formed. An opening is formed in the region, a sidewall insulating film is formed on a side wall of the opening, and the second-layer storage electrode passes through a gap of the sidewall insulating film and a capacitive contact hole thereunder. Connected to the source / drain region of the transfer transistor ;
A second plate electrode is formed on the storage electrode via a capacitive insulating film.
Formed between the storage electrodes of the second layer.
2. A semiconductor device, wherein two plate electrodes are connected to the first plate electrode . 2. A method according to claim 1, characterized in that the storage electrodes which are arranged in the second layer and the storage electrode are arranged in the first layer is formed in the same pattern
Serial mounting semiconductor device. Wherein the first layer of the storage electrode is arranged at a predetermined pitch, according to claim 2, wherein the second layer of the storage electrode is characterized in that it is arranged in a different predetermined pitch Semiconductor device. 4. A step of forming a transfer transistor forming a memory cell, a step of forming a first interlayer insulating film having a flat surface, and a step of forming a first capacitor in a predetermined region of the first interlayer insulating film. Forming a first contact hole, filling the first capacitor contact hole and forming a first-layer storage electrode, and forming a predetermined region on the first-layer storage electrode. Forming a first plate electrode having a first opening and a second interlayer insulating film thereon; forming a sidewall insulating film on a side wall of the first opening; Forming a second-layer storage electrode by filling a gap in the sidewall insulating film; and selectively etching the second interlayer insulating film using the second-layer storage electrode as a mask. And the second opening is formed. Forming a second plate electrode so as to be connected to the first plate electrode through a portion.