JPH05347392A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a fine ring-shaped storage node without remarkably increasing the steps by exposing by using an exposure reticle with a shifter, and forming a storage node forming fine pattern with a pattern corresponding to a boundary between a transmitted light phase inverted part and the other part. CONSTITUTION:When a resist film 14 for forming a storage node is pattern- processed, an exposure reticle 40 with a shifter is used. A transmitted light phase inverted part 42 is formed in a predetermined pattern on the reticle 40. Accordingly, when the reticle 40 is used, an exposure light passed through the part 42 is inverted with respect to the phase of the light passed through the other part, and hence a part to become a shade of a light is generated due to an interference of the light on the boundary part, and a fine pattern is formed. Thus, a resist film 14 can be pattern-processed in a ring state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a capacitor having a large storage capacity with a small cell area.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and large capacity of semiconductor devices, for example, a typical semiconductor LSI memory, DR
In the AM, it is difficult to secure the area of the storage node for a capacitor as the cell area is reduced, and it is difficult to form a capacitor having a desired capacitance on a semiconductor substrate. Recently, a memory cell for DRAM in which a storage node for a capacitor is formed in a ring shape has been developed (1
989 VLSI Symposium P. 69-70).
By thus forming the storage node for a capacitor in a ring shape, it is possible to increase the area forming the capacitor of the storage node and form a capacitor having a large storage capacity with a small cell area on the semiconductor substrate.

[0003]

However, when such a semiconductor device is manufactured by the conventional manufacturing method, additional CVD or RIE is required as compared with the case where the capacitor storage node is not formed in a ring shape. Therefore, there is a problem that the number of manufacturing steps of the semiconductor device is increased. Therefore, the manufacturing cost increases, and it is difficult to manufacture a highly integrated and inexpensive semiconductor device. The present invention has been made in view of such problems of the conventional technology, and an object thereof is to mold a fine ring-shaped storage node without causing a significant increase in the number of steps as compared with the conventional process. An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having a large-capacity capacitor at low cost.

[0004]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention performs exposure using an exposure reticle with a shifter having a transmitted light phase inversion portion of a predetermined pattern, The storage node forming fine pattern is formed in a pattern corresponding to the boundary between the transmitted light phase inversion portion and the other portion.

[0005]

In the method of manufacturing a semiconductor device of the present invention, since the exposure reticle with the shifter is used for the exposure, the phase of the exposure light passing through the transmitted light phase inversion portion is the same as that of the exposure light passing through the other portion. Since they are inverted with respect to the phase of light, light interference occurs at these boundaries and cancel each other out, and only the boundaries are shielded. As a result, a fine pattern corresponding to the boundary portion can be transferred to a resist or the like, and the fine pattern accumulating node can be formed using this fine pattern. The line width of the fine pattern can be adjusted by changing the exposure amount of the stepper. For example, even a line stepper can process a line width of about 0.15 μm, which exceeds the normal resolution limit.

By using such a method, a ring-shaped storage node can be easily obtained without significantly increasing the number of steps as compared with the conventional steps, and the area constituting the capacitor of the storage node is increased. be able to. Therefore, an increase in manufacturing cost can be prevented, and a highly integrated and inexpensive semiconductor device can be manufactured.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, in this embodiment, first, an element isolation region 5 is formed in a predetermined pattern on the surface of a semiconductor substrate 4 made of single crystal silicon or the like by a LOCOS method or the like, and the element isolation region 5 is formed. A gate oxide film 18 is formed on the surface of the semiconductor substrate 4 between the layers 5 by a thermal oxidation method or the like. After that, word lines 7a and 7b which also serve as gate electrodes are formed on the gate oxide film 9 in a predetermined pattern. The word lines 7a and 7b are made of, for example, a polysilicon film formed by a CVD method, and are doped with impurities such as phosphorus to enhance conductivity.

An interlayer insulating layer 8 is laminated on the word lines 7a and 7b. The interlayer insulating layer 8 is composed of, for example, a silicon oxide film formed by a CVD method. A bit line contact hole is opened in the interlayer insulating layer 8, and the bit line 6 is formed in a predetermined pattern on the interlayer insulating layer 8 so as to enter the contact hole.

As shown in FIG. 2, an interlayer insulating layer 11 is formed on the surface of the bit line 6. The interlayer insulating layer 11 is composed of, for example, a silicon oxide film formed by a CVD method. The surface of the interlayer insulating layer 11 is flattened. Contact holes 10 facing the surface of the semiconductor substrate 4 are formed in the interlayer insulating layers 11 and 8.

Next, as shown in FIG. 3, a conductive layer 12 for forming a storage node is laminated so as to enter the contact hole 10. The conductive layer 12 is, for example, CV
It is composed of a polysilicon film formed by the D method. The thickness of this polysilicon film is not particularly limited, but is about 600 nm, for example. The polysilicon film that has entered the contact hole 10 becomes the conductive plug 12b. A resist film 14 is formed on the surface of the conductive layer 12,
This is pattern processed into a processing pattern of the storage node.

In this embodiment, when patterning the resist film 14, an exposure reticle 40 with a shifter as shown in FIG. 6A is used. This exposure reticle 40 has
The transmitted light phase inversion portion 42 is formed in a predetermined pattern. The transmitted light phase inversion portion 42 can be formed by changing the thickness of the transparent plate that constitutes the exposure reticle 40 as compared with other portions. For example, a portion corresponding to the transmitted light phase inversion portion 42 and having a thicker plate thickness may be formed by other portions.

By using such a reticle 40,
As shown in FIG. 6B, the resist film 14 can be patterned into a ring shape with a fine pattern corresponding to the boundary between the transmitted light phase inversion portion 42 and other portions. The pattern width of this fine pattern can be adjusted by changing the exposure amount. For example, even an i-line stepper can process a line width of about 0.15 μm, which exceeds the normal resolution limit.

The reason why such a fine pattern can be formed can be explained as follows. That is, if the exposure reticle 40 with a shifter is used, the exposure light passing through the transmitted light phase inversion portion is inverted with respect to the phase of the light passing through the other portions, and therefore, at the boundary portion between them, This is because the interference of light causes a portion that becomes a shadow of light.
This shaded portion corresponds to a fine pattern.

Next, as shown in FIG. 4, the conductive layer 12 is patterned by an etching means such as RIE using a predetermined pattern 14 to obtain a storage node 12a in the form of a fine ring. Note that in FIG. 4, the storage node 12a and the conductive plug 12b do not seem to be connected, but in reality, as shown in FIG. 7, one side of the square ring-shaped storage node 12a becomes the conductive plug 12b. It is designed to connect to each other. That is, the square ring-shaped storage node 12a has a conductive plug 12b on each side.
They are arranged in a matrix in a pattern that connects the above.

Next, as shown in FIG. 5, the insulating thin film layer 15 for capacitors is laminated, and then the cell plate layer 16 for capacitors is laminated by the CVD method or the like, whereby the DRAM memory cell 2 is obtained. The insulating thin film layer 15 for capacitors is
The insulating film is not particularly limited as long as it is insulative, but is composed of, for example, a laminated film of a silicon oxide thin film and a silicon nitride thin film. The capacitor cell plate layer 16 is not particularly limited as long as it has conductivity, but is made of, for example, polysilicon.

The DRAM memory cell 2 manufactured through the above steps has a ring-shaped storage node 12a,
Since the inner and outer walls are used as the capacitor surface, a large storage capacity can be obtained. Moreover, as compared with the conventional process, since only the reticle needs to be changed, the manufacturing process and the manufacturing cost hardly increase.

A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 8, in the same process as in the above-described first embodiment,
After forming the word lines 7a and 7b and the bit line 6 on the semiconductor substrate 4, an interlayer insulating layer 11 'made of SiO ₂ or the like is formed on the surface of the bit line 6 by the CVD method or the like, and the surface thereof is formed. Flatten. Then, an etching stopper layer 22 that also functions as a second interlayer insulating layer is formed on the surface thereof. The etching stopper layer 22 is made of, for example, a silicon nitride film formed by a CVD method, and functions as an etching stopper for protecting a lower layer when the dummy layer 26 described later is etched. Etching stopper layer 22
Further, the contact hole 10 facing the surface of the semiconductor substrate 4 is formed in the interlayer insulating layers 8 and 11 '. Next, a conductive layer 24 for forming a part of the storage node and a conductive plug is laminated on the surface of the etching stopper layer 22 so as to enter the contact hole 10. The conductive layer 24 is composed of, for example, a polysilicon film formed by the CVD method. The film thickness is not particularly limited,
For example, it is about 100 nm.

Next, as shown in FIG. 9, a dummy layer 26 is laminated on the surface of the conductive layer 24. The dummy layer 26 is made of a material having an etching rate different from that of the etching stopper layer 24, for example, a silicon oxide film formed by the CVD method. The film thickness is not particularly limited, but is 600 nm, for example.

In this embodiment, the dummy layer 26 is finely processed into a ring-shaped fine pattern by the exposure reticle 40 shown in FIG. 6A used in the above-mentioned embodiment. This fine pattern becomes a dummy pattern of the storage node.

Next, in this embodiment, as shown in FIG. 10, a conductive layer for forming a double ring-shaped storage node is laminated on the dummy layer 26 having a predetermined pattern. The conductive layer is formed of, for example, a polysilicon film formed by the CVD method, and the film thickness thereof is not particularly limited, but is about 100 nm, for example. This polysilicon film is RI
It is etched back by anisotropic etching such as E.
As a result, the sidewall 2 is formed on the side of the dummy layer 26.
8 is formed. At the same time, the lower conductive layer 24 is also etched, so that the sidewall 28 and the dummy layer 26 are formed.
Bottom wall portion 24 of the storage node in a predetermined pattern only in the layer immediately below
b is formed. Note that in FIG. 10, the storage node bottom wall portion 24b and the conductive plug 24a appear to be cut, but in reality, as seen from the plane side, these are not connected as in the above-described embodiment. There is.

Next, the dummy layer 2 is treated with hydrofluoric acid or the like.
If 6 is removed, as shown in FIG. 11, a double ring-shaped storage node 30 composed of the sidewalls 28, 28 and the storage node bottom wall portion 24b can be formed. After that, if the insulating thin film layer for capacitors and the cell plate layer for capacitors are laminated in the same manner as in the above embodiment, D
The RAM memory cell 20 is obtained.

In this embodiment, the storage node is formed in a double ring shape, and the inner circumference and the outer circumference of each of the storage nodes form a capacitor. Therefore, the storage capacity can be further increased as compared with the first embodiment. Becomes Therefore, future 256MD
It is possible to cope with miniaturization at the time of forming a RAM or the like and reduction in voltage such as 1.5V.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, the method of manufacturing a semiconductor device according to the present invention is not used only for DRAM, but for example DR
It can be used for a method of manufacturing other semiconductor devices having storage nodes, such as ASIC devices having AM.

[0024]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a ring-shaped storage node can be easily obtained without significantly increasing the number of steps as compared with the conventional steps. The area of the storage node capacitor can be increased. Therefore, an increase in manufacturing cost can be prevented, and a highly integrated and inexpensive semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a method of manufacturing a DRAM according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

FIG. 3 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

FIG. 6 is a plan view of an exposure reticle used in the same example and a fine pattern view obtained using the reticle.

FIG. 7 is a plan view showing a pattern of storage nodes obtained by the manufacturing method according to the embodiment.

FIG. 8 is a schematic cross sectional view showing the method of manufacturing the DRAM according to the second embodiment of the present embodiment.

FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the DRAM according to the embodiment.

[Explanation of symbols]

 2, 20 DRAM memory cell 4 Semiconductor substrate 6 Bit line 7a, 7b Word line 8, 11, 11 'Interlayer insulating layer 9 Gate oxide film 10 Contact hole 12 Conductive layer 12a Storage node 12b Conductive plug 14 Resist film 15 For capacitor Insulating thin film layer 16 Cell plate layer for capacitor 22 Etching stopper layer 24 Conductive layer 24a Conductive plug 24b Storage node bottom wall portion 26 Dummy layer 28 Sidewall 30 Storage node 40 Exposure reticle 42 Transmitted light phase inversion portion

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 C 8427-4M 7352-4M H01L 21/30 311 W

Claims (4)

[Claims] 1. An exposure reticle having a shifter having a predetermined pattern of transmitted light phase inversion is used for exposure,
A method for manufacturing a semiconductor device, comprising forming a storage node forming fine pattern in a pattern corresponding to a boundary between the transmitted light phase inversion portion and the other portion. 2. A conductive layer serving as a storage node for a capacitor is stacked above a semiconductor substrate, a resist film is formed on the surface of the conductive layer, and the resist film is formed using the exposure reticle with a shifter. 2. The ring-shaped capacitor storage node is formed by processing by exposure to form a ring-shaped pattern, and by using the resist film as a mask to etch the conductive layer. Method of manufacturing semiconductor device. 3. An interlayer insulating layer is stacked above a semiconductor substrate, a conductive layer serving as a storage node for a capacitor is stacked on the surface of the interlayer insulating layer, and a dummy layer is stacked on the surface of the conductive layer. The dummy layer is processed into a ring-shaped pattern by exposure using the exposure reticle with the shifter,
The present invention is characterized in that conductive sidewalls are formed on the inner circumference and the outer circumference of the ring-shaped dummy layer, and then the dummy layer is removed by etching to form a storage node for a double ring-shaped capacitor. The method for manufacturing a semiconductor device according to claim 1. 4. A plurality of storage nodes for capacitors are formed above the semiconductor substrate in a matrix so as to be connected to the conductive plug layers located therebelow. A method of manufacturing a semiconductor device according to claim 3 or 4.