JP2973495B2 - Method for manufacturing semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor memory, which is called a DRAM and has a memory cell composed of a transistor and a capacitor.

[Summary of the Invention]

According to a first aspect of the present invention, in the method of manufacturing a semiconductor memory as described above, a highly integrated semiconductor memory is manufactured by patterning a gate electrode of a transistor in a pattern of an overlapping portion of the first and second masks. It is something that can be done.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor memory as described above, the storage node of the capacitor connected to the impurity diffusion layer of the transistor through the contact hole formed in the spacer film and the insulating film is formed on the spacer film. After forming and removing the spacer film, the dielectric film and the plate electrode of the capacitor are formed, so that a highly integrated semiconductor memory can be manufactured.

[Conventional technology]

FIG. 7 shows a memory cell in a stacked capacitance type DRAM manufactured according to a conventional example of the present invention. In this memory cell, the gate electrode 14 of the transistor 13 crosses the element forming region 12 surrounded by the LOCOS film 11.

Bit holes and storage node contact holes 17 and 18 are provided for one and the other impurity diffusion layers 15 and 16 of the gate electrode 14, respectively. The gate electrodes 21 and 22
Is for a memory cell adjacent in the direction in which the gate electrode 14 extends.

By the way, the direction in which the bit line (not shown) extends, that is, the direction perpendicular to the direction in which the gate electrode 14 extends, is the long side direction of the memory cell. Size
It is the sum of a ₁ Ea ₈ .

Here, a ₁ is _1/2 of the diameter of the contact hole 17, a ₂ is the distance between the contact hole 17 and the gate electrode 14, and a ₃ is the gate electrode
Gate length of 14, a ₄ is the distance between the gate electrode 14 and the contact hole 18, the diameter of a ₅ the contact hole 18, a ₆ denotes a contact hole
The distance between 18 and the gate electrode 21, a ₇ is the wiring width of the gate electrode 21, and a ₈ is 1/2 of the wiring distance between the gate electrodes 21 and 22.

Therefore, the only way to reduce the memory cell area by shortening the long side of the memory cell is to reduce each of the dimensions a _i .

[Problems to be solved by the invention]

However, the dimensions a _i cannot be made smaller than a certain value due to lithographic limitations. For this reason, in the above-described conventional example, it was difficult to manufacture a semiconductor memory with a high degree of integration.

[Means for solving the problem]

In the method of manufacturing a semiconductor memory according to the first invention of the present application, a first mask 23 which branches on a memory cell so as to pass over each of the memory cells and is integrated at a boundary region between the memory cells is provided. A step of preparing; and a step of preparing a second mask 24 having an opening 24a in the boundary region having a width smaller than the width of the first mask 23 in the boundary region and overlapping the first mask 23, Patterning the gate electrodes 14, 21, 22 of the transistor 13 in the pattern of the overlapping portion of the first and second masks 23, 24, respectively.

The method of manufacturing a semiconductor memory according to the second invention of the present application includes the steps of: laminating insulating films 31 to 33 and a spacer film 35 on the impurity diffusion layer 16 of the transistor 13; Forming a hole in the spacer film 35 and the insulating films 31 to 33; and forming a first conductive film 37 connected to the impurity diffusion layer 16 through the contact hole 36 and having a storage node pattern of the capacitor 43. Forming the first conductive film 37 on the spacer film 35, removing the spacer film 35 after forming the first conductive film 37, and removing the spacer film 35 on the surface of the first conductive film 37. A step of forming a dielectric film 41 and a step of forming a second conductive film 42 facing the first conductive film 37 via the dielectric film 41 and having a pattern of a plate electrode of the capacitive element 43 Respectively.

[Action]

In the method for manufacturing a semiconductor memory according to the first invention of the present application,
On the memory cells, the first mask 23 branches so as to pass over each memory cell, and in the boundary region between the memory cells, the width is smaller than the width of the integrated first mask 23. The opening 24a of the second mask 24 overlaps with the first mask 23. Therefore, it is possible to pattern the gate electrodes 21 and 22 that are separated from the adjacent gate electrodes 22 and 21 but extend one at a time.

In the boundary region between the memory cells, the remaining half obtained by subtracting the width of the opening 24a of the second mask 24 from the width of the first mask 23 becomes the width of one gate electrode 21, 22. The gate electrodes 14, 21, 22 are not patterned with a single mask. Accordingly, the wiring width a ₇ of the gate electrodes 21 and 22 in the boundary region can be thin without being limited to the limit of lithography.

In the method for manufacturing a semiconductor memory according to the second invention of the present application,
After forming a first conductive film 37 as a storage node of the capacitor 43 on the spacer film 35 and removing the spacer film 35, a second conductive film 42 as a plate electrode of the dielectric film 41 and the capacitor 43 is formed. To form Therefore, the hollow portion formed by removing the spacer film 35 also becomes a part of the capacitor 43, so that the capacitor 43 having a large capacity for the memory cell area can be formed.

[Implementation]

Hereinafter, the first aspect of the present invention applied to the manufacture of a stacked capacitance type DRAM will be described.
The fourth to fourth embodiments will be described with reference to FIG. 1 to FIG.

FIG. 1 shows a first embodiment. Also in the first embodiment, as shown in FIG. 1A, a LOCOS film 11 is formed on the surface of a Si substrate, and a region surrounded by the LOCOS film 11 is an element forming region 1.
2, and until a polycrystalline Si film or a polycide film, which is a wiring material for the gate electrode, and a resist film are sequentially laminated, a conventionally known method is used.

In the first embodiment, the first exposure of the resist film is performed using the mask 23 thereafter.

The mask 23 is branched so as to pass over each memory cell on the memory cell, but is integrated on the LOCOS film 12, that is, in a boundary region between the memory cells.

That is, the mask 23 corresponds to the gate electrode 14 shown in FIG. 7, but the gate electrodes 21 and 22 have a pattern in which they are integrated.

After that, a second exposure of the resist film is performed using the mask 24.

The mask 24 has an opening 24a that connects the boundary regions between the memory cells in the extending direction of the gate electrode to be patterned and extends so as to overlap the mask 23 in the boundary region.
have. The width of the opening 24a is smaller than the width of the mask 23 in the boundary region between the memory cells.

After that, the resist film is developed, and a portion that is not exposed by any of the first and second exposures, that is, the mask 2
3. Leave the overlapping part of 24. Therefore, the developed resist film is separated at the boundary region between the memory cells.

Next, using the resist film patterned in this manner as a mask, the wiring material of the gate electrode is etched to pattern the gate electrodes 14, 21, 22 and the like as shown in FIG. 1B.

In the first embodiment, such as described above, in the first 1B 1 single lithography part of the dimension a ₇ in Figure because not formed, it is possible to narrow the dimension a ₇ below limit of lithography.

For example, the resolution limit by the reduced projection exposure apparatus using g-line is line and space = 0.45 / 045 μm,
Dimensions a ₇ in FIG even can not be thinner than this value.

However, if it is sufficient that the wiring width of the gate electrode is 0.1 μm at the minimum, the misalignment margin of the masks 23 and 24 is set to 0.
Even considering the 2 [mu] m, the dimensions a ₇ in Figure 1B can be thinned to 0.3 [mu] m.

Therefore, in the first embodiment, the long side of the memory cell can be shortened by 0.15 μm as compared with the case of FIG. On the other hand, the length of the long side of the memory cell is currently 3 to
Since it is about 3.5 μm, the long side is reduced by about 5%.

In the first embodiment, double exposure is performed on a single resist film. For each exposure, development of the resist film and patterning of the wiring material of the gate electrode are performed. Is also good.

In such a method, the number of steps is increased, but the mask 24 at the time of the second exposure can be aligned with the wiring material after the first patterning. Therefore, the margin for misalignment may be 0.15 μm, and the long side of the memory cell can be further reduced by 0.05 μm.

FIG. 2 and FIG. 3 show a second embodiment according to such a method. Also in the second embodiment, as shown in FIGS. 2A and 3A, a LOCOS film 11 and an element formation region 12 are formed on a Si substrate 25, and a wiring material 26 for a gate electrode and a resist film 27 are formed.
The resist film 27 is sequentially laminated on the Si substrate 25, and the resist film 27 is exposed using a mask having substantially the same pattern as the mask 23 of the first embodiment.

However, in the second embodiment, the resist film 27 is developed immediately thereafter, and the wiring material 26 is etched using the resist film 27 as a mask.

By this etching, a portion of the gate electrode on the element forming region 12, that is, the gate electrode 14 shown in FIG. 7 is patterned.
The upper part, that is, the gate electrodes 21 and 22 shown in FIG. 7 are integrated.

Next, as shown in FIGS. 2B and 3B, the resist film 27 is removed, another resist film 28 is applied, and the resist film 28 is patterned using a mask having a pattern similar to the mask 24 of the first embodiment. Is exposed.

However, the mask used at this time in the second embodiment has an opening only on the LOCOS film 11 in the boundary region between the memory cells. Therefore, even if the resist film 28 is subsequently developed, the resist film 28 also has an opening 2 on the LOCOS film 11.
8a is not formed.

Next, by etching the wiring material 26 using the resist film 28 as a mask, the gate electrodes 21 and 22 are separated from each other as shown in FIGS. 2C and 3C.

In the second embodiment, such as described above, as in the first embodiment described above, it is possible to thin the first 2C view and dimensions a ₇ in Figure 3C below limit of lithography. In the second embodiment, since the opening 28a is formed only on the thick LOCOS film 11, the thin gate oxide film on the element forming region 12 is not affected by the etching using the resist film 28 as a mask.

FIG. 4 and FIG. 5 show a third embodiment. Also in the third embodiment, as shown in FIG. 4A, the gate electrodes 14, 22
Patterning and the formation of the impurity diffusion layers 15 and 16
This is performed by a conventionally known method.

After that, a PSG film 31 with a thickness of about 1000 mm and 200-300 mm
SiN film 32 with a thickness of about 20 mm and SiO ₂ film 33 with a thickness of 2000 mm or more.
Is formed.

Then, a polycrystalline Si film having a thickness of about several thousand degrees is deposited, and an opening a is formed in a portion of the polycrystalline Si film on the impurity diffusion layer 16.

Further, a side wall made of a SiO ₂ film 35 is formed in the opening 34a, and a contact hole 36 reaching the impurity diffusion layer 16 is opened, and a polycrystalline Si film 37 is connected to the impurity diffusion layer 16 through the contact hole 36. Let it.

Next, as shown in FIGS. 4B and 5, the resist film 38 is patterned into a pattern of a storage node, and the resist film 38 is used as a mask to form polycrystalline Si until the SiO ₂ film 35 is exposed.
RIE is performed on the film 37.

After that, with the resist film 38 remaining, the SiO ₂ film 35 is etched off with hydrofluoric acid, and the donut-shaped portion where the SiO ₂ film 35 was present is made hollow.

Next, as shown in FIG. 4C, the polycrystalline Si films 37 and 34 are etched using the resist film 38 as a mask, and these polycrystalline Si films 37 and 34 are etched.
Dielectric film on the inner surface of 34 and 37, that is, the above-mentioned intermediate part and outer surface
Form 41.

Then, by patterning the polycrystalline Si film 42 into a plate electrode pattern and filling the donut-shaped hollow portion with the polycrystalline Si film 42, the capacitive element 43 constituting the memory cell is formed.

In the third embodiment as described above, the donut-shaped hollow portion formed by etching off the SiO ₂ film 35 is also a part of the capacitance element 43. Therefore, the capacitance element 43 has a smaller area than the memory cell area. Large capacity and easy integration.

By the way, when a storage node is made three-dimensional for high integration of a stacked capacitance type DRAM, a step becomes severe.

Therefore, as shown in FIG. 8, the same polycrystalline Si film 37 as the storage node is also provided on impurity diffusion layer 15 for connecting the bit line.
Is a dielectric film on the polycrystalline Si film 37 or the like.
By depositing the SiN film 44 and filling the grooves between the polycrystalline Si films 37 with the polycrystalline Si film 42 as a plate electrode, the processing in the subsequent process is facilitated.

However, in this structure, the polycrystalline Si film 37 on the impurity diffusion layer 15 and the polycrystalline
Since only a thin SiN film 44 exists between itself and the Si film 42, the capacitance between the bit line and the plate electrode is extremely large.

Moreover, since the SiN film 44 is thin, the polycrystalline Si film 37 on the impurity diffusion layer 15 is also etched when the polycrystalline Si film 42 is etched.

FIG. 6 shows a fourth embodiment for solving such a problem. Also in this fourth embodiment, the polycrystalline Si film 37 is patterned as shown in FIG.
Until the N film 44 is deposited, the steps are substantially the same as those in the conventional example shown in FIG.

Next, as shown in FIG. 6B, an opening 45 is formed on the impurity diffusion layer 15.
The resist film 45 is patterned to have a, and the SiN film 44 in a region other than the capacitive element 43 is removed by isotropic etching using SF ₆ or the like using the resist film 45 as a mask.

Next, after removing the resist film 45, pyrogenic oxidation is performed. Then, the surface of the SiN film 44 is oxidized, the withstand voltage of the SiN film 44 is improved, and as shown in FIG. 6C, the surface of the polycrystalline Si film 37 on the impurity diffusion layer 15 has a thick SiO 2 _{The two} films 46 grow.

Thereafter, as in the case of the conventional example shown in FIG.
The grooves between the polycrystalline Si films 37 are filled with the polycrystalline Si film 42 for the plate electrode, and planarization is performed.

In the fourth embodiment as described above, since the thick SiO ₂ film 46 is formed on the surface of the polycrystalline Si film 37 on the impurity diffusion layer 15, the capacitance between the bit line and the plate electrode is reduced, and The planarization by the polycrystalline Si film 42 can be achieved while preventing the polycrystalline Si film 37 on the impurity diffusion layer 15 from being etched.

〔The invention's effect〕

In the method for manufacturing a semiconductor memory according to the first invention of the present application,
Since the wiring width of the gate electrode in the boundary region between the memory cells can be reduced without being limited by the limit of lithography, the memory cell area can be reduced and a highly integrated semiconductor memory can be manufactured.

In the method for manufacturing a semiconductor memory according to the second invention of the present application,
Since a capacitor with a large capacity can be formed for the memory cell area, the memory cell area can be reduced and a highly integrated semiconductor memory can be manufactured.

[Brief description of the drawings]

1 and 2 are plan views sequentially showing a first and a second embodiment of the present invention, respectively. FIG. 3 is a side sectional view taken along the line III-III of FIG. 2, and FIG. Side sectional view sequentially showing the embodiment,
FIG. 5 is a side sectional view taken along line VV in FIG. 4B, and FIG. 6 is a side sectional view sequentially showing the fourth embodiment. FIG. 7 is a plan view of a semiconductor memory manufactured by one conventional example of the present invention, and FIG. 8 is a side sectional view of a semiconductor memory manufactured by another conventional example. In the reference numerals used in the drawings, 13 ... transistors 14,21,22 ... gate electrodes 23,24 ... mask 24a ... openings 43 ... capacitance elements.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242 H01L 27/04 H01L 21/822

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor memory in which a memory cell is composed of a transistor and a capacitor, wherein the memory cell is branched so as to pass over each of the memory cells and a boundary between the memory cells. Preparing a first mask integrated in the region; and a second region having an opening overlapping the first mask with a width smaller than the width of the first mask in the boundary region. And a step of patterning the gate electrode of the transistor in a pattern of an overlapping portion of the first and second masks. 2. A method of manufacturing a semiconductor memory in which a memory cell is composed of a transistor and a capacitor, wherein: a step of stacking an insulating film and a spacer film on an impurity diffusion layer of the transistor; Forming a contact hole that reaches the spacer film and the insulating film; connecting the first conductive film having a pattern of a storage node of the capacitor element to the impurity diffusion layer through the contact hole; Forming on the film, removing the spacer film after forming the first conductive film, and forming a dielectric film on the surface of the first conductive film after removing the spacer film A second electrode facing the first conductive film via the dielectric film and having a pattern of a plate electrode of the capacitive element;
And a step of forming a conductive film.