JPH0677430A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having sufficient capacitance by using capacitor electrodes in the shape of a dual elliptical cylinder, which are formed according to the same layout rule and in the same number of process steps of the conventional method. CONSTITUTION:Minute annular grooves are formed by phase shifting of negative photoresist. The grooves are used to form capacitor electrodes 115 of phosphorus-doped polysilicon in the shape of a dual elliptical cylinder. Such capacitor electrodes are capable of providing capacitance equivalent to STC cells. This process for capacitor electrodes, considerably simplified, prevents electrodes from peeling, and thus improving yield.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a stacked capacitor cell (S
The present invention relates to a semiconductor device having a storage electrode of a TC cell) and a manufacturing method thereof.

[0002]

2. Description of the Related Art The degree of integration of semiconductor LSIs has been increasing year by year, and in particular in the field of MOSLSI DRAMs (dynamic random access memories), there are already 6
A 4-megabit DRAM is the subject of development. 64
In order to realize a DRAM of megabits or later, one cell has a very small area of about 0.7 to 1.5 μm ² and a certain amount of capacitor capacity, that is, the capacity required to maintain reliability. Must be secured.

As one countermeasure, a so-called crown type STC cell has been proposed which can obtain a large storage capacity even with a fine cell area (Japanese Patent Laid-Open No. 2-226761). The feature of this cell is that the storage electrode has an elliptic cylindrical shape (the cross section is a crown type),
The point is that the region in contact with the side wall is the capacitance region.
A method of manufacturing this crown type STC cell will be described with reference to FIGS. 10 to 14.

First, after forming an element isolation region 202 on a p-type Si single crystal substrate 201, an 8 nm gate insulating film 203, a 200 nm gate electrode 204 and a diffusion layer 20 are formed.
A switching MOS transistor composed of 5 (a) and 5 (b) is formed. Then, the gate electrode 204 is formed on the insulating film 206.
Then, an opening is provided so that the diffusion layers 205 (a) and (b) of the switching transistor are exposed after being electrically insulated. Then, a 500 nm phosphorus-doped polycrystalline Si film 207 is deposited by LP (low pressure) -CVD method (chemical vapor deposition method) and then etched back to leave the polycrystalline Si film 207 in the groove above the diffusion layer (see FIG. 10).

Next, after forming the bit line 208, a SiO ₂ film 209 covering the bit line 208 is formed by the CVD method,
Isolate electrically. Subsequently, a Si ₃ N ₄ film 210 of about 100 nm and a Si ₂ O film 211 of about 500 nm are sequentially deposited by the LP-CVD method (FIG. 11).

Next, using the photoresist 212 patterned into a predetermined shape as a mask, the SiO ₂ film 21 is formed.
1 and the Si ₃ N ₄ film 210 are etched to form a diffusion layer 205.
(B) A frame of an insulating film (SiO ₂ film 211, Si ₃ N ₄ film 210) surrounding the upper phosphorus-doped polycrystalline Si film 207 is formed. At this time, at the same time, the surface of the phosphorus-doped polycrystalline Si film 207 connected to the diffusion layer 205 (b) is exposed (FIG. 12 (c)). Here, as shown in FIG. 12A, the resist pattern was formed with an i-line having a wavelength of 365 nm by using a reticle in which shifter films are alternately placed in the transmissive portions between the patterns of the chrome film. A positive resist was used as the photoresist, and a pattern in which the distance between adjacent hole patterns was 0.3 μm was formed (FIG. 12).
(B)).

Subsequently, the photoresist 212 is removed, and the LP-
A phosphorus-doped polycrystalline Si film to be the storage electrode 213 is formed to a thickness of about 80 nm by the CVD method. Next, an insulating film (SiO ₂
After depositing a SiO ₂ film 214 with a film thickness that sufficiently fills the groove portion in the frame of the film 211 and the Si ₃ N ₄ film 210) by the CVD method,
The SiO ₂ film 214 is etched back by dry etching to fill only the groove with the SiO ₂ film 214. Then, an insulating film (SiO ₂ film 2
11 and the Si ₃ N ₄ film 210) and the exposed phosphorus-doped polycrystalline Si film 213 are removed (FIG. 13).

Next, the SiO ₂ film 2 which has buried the inside of the groove
14 and the Si ₂ O film 211 forming the frame of the insulating film are removed with an aqueous solution of hydrofluoric acid to form an elliptic cylindrical storage electrode 213 (FIG. 14). After that, the capacitive insulating film, the plate electrode and the predetermined wiring are formed, and the manufacturing of the crown type STC cell is completed. By thus forming the storage electrode 213 in an elliptic cylindrical shape, a large storage capacity can be secured.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above,
In order to realize a 64-megabit or later DRAM with a crown-type STC cell using the current technology, (1) the height of the elliptic cylindrical storage electrode should be suppressed to about 0.5 μm, and 2 in terms of Si oxide film.
A Ta ₂ O ₅ (tantalum pentaoxide) film of about 3 nm is used as a capacitive insulating film, or (2) the height of the elliptic cylindrical storage electrode is increased to about 0.8 μm and converted to a Si oxide film of 4 to 4 nm.
Two methods of using a SiO ₂ / Si ₃ N ₄ laminated film having a thickness of about 4.5 nm are considered promising.

However, when the Ta ₂ O ₅ film is used, there are problems that the film can be made thin, but the forming method is complicated, and that the plate electrode material must be a metal. On the other hand, when a laminated film of SiO ₂ and Si ₃ N ₄ is used, a polycrystalline Si plate that has been used conventionally can be applied, but it cannot be thinned, so a higher storage electrode is required. However, if the storage electrode is raised, problems such as poor resolution in the lithography process and disconnection and short circuit in the dry etching process become apparent.

As one countermeasure, as shown in FIG.
A storage ellipsoidal cylindrical storage electrode has been proposed. Note that FIG.
Shows a cross section in the word line direction. If this double elliptic cylindrical storage electrode is used, a sufficient capacity can be secured by the SiO ₂ / Si ₃ N ₄ laminated film even if the electrode height is about 0.5 μm.
However, in the conventional method, since the outer peripheral portion and the inner peripheral portion of the storage electrode are individually formed, the method of forming the storage electrode is complicated, and the contact area between the inner peripheral portion and the outer peripheral portion is very large. Since it is small, the adhesive strength is weak and there is a problem such as peeling in the washing process. Further, when forming the side wall of the SiO ₂ film that serves as a partition for forming the inner peripheral portion, a large overetch is required because the etching rate of the groove bottom decreases. As a result, the height of the partition of the SiO ₂ film is lowered and the storage capacitance is reduced.

An object of the present invention is to provide a semiconductor device which can obtain a large storage capacitance in a fine plane area and a manufacturing method capable of manufacturing the semiconductor device with a high yield.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention comprises a storage electrode comprising a double cylindrical outer peripheral portion, an inner peripheral portion and a bottom portion connecting the lower portions thereof. An outer peripheral portion, an inner peripheral portion, and a bottom portion of a semiconductor element formed of a transistor are formed in the same layer.

The cylindrical shape may be any shape such as a circular cross section, an elliptical shape, a modified circular shape or an elliptical shape, and a part thereof may have a straight line portion. Also,
It is preferable that the distance between the upper ends of the pair of the outer peripheral portion and the inner peripheral portion appearing in a desired vertical section of the storage electrode is substantially the same. Further, it is preferable that the distance between the outer peripheral portion and the inner peripheral portion of the storage electrode is in the range of 0.1 μm to 0.3 μm. Further, it is preferable that the upper ends of the outer peripheral portion and the inner peripheral portion of the storage electrode are substantially at the same height.

In the semiconductor device of the present invention, the wall-shaped structure of the outer peripheral portion formed so as to surround a desired region, the wall-shaped structure of the inner peripheral portion formed inside the wall-shaped structure, and the bottom portion connecting the lower portions thereof are provided. The outer wall and the inner wall of the semiconductor element including the storage electrode and the transistor are formed so that the wall-shaped structure and the bottom are in the same layer. In this case as well, the interval between the upper ends of the pair of the outer peripheral wall-shaped structure and the inner peripheral wall-shaped structure appearing in the desired vertical section of the storage electrode is substantially the same, and the interval is 0. It is preferable that the thickness is in the range of 1 μm to 0.3 μm, and the upper ends of the wall-shaped structure on the outer peripheral portion and the wall-shaped structure on the inner peripheral portion of the storage electrode are substantially at the same height.

In such a semiconductor device, a film of a material having an etching rate higher than that of the material forming the storage electrode is formed on at least the upper portion of the substrate, an annular groove is formed in the film, and an outer peripheral portion of the groove is formed. It can be manufactured by forming a continuous film of a conductive material on the wall surface and the bottom of the inner peripheral portion and using this film of the conductive material as a storage electrode. In the step of forming the annular groove, the predetermined pattern portion changes the phase of light to 18
It is preferably formed by lithography and dry etching using a reticle formed only of a shifter film that is inverted by 0 degrees.

[0017]

As is well known, if the phase shift method of inverting the phase of light by 180 ° is used, it is possible to form a fine pattern with a wavelength of light or less. An example thereof is shown in FIG.
19 (a) and 19 (b) show the phase of light on the reticle substrate.
A plan view of a mask provided with a shifter pattern for inversion by 0 ° and its sectional view taken along line AA ', and FIGS. 19C and 19D are a plan view of a photoresist pattern obtained by using it and a sectional view taken along line BB' thereof. .

When a negative type photoresist is used, the light intensity at the edge portion of the shifter pattern becomes zero as shown in the figure, and therefore the photoresist at the portion where the light intensity is zero is removed. An annular groove hole pattern is formed, and an island pattern is formed inside the groove (FIGS. 19C and 19D). The annular groove width can be controlled to about 0.1 to 0.3 μm by selecting the wavelength (λ) of light, the numerical aperture (NA) of the lens and the exposure amount. The width of the island pattern can be adjusted by the width of the shifter pattern and the groove width.

Further, FIG. 20 shows a plan view and a sectional view of the patterns of two kinds of shifters. It is not necessary to form a light-shielding chromium film on the reticle substrate. Such a shifter pattern can be obtained by forming a shifter film on the entire surface and then (1) leaving the shifter film in a predetermined pattern size, or (2) removing only the shifter film having a pattern size. . In either case, a photoresist pattern having the same shape can be obtained.

22 to 24 show an example of the light intensity distribution by such a shifter pattern. 22 (b) and FIG.
3 (b) and FIG. 24 (b) show the layout of the shifter installed on the reticle, and FIG. 22 (a) (c) and FIG.
24A and 24C show simulation results of the light intensity distribution when the wavelength of light and the numerical aperture of the lens are used as parameters. The horizontal axis of the figure shows the cross-sectional position of the line AA 'in the layout figure, and the vertical axis shows the light intensity. Also, the broken line in the figure indicates the threshold value of the light intensity at which the photoresist is resolved. When the shifter width and the shifter interval are 0.4 μm, the i-line with the wavelength λ = 365 nm and the numerical aperture NA = 0.5
It is not possible to resolve with the lens No. 2, but it is possible to resolve with a lens with an NA of 0.55 or more (FIGS. 22 and 23). It is also understood that even if the shifter width and the shifter interval are 0.3 μm, resolution can be resolved by using a KrF excimer laser with a wavelength λ = 248 nm. in this way,
A fine annular groove can be formed by using the phase shift method.

Further, according to the present invention, since the double cylindrical outer peripheral portion and the inner peripheral portion can be formed in the same layer, the forming process is simple, and the mechanical strength of the storage electrode is strong, so that there is no problem such as peeling. Absent. Further, SiO ₂ which becomes a partition of the storage electrode in the inner peripheral portion
Since the side wall of the film is not formed, there is no problem that the height of the storage electrode in the inner peripheral portion is lowered.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the drawings.

<Embodiment 1> FIGS. 2 to 9 show the first embodiment of the present invention.
The manufacturing process of the semiconductor device of the embodiment is shown. First, an element isolation region 102 is formed on a P-type Si single crystal substrate 101 by a LOCOS method (a selective oxidation method of silicon), and then an 8 nm SiO ₂ film to be a gate insulating film 103 is formed by a wet oxidation method at 850 ° C. Form 103. Then L
A 200 nm phosphorus-doped polycrystalline Si film and a SiO ₂ film 105 to be the gate electrode 104 are sequentially formed by the P-CVD method. In the present embodiment, the phosphorus-doped polycrystalline Si described above is used.
The film was formed at a temperature of 580 ° C. using SiH ₄ gas and PH ₃ gas. Next, after the SiO ₂ film 105 and the phosphorus-doped polycrystalline Si film are processed into a predetermined shape by lithography and dry etching techniques, arsenic is ion-implanted into the diffusion layer 106 (a) (b) of the switching transistor. , 850 ° C., and N ₂ annealing for 15 minutes. Next, SiO 2 is formed on the side wall of the gate electrode 104 by the CVD method.
_{2 After the} film 107 is formed and electrically insulated, the surfaces of the diffusion layers 106 (a) and (b) of the transistor are exposed.
Then, the phosphorus-doped polycrystalline Si film 10 is formed by the LP-CVD method.
8 is deposited to a thickness of 500 nm, and the polycrystalline Si film 108 is etched back by a thickness of 250 nm by a dry etching method so as to be flattened (FIG. 2).

Next, a phosphorus-doped polycrystalline Si film of 150 nm and a SiO ₂ film 1 of 200 nm are formed by the LP-CVD method.
After 10 are sequentially deposited, they are processed into a predetermined shape to form the bit line 109. After that, the SiO ₂ film 111 is formed on the side wall of the bit line 109 by the CVD method and electrically insulated. Next, the Si ₃ N ₄ film 112 is formed by the LP-CVD method.
Of 100 nm and a SiO ₂ film 113 of 500 nm are sequentially deposited (FIG. 3).

Next, a photoresist pattern 114 having a fine ring-shaped space is formed by the phase shift method (FIG. 4C). A plan view of the reticle used in this embodiment is shown in FIG. 8 (a), and a sectional view thereof is shown in FIG. 8 (b). The shifter formed on the reticle has a long side of 1.1 μm and a short side of 0.
The distance between the shifters was 4 μm, and the distance between the shifters was 0.4 μm. For exposure, i-line with wavelength (λ) of 365 nm and numerical aperture (NA)
A 0.55 lens was used. FIG. 8C is a plan view of the photoresist pattern formed by the above method, and FIG.
It is shown in (d). As shown in the figure, the edge of the ring-shaped space was shifted to both sides by about 0.125 μm from the edge of the shifter, and a space of about 0.25 μm was obtained (FIG. 8 (c)). At this time, the length of the short side of the island pattern surrounded by the ring-shaped space is 0.4 times the length of the short side of the shifter.
It becomes about 0.15 μm, which is obtained by subtracting the space length from μm (FIGS. 8C and 8D).

In the present embodiment, the ring-shaped space length was set to 0.25 μm, but it was possible to control in the range of 0.2 μm to 0.3 μm by adjusting the exposure amount. Further, in the present embodiment, the distance between the shifters and the short side length of the shifters are set to 0.4 μm (FIGS. 8A and 8B), but a KrF excimer laser with a wavelength (λ) of 248 nm and a numerical aperture (N) are used.
A) If a lens of 0.5 was used together, pattern formation was possible even with 0.3 μm.

Returning to FIG. 4, the description will be continued. Using the ring-shaped resist as a mask, the SiO ₂ film 113, Si ₃ N ₄
The film 112 is sequentially etched by the dry etching method to expose the surface of the phosphorus-doped polycrystalline Si film 108 connected to the diffusion layer 106 (b) of the switching transistor. The exposed portion of the phosphorus-doped polycrystalline Si film 108 is shown in FIG.
It is at the position of the connection hole in (a) and is not shown in FIG. 4 (b).

Subsequently, after removing the photoresist pattern 114, the phosphorus-doped polycrystalline Si is diluted with a dilute aqueous solution of hydrofluoric acid.
The natural oxide film on the surface of 108 is removed, and a phosphorus-doped polycrystalline Si film to be the storage electrode 115 is deposited to a thickness of 80 nm. In this embodiment, the phosphorus-doped polycrystalline Si film is also formed
It was deposited at a temperature of 580 ° C. using SiH ₄ gas and PH ₃ gas. Next, the SiO ₂ film 116 is formed to 300 by the LP-CVD method.
nm is deposited to fill the groove between the phosphorus-doped polycrystalline Si films. After that, by anisotropic dry etching, SiO
_{2 The} film 116 is etched to expose the surface of the phosphorus-doped polycrystalline Si film on the insulating film (SiO ₂ film 113 and Si ₃ N ₄ film 112) forming the ring-shaped frame. Subsequently, the phosphorus-doped polycrystalline Si film having the exposed surface is etched by an anisotropic dry etching method to expose the surface of the SiO ₂ film 113 forming a part of the ring-shaped frame (FIG. 5). .

After that, the SiO ₂ film 113 forming a part of the ring-shaped frame and the SiO ₂ film 116 filling the inside of the groove are removed with a dilute hydrofluoric acid solution. SiO ₂ film 113
Since the underlying Si ₃ N ₄ film 112 and the phosphorus-doped polycrystalline Si film are hardly etched with a dilute hydrofluoric acid aqueous solution, the double elliptic cylindrical storage electrode 115 of the phosphorus-doped polycrystalline Si film as shown in the figure is formed. (Fig. 6).

According to this method, the phosphorus-doped polycrystalline Si film of the same layer exists at the bottom of the region sandwiched between the outer peripheral portion and the inner peripheral portion of the storage electrode 115, but the bottom portion inside the inner peripheral portion is phosphorus-doped polycrystalline. There is a Si ₃ N ₄ film 112 without the Si film. Therefore, the diffusion layer 106 of the switching transistor
The connection hole with the phosphorus-doped polycrystalline Si film 108 connected to (b) was set in a region sandwiched between the outer peripheral portion and the inner peripheral portion as shown in FIG.

Next, after removing the natural oxide film existing on the surface of the storage electrode 115 made of a phosphorus-doped polycrystalline Si film with a dilute hydrofluoric acid aqueous solution, the LP-C equipped with a load lock mechanism.
A 5 nm Si ₃ N ₄ film is deposited by a VD apparatus. In this example, SiH ₂ Cl ₂ gas and NH ₃ gas were used for depositing the Si ₃ N ₄ film, and the film was formed at a temperature of 600 ° C. Subsequently, the above Si was formed by a wet oxidation method at 850 ° C.
_{The 3} N ₄ film is oxidized by 1 nm to form an SiO ₂ / Si ₃ N ₄ laminated film having a Si oxide film equivalent film thickness of 5 nm, and the capacitive insulating film 117 is formed.
And Next, a phosphorus-doped polycrystalline Si film was deposited to a thickness of 150 nm by the LP-CVD method, and then processed into a predetermined shape by the lithography and dry etching methods to form the plate electrode 118. Thereafter, the surface of the interlayer insulating film 119 is flattened to form a predetermined wiring 120 connecting the peripheral circuit and the memory cell, and the preparation of the STC cell having the double elliptic cylindrical storage electrode 115 is completed (FIG. 7).

FIG. 1 is a perspective view of the state shown in FIG. However, the cross section is parallel to the word line. As shown, the storage electrode 115 has a double elliptic cylindrical shape.

The STC cell created in this embodiment is
The same storage capacity as that of the STC cell having the double elliptic cylindrical storage electrode produced by the conventional method was obtained. In addition, since the process of forming the storage electrode is greatly simplified and defects such as peeling of the storage electrode are eliminated, the manufacturing yield is dramatically improved.

<Second Embodiment> A second embodiment of the present invention will be described with reference to FIGS. The element isolation region 30 is formed on the P-type Si single crystal substrate 301 by the same procedure as in the first embodiment.
2 and the gate insulating film 303, the gate electrode 304, and the switching transistor composed of the diffusion layers 306 (a) and (b) and the SiO ₂ films 305 and 30 for insulating the gate electrode 304.
Form 7. Then, a phosphorus-doped polycrystalline Si film 308 having a thickness of 500 nm is deposited by the LP-CVD method, and then the phosphorus-doped polycrystalline Si film 308 is deposited by a dry etching method.
Etched back to 50 nm and on the diffusion layer 306 (a)
A phosphorus-doped polycrystalline Si 308 plug is formed in (b) (FIG. 15).

Then, a bit line 309 made of a phosphorus-doped polycrystalline Si film and a SiO ₂ film 310 for insulating the bit line 309,
311 is formed. At this time, the surface of the phosphorus-doped polycrystalline Si film 308 connected to the diffusion layer 306 (b) is exposed (the exposed portion is not shown). Then, the organic polymer film 3
After spin-coating 12 of 1 μm, the organic polymer film 312 is baked in a reduced pressure atmosphere at 600 ° C. to degas the film. Next, the organic polymer film 312 is patterned by a multi-layer resist process. That is, a silica glass film is applied on the organic polymer film 312, and a photoresist coating film is formed on the silica glass film.
A photoresist coating film was patterned using a reticle formed of only a shifter film, and using this as a mask, the silica glass film and the organic polymer film 312 were patterned by dry etching. This pattern is a pattern having a ring-shaped space of 0.25 μm similar to that of the first embodiment. In this embodiment, the polyimide 312 is used as the organic polymer film 312, but the same result can be obtained by using a normal photoresist (FIG. 16).

Next, after cleaning the exposed surface of the phosphorus-doped polycrystalline Si film 308 with a hydrofluoric acid buffer solution, an 80-nm-thick phosphorus-doped polycrystalline Si film to be the storage electrode 313 is deposited by the LP-CVD method. In the present example, Si ₂ H ₆ gas and PH ₃ gas were used for the deposition of the phosphorus-doped polycrystalline Si film at a temperature of 500 ° C. Subsequently, a photoresist 314 is spin-coated on the surface of the storage electrode 31 by 1 μm.
The groove part between 3 is embedded. Next, the photoresist 314 is etched back by an oxygen plasma asher to leave the photoresist 314 only in the groove, and the phosphorus-doped polycrystalline Si film surface on the organic polymer film 312 is exposed. continue,
The phosphorus-doped polycrystalline Si film on the exposed pattern of the organic polymer film 312 is etched by a dry etching method to expose the surface of the organic polymer film 312 (FIG. 17).

After that, the photoresist 31 remaining in the organic polymer film 312 and the groove 31 is removed by oxygen plasma asher.
4 is removed to form a storage electrode 313 having a double elliptic cylindrical shape (FIG. 18).

After that, as in the first embodiment, the capacitor insulating film,
The plate electrode and the predetermined wiring are formed, and the formation of the STC cell including the storage electrode 313 having a double elliptic cylindrical shape is completed.

In this embodiment, since the organic polymer film 312 is used as the material for the storage electrode 313, the formation and removal are very easy and the process of forming the storage electrode 313 is greatly simplified. . Further, as shown in Example 1, when removing the partition base material, a stopper (Si ₃ N ₄
Since it is not necessary to use a film), the entire surface of the storage electrode 313 having a double elliptic cylindrical shape can be effectively used, and the storage electrode area further increases.

[0040]

According to the present invention, a double elliptic cylindrical storage electrode can be formed with the same number of steps and the same layout rule as the conventional elliptic cylindrical storage electrode formation. As a result, a sufficient storage capacitance can be obtained even if the height of the storage electrode is lowered, so that the yield is significantly improved especially in the lithography and dry etching processes.

Further, as compared with the conventional double elliptic cylindrical storage electrode, the forming method is very simple and the storage electrode has high mechanical strength, so that the manufacturing yield is remarkably improved.

[Brief description of drawings]

FIG. 1 is a perspective view of a cross section in a direction parallel to a word line of a semiconductor device according to a first exemplary embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 7 is a sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a plan view and a sectional view of a reticle used in the first embodiment of the present invention.

FIG. 9 is a plan view of a storage electrode of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device according to a conventional method.

FIG. 11 is a cross-sectional view of a conventional semiconductor device.

FIG. 12 is a plan view of a reticle used in a conventional manufacturing method, and plan views and cross-sectional views of a manufactured semiconductor device.

FIG. 13 is a sectional view of a conventional semiconductor device.

FIG. 14 is a sectional view of a conventional semiconductor device.

FIG. 15 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 17 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 18 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 19 is a diagram illustrating a phase shift method used in the present invention.

FIG. 20 is a layout view of a shifter film on a reticle substrate.

FIG. 21 is a perspective view of a cross section of a conventional semiconductor device.

FIG. 22 is a diagram showing a simulation result of light intensity distribution.

FIG. 23 is a diagram showing a simulation result of light intensity distribution.

FIG. 24 is a diagram showing a simulation result of light intensity distribution.

[Explanation of symbols]

101, 201, 301 ... Si single crystal substrate 102, 202, 302 ... Element isolation region 103, 203, 303 ... Gate insulating film 104, 204, 304 ... Gate electrode 105, 107, 110, 111, 113, 116, 2
09, 211, 214, 305, 307, 310, 31
1 ... SiO ₂ film 106 (a) (b), 205 (a) (b), 306
(A) (b) ... Diffusion layers 108, 207, 308 ... Phosphorus-doped polycrystalline Si films 109, 208, 309 ... Bit lines 112, 210 ... Si ₃ N ₄ films 114 ... Photoresist patterns 115, 213, 313 ... Storage electrodes 117 Capacitance insulating film 118 ... Plate electrode 119 ... Interlayer insulating film 120 ... Wiring 206 ... Insulating film 212, 314 ... Photoresist 312 ... Organic polymer film

Claims (19)

[Claims] 1. A semiconductor device having a semiconductor element composed of a storage electrode and a transistor, which has a double cylindrical outer peripheral portion, an inner peripheral portion, and a bottom portion connecting the lower portion to each other. A semiconductor device having a bottom made of the same layer. 2. The semiconductor device according to claim 1, wherein the distance between the upper ends of the pair of the outer peripheral portion and the inner peripheral portion, which appear in a desired vertical section of the storage electrode, is substantially the same. Semiconductor device. 3. The semiconductor device according to claim 1 or 2, wherein the distance between the upper ends of the outer peripheral portion and the inner peripheral portion of the storage electrode is 0.
A semiconductor device having a range of 1 μm to 0.3 μm. 4. The semiconductor device according to claim 1, wherein the outer peripheral portion and the inner peripheral portion of the storage electrode have substantially the same height at their upper ends. 5. The semiconductor device according to claim 1, wherein the bottom of the region surrounded by the inner periphery of the storage electrode is made of a material different from that of the storage electrode. Characteristic semiconductor device. 6. A storage electrode and a transistor comprising a wall-shaped structure of an outer peripheral portion formed so as to surround a desired region, a wall-shaped structure of an inner peripheral portion formed inside thereof, and a bottom portion connecting the lower portions thereof. In the semiconductor device having a semiconductor element made of, the outer peripheral portion and the inner peripheral portion have a wall-shaped structure and a bottom portion that are formed of the same layer. 7. The semiconductor device according to claim 6, wherein a pair of outer peripheral wall-shaped structures and inner peripheral wall-shaped structures which appear in a desired vertical cross section of the storage electrode have substantially the same upper end spacing. A semiconductor device having a length. 8. The semiconductor device according to claim 6 or 7, wherein the distance between the upper ends of the outer peripheral wall-shaped structure and the inner peripheral wall-shaped structure of the storage electrode is in the range of 0.1 μm to 0.3 μm. A semiconductor device characterized by the above. 9. The semiconductor device according to claim 6, wherein the upper ends of the outer peripheral wall-shaped structure and the inner peripheral wall-shaped structure of the storage electrode are substantially at the same height. A semiconductor device characterized by the above. 10. The semiconductor device according to claim 6, wherein a bottom of a region surrounded by a wall-shaped structure of an inner peripheral portion of the storage electrode is different from a material forming the storage electrode. A semiconductor device characterized by: 11. A step of forming a film of a material having an etching rate higher than that of a material forming a storage electrode on a substrate, a step of forming an annular groove in the film, and at least an outer peripheral portion of the groove and an inner portion of the groove. A method of manufacturing a semiconductor device, comprising a step of forming a continuous film of a conductive substance on a wall surface and a bottom part of a peripheral part, and using the film of the conductive substance as a storage electrode. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the distance between the upper ends of the conductive material films formed on the wall surfaces of the outer peripheral portion and the inner peripheral portion of the groove is 0.1 μm to 0.3 μm.
A method for manufacturing a semiconductor device, wherein the semiconductor device is in the range of m. 13. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of forming the annular groove, a predetermined pattern portion forms a light phase on a photoresist film formed on the film. A method for manufacturing a semiconductor device, which is characterized by forming an annular groove by lithography using a reticle formed only by a shifter film which is inverted by 180 degrees, and transferring the annular groove to the film by dry etching. . 14. A step of sequentially forming a first insulating film and a second insulating film on a film of a first conductive material having a desired shape, and an annular groove on the second insulating film. A step of forming a photoresist pattern, and a photoresist pattern shape is transferred to the second insulating film and the first insulating film by a dry etching method to form an annular groove, and the first conductive material in a desired region is formed. Of exposing the surface of the film, the step of removing the photoresist pattern, and the step of forming a film of the second conductive material on the outer peripheral and inner peripheral wall surfaces and bottoms of the groove and the second insulating film. And a step of forming a third insulating film having a film thickness in which the groove portion sandwiched by the film of the second conductive material is sufficiently filled, and the third insulating film is etched to form the third insulating film only in the groove portion. And the step of leaving the second conductive film on the second insulating film pattern Exposing a surface of the second insulating film is grayed, second and first insulating film as a stopper,
At least a step of removing the third insulating film by etching is included, and the film of the second conductive material is formed of a double cylindrical outer peripheral portion, an inner peripheral portion, and a bottom portion connecting the lower portions thereof. A method of manufacturing a semiconductor device, which comprises manufacturing a semiconductor element that uses a storage electrode. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the distance between the upper ends of the second conductive material films formed on the wall surfaces of the outer peripheral portion and the inner peripheral portion of the groove is 0.1 μm to 0. A method for manufacturing a semiconductor device, characterized in that the thickness is in the range of 3 μm. 16. The method of manufacturing a semiconductor device according to claim 14, wherein the step of forming a photoresist pattern having an annular groove on the second insulating film comprises the step of forming the second photoresist pattern.
A photoresist film is formed on the insulating film, and a ring-shaped groove is formed by lithography using a reticle in which a predetermined pattern portion is formed of only a shifter film that inverts the phase of light by 180 degrees. Of manufacturing a semiconductor device. 17. A step of forming a first organic polymer film on a film of a first conductive material having a desired shape, and a step of forming a material for a dry etching mask on the first organic polymer film. A step of forming a film, a step of forming a photoresist pattern having an annular groove on a film of a material which will be a mask of dry etching, and a photoresist pattern shape which is a film of a material which will be a mask of dry etching by a dry etching method, Further, the step of transferring to the first organic polymer film to form a ring-shaped groove and exposing the surface of the film of the first conductive material in a desired region is used as a photoresist pattern and a dry etching mask. A step of removing the material film, a step of forming a film of the second conductive material on the wall surfaces and bottoms of the outer peripheral portion and the inner peripheral portion of the groove, and the first organic polymer film, and a second conductive material Sandwiched in the film A step of embedding a second organic polymer film in the portion, and etching the film of the second conductive material exposed on the first organic polymer film pattern to expose the surface of the first organic polymer film And a step of removing the first and second organic polymer films by an oxygen plasma asher, which comprises a double cylindrical outer peripheral portion, an inner peripheral portion, and a bottom portion connecting the lower portions thereof. A method of manufacturing a semiconductor device, comprising manufacturing a semiconductor element using a film of a second conductive material as a storage electrode. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the distance between the upper ends of the films of the second conductive material formed on the wall surfaces of the outer peripheral portion and the inner peripheral portion of the groove is 0.1 μm to 0 μm. A method for manufacturing a semiconductor device, characterized in that the thickness is in the range of 3 μm. 19. The method of manufacturing a semiconductor device according to claim 17, wherein the step of forming a photoresist pattern having an annular groove on a film of a material that serves as a mask for the dry etching includes the step of forming the second insulating film. A semiconductor device characterized by forming a photoresist film thereon and forming an annular groove by lithography using a reticle in which a predetermined pattern portion is formed of only a shifter film for inverting the phase of light by 180 degrees. Manufacturing method.