JP2602581B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device .
It relates to the manufacturing method, and more particularly to a method of manufacturing a semiconductor memory element having a stack type memory cell.

[0002]

2. Description of the Related Art DRAMs, which are at the forefront of high integration, have increased storage capacity by a factor of four every three years.
It is expected that the capacity will sequentially increase to b, 64 Mb, 256 Mb. In order to improve the degree of integration, DRAM
It is necessary to reduce the size of the memory cell, which is the storage unit of. When reducing the size of a memory cell, in order to prevent a soft error due to radiation and to secure a sufficient S / N ratio, the charge storage capacity in the memory cell must be maintained at a certain minimum value or more. For this reason, it is impossible to form a capacitor on a semiconductor surface after a 4 Mb DRAM, and a so-called stacked memory cell in which this capacitor is formed on a MOS transistor is promising.

In manufacturing a conventional stacked memory cell, a contact hole is formed on a terminal of a MOS transistor formed on the surface of a semiconductor substrate in order to connect one electrode (storage electrode) of the capacitor to the terminal of the MOS transistor. Open . This contact hole on the interlayer insulating film formed on the transistor, the resist opening in a predetermined pattern dimension by photolithography technique, as it has been formed by etching the interlayer insulating film using the resist as a mask .

[0004]

By the way, in a stack type memory cell, in order to prevent an electrical short circuit between a storage electrode of a capacitor and a gate electrode of a transistor formed earlier, a contact hole and an underlying gate electrode are provided. Needs enough space. However, when the contact hole is formed by the above-described method, there is a problem that the alignment accuracy at the time of exposure is strict and the size of the contact hole prevents the reduction of the memory cell.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory in which a contact hole smaller than the minimum size achievable by photolithography can be formed, and therefore, the contact hole can be easily aligned with an underlying element or wiring. It is to provide a method of manufacturing element.

[0006]

In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention comprises a transistor formed on the surface of a semiconductor substrate and a capacitor having one electrode connected to a terminal of the transistor. Has a plurality of memory cells, and one electrode of the capacitor is
A columnar or cup-shaped central portion, and an outer peripheral portion in contact with the outer periphery of the central portion or surrounding the outer periphery in a spaced apart manner,
A semiconductor memory element comprising: a bottom portion integrally connecting a lower portion of the central portion and a lower portion of the outer peripheral portion; and the other electrode of the capacitor comprises portions opposed to the central portion, the outer peripheral portion, and the bottom portion of the one electrode. A step of forming an interlayer insulating film on the transistor, a first film made of a conductive material on the interlayer insulating film, and selectively etching the first film. And a second material made of a material which is etched under the same conditions as the interlayer insulating film.
Sequentially depositing a third film made of a material that is difficult to be etched under the conditions for etching the interlayer insulating film; and forming the first film from the surface of the third film on the terminal of the transistor from the surface of the third film. Forming an opening having a predetermined pattern dimension reaching the surface of the film, depositing a fourth film made of a conductive material that is difficult to be etched under conditions for etching the interlayer insulating film on the substrate, The fourth film is removed by etching except for the step portion of the opening, and the opening is narrowed in close contact with the inner wall of the opening, and a side wall connected to the first film at the lower end of the inner wall. Forming a film, etching the first film exposed at the bottom of the opening, and removing the first film; and removing the third film around the capacitor region overlapping the opening on the substrate. Remove Forming a contact hole on the terminal of the transistor by etching the interlayer insulating film exposed at the bottom of the opening using the sidewall film and the third film remaining in the capacitor region as a mask; Removing the second film present around the capacitor region, depositing a fifth conductive film on the substrate, filling the contact hole, and forming the fifth electrode on the one electrode. A step of forming a central portion, and etching and removing the fifth film except for a step around the capacitor region, and closely surrounding the side wall of the second film remaining in the capacitor region. And forming the outer peripheral portion of the one electrode having a lower portion connected to the first film, and then removing the third film exposed in the capacitor region by etching. Forming the bottom of the one electrode by etching and removing the first film exposed around the capacitor region; and removing the second film exposed between the center and the outer periphery. Removing the film with a corrosive agent, and forming the other electrode facing the central portion, the outer peripheral portion, and the bottom portion of the one electrode with the capacitor insulating film interposed therebetween. .

[0007]

[0008]

According to the method for manufacturing a semiconductor memory device of the present invention, the contact hole on the terminal of the transistor is formed by the third step.
The opening is formed using the side wall film, which is in close contact with the inner wall of the opening formed through the first film and the second film, and the third film processed into a capacitor pattern shape as a mask. Since the sidewall film is formed in a self-aligned manner without performing lithography, the size of the contact hole can be set to be equal to or smaller than the minimum dimension possible by lithography technology. Therefore, when exposing the contact hole, alignment with the underlying element or wiring becomes easier than before. Also, as the size of the contact hole is reduced, the area of the memory cell can be reduced.

The side wall film is made of a conductive material and is used as it is as a part of the storage electrode.
Therefore, there is no need to provide a special step of removing the side wall film after opening the contact hole. Further, the storage electrode of the capacitor is formed of a columnar or cup-shaped central portion made of a conductive material, an outer peripheral portion, and a bottom portion connecting both portions, and the other electrode is formed of a portion facing each of these portions. , A charge storage capacity equal to or higher than the required minimum value is secured. Since the outer peripheral portion is provided in a self-aligned manner without performing lithography, the distance between the capacitors of the adjacent memory cells can be set to be equal to or less than the minimum distance possible by the lithography technique. Therefore, in the case of high integration, the cell area is effectively utilized, and a charge storage capacity equal to or more than a required minimum value is easily secured.

[0010]

EXAMPLES The following examples a method of manufacturing a semiconductor memory element of the present invention will be described in detail.

FIGS. 1 to 8 show cross sections of a semiconductor memory device manufactured by a manufacturing method according to an embodiment of the present invention in the order of steps. FIGS. 10 to 17 show steps in the steps shown in FIGS. 1 to 8 show plane patterns (FIGS. 1 to 8 correspond to cross sections taken along line XX of FIGS. 10 to 17). In each of FIGS. 1 to 8 and FIGS. 10 to 17, a region demarcated by a dashed line indicates one memory cell.

First, as shown in FIGS. 1 and 10,
A transistor T is formed on the surface of a P-type Si substrate 1 by a known procedure, and an SiO ₂ film 7 and a Si ₃ N ₄ film 8 are formed as an interlayer insulating film under a capacitor on the substrate 1 by CVD (chemical vapor deposition). ) Method. Here, 2 is an element isolation region made of SiO ₂ formed by selective oxidation, and 3 is a gate insulating film made of SiO ₂ formed by thermal oxidation, 4, 4 ′,
4 ″ is a gate electrode (word line) made of phosphorus (P) -doped polycrystalline Si, and 5 and 6 are N (+) type source and drain regions formed by ion implantation of arsenic (As), respectively. , 6a
Indicates an N (-) region having an LDD (lightly doped drain) structure formed by phosphorus ion implantation. Further, the Si ₃ N ₄ film 8 is formed for the purpose of protecting the underlying SiO ₂ film 7 from the hydrofluoric acid treatment performed in the step described later, and it is considered that the film thickness is reduced in the step described later. Thus, the film thickness is set to a sufficient value.

Next, as shown in FIGS. 2 and 11,
A polycrystalline Si film 9 is used as a first film, and SiO _{2 is used} as a _second film.
The polycrystalline Si film 11 as the film 10 and the third film
The entire surface is sequentially deposited by the VD method, and the SiO ₂ film 12 is further deposited on the entire surface by the CVD method. Subsequently, by a lithography technique, a resist formed an opening pattern dimension L ₁ in the contact position as a mask, SiO ₂ film 12,
The polycrystalline Si film 11 and the SiO ₂ film 10 are sequentially processed by a reactive ion etching method. The leads from the surface of the SiO ₂ film 12 on the surface of the Si ₃ N ₄ film 8 to form an opening W ₁ substantially equal to the pattern dimension L ₁ between the opening of the resist.
Thereafter, the resist is removed.

Next, a polycrystalline Si film is deposited on the entire surface as a fourth film. Except for the step portion of the opening W ₁ formed in the step for removing the polycrystalline Si film by a reactive ion etching method. Then, as shown in FIGS. 3 and 12, made of polycrystalline Si, with narrowing the opening width in close contact with the inner wall of the opening W _1, the polycrystalline Si film at the lower end of the inner wall 9
Is formed. Furthermore, by reactive ion etching, the side wall film in the opening W ₁ 13
The polycrystalline Si film 9 exposed inside is removed. The etching in this step employs a reactive ion etching method capable of performing anisotropic etching so that the side wall film 13 is not etched.

Next, a resist is formed by a lithographic technique in the capacitor region (region for forming a capacitor. Overlapping with the opening W _1.), The resist as a mask, as shown in FIGS. 4 and 13, the SiO ₂ film 1
The 2 and polycrystalline Si films 11 are sequentially processed into a rectangular electrode shape by a reactive ion etching method. Thereafter, the resist is removed.

Next, as shown in FIGS. 5 and 14,
The polycrystalline Si film 11 remaining on the side wall film 13 and the capacitor region as a mask, by reactive ion etching, is exposed at the bottom of the opening W ₁ Si
_The 3N ₄ film 8 and the SiO ₂ film 7 are removed. Thus, on the source region 5 of the transistor T formed on a surface of the semiconductor substrate 1, a contact hole W ₂ of the narrow dimension L ₂ than the pattern size of the opening W _1. At the same time, S
The SiO ₂ film 12 and the SiO ₂ film 10 around the capacitor region are removed. In the capacitor area,
The SiO ₂ film 10a is left with the upper and lower portions sandwiched between the polycrystalline Si films 9,11.

Next, as shown in FIGS. 6 and 15,
Depositing a polycrystalline Si film on the entire surface in a sufficient thickness to fill the contact holes W ₂ which is opened as the fifth layer. By embedding this way the contact hole W _2,
The source region 5 of the transistor T is made of a polycrystalline Si film.
From through the contact hole W ₂ to form the central portion 15 of the storage electrode S which protrudes into a columnar shape. The central portion 15 has a columnar shape with a depression on the upper surface reflecting the step of the side wall film 13. In particular, when the fifth film is significantly thinner than the step of the side wall film 13, the central portion 15 has a cup shape. Thereafter, the polycrystalline Si film is removed by reactive ion etching except for the step formed around the capacitor region in the process. Then, as shown in FIG. 6, a polycrystalline Si film is formed, and the SiO ₂ film 10a is formed.
And closely surround the outer periphery of the polycrystalline S
The outer peripheral portion 14 of the storage electrode S connected to the i film 9 is formed.
Subsequently, the polycrystalline Si film 11 exposed in the capacitor region and the polycrystalline Si film
The film 9 is removed by etching. By removing the polycrystalline Si film 9 around the capacitor region, the bottom 9a of the storage electrode S is formed. The central portion 15 and the outer peripheral portion 14 are electrically connected via the bottom portion 9a. In addition,
The material constituting the outer peripheral portion 14 was polycrystalline Si made of the same material as that of the bottom portion 9a. However, the material is not limited to this. In the next step, the SiO ₂ film 10a is replaced with an etching solution containing hydrofluoric acid. The conductive material may be any conductive material that is not immersed in the removal. In addition, the above Si ₃ N
_{Although the four} films 8 have a sufficient thickness in the process, it is desirable to selectively etch the polycrystalline Si film 9 with respect to the Si ₃ N ₄ film 8.

Next, the SiO ₂ film 10a remaining in the gap between the central portion 15 and the outer peripheral portion 14 of the storage electrode S is removed using an etching solution containing hydrofluoric acid. Then, FIG.
As shown in FIG. 16, a capacitor insulating film 16 is formed, and as the other electrode of the capacitor C, a plate electrode 17 facing each part of the storage electrode S and serving as a common wiring of a plurality of memory cells is formed. The capacitor insulating film 16 is formed of LP
After forming a Si ₃ N ₄ film by CVD (low pressure chemical vapor deposition), the surface of this Si ₃ N ₄ film is oxidized and formed by a thermal oxidation method (SiO ₂ / Si ₃ N ₄ bilayer film). The plate electrode 17 uses phosphorus-doped polycrystalline Si.

Finally, as shown in FIGS. 8 and 17, the interlayer insulating film 1 under the bit line is formed on the capacitor C.
8, a contact hole W ₃ is opened on the drain region 6 of the transistor T, and a common wiring (bit line) is formed.
19 is formed. Thus, the fabrication of the semiconductor memory device is completed.

In the example described above, the bit line 19 is formed after the formation of the capacitor C, but the invention is not limited to this. As shown in FIG. 9, the capacitor C may be formed after the bit line 19 is formed. First,
The element isolation region 2 and the transistor T are formed on the surface of the semiconductor substrate 1 by the same procedure as described in the steps.
Subsequently, after depositing an interlayer insulating film 18 below the bit line, a bit line 19 connected to the drain region 6 of the transistor T is formed. On this, an SiO ₂ film 7 and a Si ₃ N ₄ film 8 are deposited as an interlayer insulating film below the capacitor. Thereafter, the step of forming the capacitor C is the same as the above-mentioned steps 1 to. When the capacitor C is formed after the formation of the bit line 19, the contact hole W
₂ needs to secure a sufficient space not only for the gate electrode 4 but also for the bit line 19, but according to the present invention, the problem of alignment accuracy at the time of exposure can be solved.

Next, the effect of the method for manufacturing a semiconductor memory device will be quantitatively evaluated. When formed with a minimum line width of 0.5 μm, the memory cell size is 1.2 μm × 3 μm = 3.6 μm.
the m ^2. Even when forming the bit line 19 is either before or after the capacitor C formed, the thickness of the polycrystalline Si comprising the pattern dimension L ₁ of the opening W ₁ which is open by lithography 0.5 [mu] m, the material of the side wall film 13 Is set to 0.1 μm, the dimension L ₂ of the contact hole W ₂ is set to 0.1 in a self-aligned manner.
Can be reduced to 3 μm.

Further, the shape of the capacitor C defined by lithography is made into a rectangular shape of 0.6 μm × 1.35 μm,
Assuming that 0.5 μm thick polycrystalline Si is used as the storage electrode S, the surface area of the polycrystalline Si electrode calculated from this shape is 2.8 μm ²
About. In this case, in a general stack type memory cell, only an area of about 3 μm ² can be used as the capacitor C. However, the thickness of the polycrystalline Si9 is 0.1 μm.
m, the thickness of the SiO ₂ film 10 is 0.4 μm, the outer peripheral portion (polycrystalline Si).
14 a thickness of 0.15μm, and to form the memory cell, at the height of the same storage electrode generally of stacked memory cells may utilize a surface area of about 5.8 [mu] m ² as a capacitor C. Actually, when the capacitor capacity per memory cell was compared and measured, the conventional stack type memory cell had only 17 fF, while the structure of the semiconductor memory element described above can realize a large capacity of 35 fF and 16 MbD.
The size was large enough to be used for RAM. It should be noted that no significant deterioration was observed in the leakage current and the life of the capacitor insulating film.

As described above, the SiO ₂ film 10 and the polycrystalline Si 1
After opening the opening W ₁ lithographically 1, the side wall film 13 is formed in a self-aligned manner in the opening W _1, polycrystalline Si is further left on the side wall film 13 and the capacitor region
Using the film 11 as a mask, the interlayer insulating film (SiO ₂ film 7 and Si
By opening the ₃ N ₄ film 8) to form a contact hole W ₂ smaller dimension L ₂ than the minimum dimension L ₁ capable through lithography. Further, the side wall film 13 can be used as a part of the storage electrode S as it is.

By providing the outer peripheral portion 14 around the capacitor region, the facing area of the capacitor C can be increased with a limited cell area. Since the outer peripheral portion 14 is provided in a self-aligned manner without performing lithography, the distance between the capacitors C of the adjacent memory cells can be reduced to the limit of the lithography technique, and the elements can be highly integrated. Moreover, there is no need to increase the number of masks.

[0025] In the example described above Although illustrated short diameter and the diameter of the opening W ₁ of the processed capacitor region in the step as the same size is not limited thereto. As shown in FIGS. 18 and 19, there is no problem in processing the storage electrode even if one of the dimensions is large. Further, even if the alignment of the capacitor region defined by the lithography method in the process is shifted in any of the minor diameter directions, there is no problem as shown in FIG.

[0026]

As apparent from foregoing description, according to the manufacturing method of the semiconductor memory element of the present invention, phosphorus photography a contact hole for connecting the one terminal of one electrode (storage electrode) and the transistor of the capacitor It is possible to finish to dimensions below the minimum possible with the technology. Therefore, at the time of exposure, alignment between the contact hole for the storage electrode and the underlying element or wiring becomes easier as compared with the related art. Further, since the size of the storage electrode contact hole is reduced, the area of the memory cell can be reduced.

Since the side wall film made of a conductive material used as a mask at the time of opening the contact hole is directly used as a part of the storage electrode, the step of removing the side wall film after the opening of the contact hole is performed. Need not be provided specially.

Further, since the outer peripheral portion is provided in a self-aligned manner without increasing the number of masks, the distance between adjacent memory cell capacitors can be made smaller than the minimum distance possible by lithography. Therefore, in the case of high integration, the cell area can be effectively utilized,
It is possible to easily secure a charge storage capacity equal to or more than the required minimum value.

[Brief description of the drawings]

FIG. 1 is a process diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a process diagram illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a process diagram illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 4 is a process chart illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 5 is a process chart illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 6 is a process chart illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 7 is a process chart illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 8 is a process chart illustrating a method for manufacturing a semiconductor memory device according to one embodiment of the present invention.

FIG. 9 is a diagram showing a semiconductor memory device manufactured by a manufacturing method according to another embodiment of the present invention.

FIG. 10 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 1;

FIG. 11 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 2;

FIG. 12 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 3;

FIG. 13 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 4;

FIG. 14 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 5;

FIG. 15 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 6;

FIG. 16 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 7;

FIG. 17 is a view showing a plane pattern of the semiconductor memory element in the step shown in FIG. 8;

FIG. 18 is a view showing a modification of the semiconductor memory device.

FIG. 19 is a view showing a modification of the semiconductor memory device.

FIG. 20 is a diagram showing an example in which the alignment of the capacitor region of the semiconductor memory element is shifted.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 P-type silicon substrate 2 element isolation insulating film 3 gate insulating film 4, 4 ′, 4 ″ gate electrode 5 source region 6 drain region 7, 10, 12 SiO ₂ film 8 Si ₃ N ₄ film 9, 11 polycrystalline Si Film 13 sidewall film 14 outer peripheral portion 15 central portion 16 capacitor insulating film 17 plate electrode 18 interlayer insulating film under bit line 19 bit line C capacitor T MOS transistor S storage electrode

Claims (1)

(57) [Claims] 1. A semiconductor memory device comprising: a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and a capacitor having one electrode connected to a terminal of the transistor; one electrode of the capacitor having a columnar shape or a cup shape; A central portion, an outer peripheral portion that is in contact with the outer periphery of the central portion or surrounds the periphery of the outer periphery at a distance, and a bottom portion that integrally connects the lower portion of the central portion and the lower portion of the outer peripheral portion, and The method according to claim 1, wherein the electrode is a part of the semiconductor memory device including a portion opposed to a center portion, an outer peripheral portion, and a bottom portion of the one electrode; and a step of forming an interlayer insulating film on the transistor; A first film made of a conductive material,
A second film made of a material that can be selectively etched with the first film and etched under the same conditions as the interlayer insulating film, and a second film made of a material that is hardly etched under the conditions of etching the interlayer insulating film. A step of sequentially depositing a third film; a step of forming an opening having a predetermined pattern dimension from the surface of the third film to the surface of the first film on the terminal of the transistor; Depositing a fourth film made of a conductive material that is difficult to be etched under the condition of etching the insulating film on the substrate; and etching and removing the fourth film except for a step portion of the opening. Forming a side wall film connected to the first film at the lower end of the inner wall while closely contacting the inner wall of the opening, and forming the first film exposed at the bottom of the opening. The Removing the third film around the capacitor region overlapping the opening on the substrate; and removing the interlayer insulating film exposed at the bottom of the opening. Etching using the side wall film and the third film remaining in the capacitor region as a mask to open a contact hole on the terminal of the transistor and removing the second film present around the capacitor region; Depositing a fifth film having conductivity on the substrate, filling the contact hole to form the central portion of the one electrode, and excluding a step around the capacitor region. The fifth film is removed by etching so that the side wall of the second film remaining in the capacitor region closely surrounds the side wall of the second film and has a lower portion connected to the first film. Forming the outer peripheral portion of one of the electrodes, and subsequently removing the third film exposed in the capacitor region by etching, while etching the first film exposed around the capacitor region. Removing the second film exposed between the central portion and the outer peripheral portion with a corrosive agent; and removing the second insulating film between the central portion and the outer peripheral portion with a corrosive agent. Forming the other electrode facing the central portion, the outer peripheral portion, and the bottom portion of the one electrode, respectively.