JP2936326B1 - Method of manufacturing lower electrode of capacitor - Google Patents

Abstract

A method for manufacturing a lower electrode of a capacitor is disclosed, which prevents over-etching of a hemispherical granular silicon layer and formation of a microbridge in a conventional assembling method. A first conductive layer is formed in an opening for making an electrical connection with a specific region of a substrate. A first hemispherical granular silicon layer 42 and a second dielectric layer 44 are formed on the first conductive layer 40, and the second dielectric layer 44, the first hemispherical granular silicon layer 42 and the first conductive layer 40 is patterned. Further, a second conductive layer 46 and a second hemispherical granular silicon layer 48 are formed over the entire substrate structure, and the oxide layer 36 and the second hemispherical granular silicon layer 48 and the second conductive layer 46 of the second hemispherical granular silicon layer 48 and the second conductive layer 46 are formed. The portion on the dielectric layer 44 is removed, the second dielectric layer 44 is removed, and the first hemispherical granular silicon layer 42 is exposed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a lower electrode of a capacitor.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) is a device for storing digital data. Since a DRAM uses a capacitor to store data, the capacitance (capacitance) of the capacitor of the DRAM must be large enough to increase the data retention time. Very large scale integrated circuit (U
With the advent of LSIs, the size of each memory cell in a DRAM has been reduced. As a result, the electrode surface area of the capacitor needs to be increased in any way to compensate for the reduction in capacitance. For example, a silicon (HSG) layer having a hemispherical granular surface is disposed on the electrode plate of the capacitor to increase the surface area.

FIGS. 1 to 6 are sectional views sequentially showing steps of manufacturing a lower electrode of a capacitor by a conventional method. First, as shown in FIG. 1, a semiconductor substrate 10 having a field oxide layer 12 for defining an element (device) region.
Is supplied. Details of the devices in the device region are not shown in the drawings. A dielectric layer 14 is formed on the substrate 10;
Further, a contact window 16 is formed in the dielectric layer 14 to expose one of the transistor source / drain regions (not shown) in the device region.

Next, as shown in FIG. 2, a conductive layer 18 is laminated on the dielectric layer 14 and in the contact opening 16 to form an electrical connection with the source / drain regions. The conductive layer 18 is an ion-implanted poly (polycrystalline) silicon layer formed by, for example, a reduced pressure vapor deposition method. Thereafter, a cap dielectric layer 22 is deposited on the conductive layer 18 using, for example, a vapor deposition method. The cap dielectric layer 22 is made of, for example, boron phosphorus silicate glass (B
PSG). Thereafter, a photolithography process and an etching process are used to pattern the cap dielectric layer 22 and the conductive layer 18, and finally the structure shown in FIG. 2 is formed.

[0005] Next, as shown in FIG. 3, the ion-implanted polysilicon is formed by, for example, low pressure vapor deposition (LPCVD).
It is laminated on the whole substrate structure by the method. After a while
This polysilicon layer is etched back, for example by an anisotropic etching method, to form spacers 24 on the cap dielectric layer 22 and the sidewalls of the conductive layer 18.

[0006] Next, as shown in FIG. 4, the cap dielectric layer 22 is removed to expose the conductive layer 18. This cap dielectric layer 22 is formed by reactive ion etching (RI) using, for example, a gaseous hydrogen fluoride or hydrofluoric acid solution.
E) is removed by the method.

Next, as shown in FIG. 5, a silicon layer having a hemispherical granular surface, that is, a hemispherical granular silicon layer 26 is formed.
Is formed over the entire substrate structure, including the conductive layer 18, the dielectric layer 14, and the spacers 24. The hemispherical granular silicon layer 26 can be stacked by, for example, a low pressure vapor deposition (LPCVD) method using silane SiH ₄ or Si ₂ H ₆ as a reaction gas source. Preferably, the stack of hemispherical granular silicon is introduced at a temperature between the growth of amorphous silicon and the growth of polysilicon.

Next, as shown in FIG. 6, the hemispherical granular silicon layer 26 on the dielectric layer 14 is removed by, for example, an anisotropic etching back process. The rest of the conductive layer 18, the spacer 24 and the hemispherical granular silicon layer 26 constitute the lower electrode of the capacitor. The reason for partially removing the hemispherical granular silicon layer 26 on the dielectric layer 14 is as follows.
This is to prevent any electrical connection between the two conductive layers 18. In other words, this is to avoid damage to the semiconductor device caused by electrical connection between the two lower electrodes of the adjacent capacitors.

[0009]

However, the portion of the hemispherical layer 26 laminated on the dielectric layer 14 is etched and removed.
When removed by the backing process, the hemispherical granular silicon layer 2
All 6 are exposed to the etchant. As a result, the remaining portion of the hemispherical granular silicon layer 26 is similarly damaged. Damage to the hemispherical granular silicon layer 26 at this portion on the conductive layer 18 is particularly severe, and causes leakage current from a dielectric layer to be laminated later. Therefore, the etching process must be carefully controlled to avoid excessive damage to hemispherical granular silicon layer 26.

[0010] Furthermore, if the back etching process is not properly controlled, residual electrical connections, called microbridges, that can be connected to adjacent lower electrodes can occur. This microbridge creates a short path that damages both adjacent capacitors.

In view of the foregoing, there is a need for an improved method of forming a hemispherical granular silicon layer.

It is an object of the present invention to provide a method of manufacturing a lower electrode of a capacitor in which over-etching of a hemispherical granular silicon layer and formation of a microbridge are prevented in a conventional assembling method.

[0013]

In connection with the above objects of the present invention and to achieve these and other advantages,
The present invention provides a method of manufacturing a lower electrode of a capacitor.
The method comprises providing a semiconductor substrate and then forming a first dielectric layer on the substrate. Next, a silicon nitride layer is formed on the first dielectric layer, and then an oxide layer is formed on the silicon nitride layer. After a while
The oxide layer, the silicon nitride layer, and the first dielectric layer are patterned to form a contact opening exposing a specific region of the semiconductor substrate.

In a subsequent step, a first conductive layer is laminated on the oxide layer and in the contact opening to form an electrical connection with the specific region of the substrate. Next, a first hemispherical granular silicon layer is formed on the first conductive layer, and then a second dielectric layer is formed on the first hemispherical granular silicon layer. Then, the second dielectric layer, the first hemispherical granular silicon layer, and the first conductive layer are patterned to expose portions of the oxide layer. Thereafter, a second conductive layer is formed on the second dielectric layer, the first conductive layer, and the oxide layer.

Thereafter, a second hemispherical granular silicon layer is formed on the second conductive layer. Portions of the second conductive layer and the second hemispherical granular silicon layer located on the oxide layer and the second dielectric layer are removed to expose the oxide layer and the second dielectric layer Let it. However, the second conductive layer and a part of the second hemispherical granular silicon layer remain fixed to the second dielectric layer and the first conductive layer. Finally, the second dielectric layer and the oxide layer are removed, forming the lower electrode of the capacitor. The lower electrode is formed from the second hemispherical granular silicon layer, the second conductive layer, the first hemispherical granular silicon layer, and the first conductive layer.

The present invention uses the second dielectric layer as a protective mask for the first hemispherical granular silicon layer against an etch back process so that any damage to the first hemispherical granular silicon layer can be avoided. . As a result, leakage current from the dielectric layer that is laminated on the lower electrode later can be prevented.

According to another aspect of the present invention, the etch-back process of the first hemispherical granular silicon layer can be effectively controlled so that micro-bridge formation between lower electrodes does not occur.

According to another aspect of the present invention, removing the oxide layer increases the surface area of the lower electrode, thereby increasing the capacitance of the capacitor.

It is understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the scope of the invention.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the examples shown in the drawings. Wherever possible, the same reference numbers are used in the drawings and the description for the same parts.

7 to 10 are sectional views showing the progress of the manufacturing process in manufacturing the lower electrode of the capacitor according to the preferred embodiment of the present invention. First, as shown in FIG. 7, a semiconductor substrate 30 having a field oxide layer 32 defining an element region is provided. Details of the elements in this element region are not shown in the drawings. Next, a dielectric layer 34, eg, a silicon oxide layer, is formed over the entire substrate structure, and then a silicon nitride layer 35 is laminated over the dielectric layer 34. Thereafter, an oxide layer 36 is formed on the silicon nitride layer 35. This oxide layer 36 is made of, for example, boron phosphorus silicate glass (BPSG). In a subsequent step, a photolithography process and an etching process are performed for the oxide layer 36, the silicon nitride layer 35, and the dielectric layer 3.
4 used to pattern. Subsequently, a contact opening 38 for exposing the source / drain of the transistor in the element region (not shown) is formed.

Next, as shown in FIG. 8, a conductive layer 40 is laminated over the oxide layer 36 and in the contact opening 38 to make an electrical connection with the source / drain regions of the transistor. The conductive layer 40 is formed, for example, under reduced pressure vapor phase growth (LPCVD).
FIG. 2 is an ion-implanted polysilicon layer formed using a method. Thereafter, hemispherical granular silicon layer 42 is formed on conductive layer 40. This hemispherical granular silicon layer 42
Is deposited by a low pressure vapor phase epitaxy (LPCVD) method using silane SiH ₄ or Si ₂ H ₆ as a reaction gas source. Preferably, the stack of hemispherical granular silicon is introduced at a temperature between the growth of amorphous silicon and the growth of polysilicon. Next, the cap dielectric layer 4
4, for example, boron phosphorus silicate glass is deposited on the hemispherical granular silicon layer 42 using, for example, vapor deposition. Subsequently, photolithography and etching processes pattern the cap dielectric 44, the hemispherical granular silicon layer 42 and the conductive layer 40 to form the oxide layer 36.
Used to expose part of the Finally, the structure shown in FIG. 8 is obtained.

Next, as shown in FIG. 9, a conductive layer 46 made of ion-implanted polysilicon is deposited on the entire substrate structure including the cap dielectric layer 44 and the oxide layer 36 by, for example, low pressure vapor deposition. Are laminated using a method. Thereafter, another hemispherical granular silicon layer 48 is formed on the conductive layer 46.
Is formed using the same method as that for forming the hemispherical granular silicon layer 42.

Next, as shown in FIG. 9, the hemispherical granular silicon layer 48 and the conductive layer 46 are etched back using, for example, an anisotropic etching method. This etching
After the backing process, the conductive layer 46 is converted into a spacer structure on the sidewalls of the dielectric layer 44 and the conductive layer 40, exposing a portion of the oxide layer 36. Because an anisotropic etch back process is used, the portion of hemispherical granular silicon layer 48 that is formed over conductive layer 46 is retained. In a subsequent step, the cap dielectric layer 44 is removed until the hemispherical granular silicon layer 42 is exposed. This cap dielectric layer 4
4 is removed by, for example, a reactive etching (RIE) method using a gaseous hydrogen fluoride or hydrofluoric acid solution. Since oxide layer 36 is made of the same material as cap dielectric layer 44, oxide layer 36 also
It is also removed by the method. By this stage, the lower electrode of the capacitor including the hemispherical granular silicon layer 42, the hemispherical granular silicon layer 48, the conductive layer 40, and the conductive layer 46 is formed.

The present invention uses the cap dielectric layer 44 as a protective mask for the hemispherical granular silicon layer 42 against the etch back process so that damage to the hemispherical granular silicon layer is minimized. As a result,
Leakage current from a dielectric layer that is later laminated on the lower electrode of the capacitor is prevented.

Another embodiment of the present invention is to effectively control the etching of the hemispherical granular silicon layer 48 so that little micro-bridges between lower electrodes are formed.

A third embodiment of the present invention is that the surface area of the lower electrode can be increased by removing the oxide layer.
Therefore, the capacitance of the capacitor can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to include modifications and variations of the present invention and their equivalents.

[0030]

As described above, according to the present invention, there is provided a method of manufacturing a lower electrode of a capacitor in which over-etching of a hemispherical granular silicon layer and formation of a microbridge are prevented in a conventional assembling method. Can be.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a progress of a manufacturing process in manufacturing a lower electrode of a capacitor by a conventional method.

FIG. 2 is a cross-sectional view showing the progress of a manufacturing process in manufacturing a lower electrode of a capacitor according to a conventional method.

FIG. 3 is a cross-sectional view showing a progress of a manufacturing process in manufacturing a lower electrode of a capacitor according to a conventional method.

FIG. 4 is a cross-sectional view showing a progress of a manufacturing process in manufacturing a lower electrode of a capacitor according to a conventional method.

FIG. 5 is a cross-sectional view showing a progress of a manufacturing process in manufacturing a lower electrode of a capacitor by a conventional method.

FIG. 6 is a cross-sectional view showing a progress of a manufacturing process in manufacturing a lower electrode of a capacitor according to a conventional method.

FIG. 7 is a cross-sectional view illustrating a process of manufacturing a lower electrode of a capacitor according to a preferred embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a process of manufacturing a lower electrode of a capacitor according to a preferred embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a process of manufacturing a lower electrode of a capacitor according to a preferred embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a process of manufacturing a lower electrode of a capacitor according to a preferred embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 30 semiconductor substrate 32 field oxide layer 34 first dielectric layer 35 silicon nitride layer 36 oxide layer 38 contact opening 40 first conductive layer 42 first hemispherical granular silicon layer 44 second dielectric layer 46 spacer (second 48 second hemispherical granular silicon layer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-9-36322 (JP, A) JP-A-8-306882 (JP, A) JP-A-6-112430 (JP, A) JP-A-5-302 129548 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108

Claims (15)

(57) [Claims] A step of providing a semiconductor substrate; a step of forming a first dielectric layer on the substrate; a step of forming a silicon nitride layer on the first dielectric layer; Forming an oxide layer on the layer; patterning the oxide layer, the silicon nitride layer and the first dielectric layer to form a contact opening exposing a specific region of the semiconductor substrate; Laminating a conductive layer on the oxide layer and in the contact opening to form an electrical connection with the specific region of the substrate; and forming a first hemispherical particle on the first conductive layer. A step of forming a silicon layer; a step of forming a second dielectric layer on the first hemispherical granular silicon layer; the second dielectric layer, the first hemispherical granular silicon layer, and the first Pattern the conductive layer Exposing a portion of the oxide layer; forming a second conductive layer on the second dielectric layer, the first conductive layer and the oxide layer; and forming a second conductive layer on the second conductive layer. Forming a second hemispherical granular silicon layer, and removing portions of the second conductive layer and the second hemispherical granular silicon layer located on the oxide layer and the second dielectric layer. Exposing the oxide layer and the second dielectric layer to remove the second conductive layer and a part of the second hemispherical granular silicon layer from the second dielectric layer and the first dielectric layer.
A method of forming a lower electrode of a capacitor, the method comprising: fixing the remaining dielectric layer to the conductive layer; and removing the second dielectric layer and the oxide layer. 2. The method according to claim 1, wherein the step of forming the first conductive layer includes a low pressure chemical vapor deposition method. 3. The method according to claim 1, wherein the step of forming the second conductive layer includes a low pressure chemical vapor deposition method. 4. The method of claim 1, wherein forming the first hemispherical granular silicon layer comprises low pressure vapor deposition. 5. The method of claim 1, wherein forming the second hemispherical granular silicon layer comprises low pressure vapor deposition. 6. The method of claim 1, wherein removing the oxide layer, the second conductive layer, and the second hemispherical granular silicon layer comprises an anisotropic etching method. 7. The step of removing the second dielectric layer,
The method of claim 1, comprising the use of a hydrofluoric acid solution. 8. The step of removing the second dielectric layer,
2. The method of claim 1, further comprising the use of gas-phase hydrogen fluoride.
The method described in. 9. The step of removing the second dielectric layer,
The method of claim 1, comprising the use of reactive ion etching. 10. The method according to claim 1, wherein the specific region is a source / drain region of a transistor. 11. The step of forming the first conductive layer,
The method of claim 1 including a stack of implanted polysilicon. 12. The step of forming the second conductive layer,
The method of claim 1 including a stack of implanted polysilicon. 13. The method of claim 1, wherein forming the first dielectric layer comprises stacking silicon oxide. 14. The method of claim 1, wherein forming the second dielectric layer comprises laminating a boron phosphorus silicate glass. 15. The method of claim 1, wherein the step of forming an oxide layer comprises a stack of boron phosphorus silicate glass.