GB2337159A - Method for manufacturing capacitor lower electrode - Google Patents
Method for manufacturing capacitor lower electrode Download PDFInfo
- Publication number
- GB2337159A GB2337159A GB9809770A GB9809770A GB2337159A GB 2337159 A GB2337159 A GB 2337159A GB 9809770 A GB9809770 A GB 9809770A GB 9809770 A GB9809770 A GB 9809770A GB 2337159 A GB2337159 A GB 2337159A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- forming
- dielectric layer
- conductive layer
- hemispherical grained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
Abstract
A method for forming the lower electrode of a DRAM stacked capacitor comprising the steps of forming a first dielectric layer 34, a silicon nitride layer 35 and an oxide layer 36 over a substrate 30. Then, a first conductive layer 40 is formed in an opening 38 making electrical contact with a specified region of the substrate 30. Next, a first hemispherical grained silicon layer 42 and a second dielectric layer 44 are formed over the first conductive layer 40. Thereafter, the second dielectric layer 44, the first hemispherical grained silicon layer 42 and the first conductive layer 40 are patterned. Subsequently, a second conductive layer 46 and a second hemispherical grained silicon layer 48 are formed over the whole substrate structure. Next, portions of the second hemispherical grained silicon layer 48 and the second conductive layer 46 lying above the oxide layer 36 and the second dielectric layer 44 are removed. Finally, the second dielectric layer 44 is removed to expose the first hemispherical grained silicon layer 42. This invention avoids the damaging effects to the first hemispherical grained silicon layer 42 caused by the etching back operation, and prevents the formation of micro-bridges that may erroneously link up adjacent lower electrodes.
Description
2337159 METHOD FOR MANUFACTURING CAPACITOR'S LOWER ELECTRODE BACKGROU,\iD
OF THE
Field of Invention
The present invention relates to a method for manufacturina semiconductor 0 device. More particularly, the present invention relates to a method for manufacturing the lower electrode of a capacitor.
io Description of Related Art
Dynamic random access memory (DR-AIM) is a device for storing digital data. Si-nce DR-AMs make use of a capacitor to store data, the capacitance of a DRAIN1 capacitor should be sufficiently large so that data retention time can be longer. With the advent of ultra-large semiconductor integration (ULSI), the size of each memory cell in a DRAIM is reduced. Consequently, the electrode surface area of a capacitor must somehow be increased in order to compensate for the drop in capacitance. For example, a hemispherical grained silicon (HSG) layer is deposited over an electrode plate of the capacitor to increase its surface area.
Figs. 1A through IF are cross-sectional views showing the progression of manufacturm'g steps in producing the lower electrode of a capacitor according to a conventional method. First, as shown in Fig. IA, a semiconductor substrate 10 having field oxide layers 12 defining a device region is provided. Details of the devices within the device region are not shown in the figure. A dielectric layer 14 is formed over the substrate 10, and contact windows 16 are formed in the dielectric layer 14
2 exposing one of the sourceldrain region (not shown in the figure) of a transistor within W the device region.
Next, as shown in Fig. IB, a conductive layer 18 is deposited over the dielectric layer 14 and into the contact openings 16 making electrical connection with the source/drain rezion. The conductive layer 18 can be, for example, an ion-doped polysilicon layer deposited by a low-pressure vapor deposition process. Then, a cap dielectric layer 22 is deposited over the conductive layer 18 using, for example, a chemical vapor deposition method. The cap dielectric layer 22 can be made from, for example, borophosphosilicate glass (BPSG). Thereafter, photo lithographic and io etching n g processes are used to pattern the cap dielect 'c layer 272 and the conductive layer 18, finally forming the structure as shown in Fig. IB.
Next, as shown in Fig. 1 C, a layer of ion-doped polysilicon is deposited over the whole substrate structure using, for example, a low-pressure chemical vapor deposition (LPCVD) method. Thereafter, the polysilicon layer is etched back to form spacers over the slidewalls of the cap dielectric layer 29- and the conductive layer 18 using, example, an anisotropic etching method.
Next, as shown in Fig. ID, the cap dielectric layer 22 is removed to expose the conductive layer 18. The cap dielectric layer 22 is removed, for example, by a reactive ion etching (RIE) method employing gaseous hydrogen fluon'de or hydrofluoric acid solution.
Next, as shown in Fig. IE, a hemispherical grained silicon layer 26 is formed over the whole substrate structure including the conductive layer 18, the dielectric layer 14 and the spacers 24. The hemispherical grained silicon layer 26 can be deposited, 0 for example, by a low pressure vapor deposition (LPCVD) method using a silane S1H4 Z> 3 or Si:R, as the source of reactive gas. The deposition of hemispherical arained silicon is preferably conducted at a temperature between the growth of amorphous s 'con and the aro,.,,,-th of polysilicon.
Next, as shown in Fig. IF, the hemispherical gralned silicon laver 26 abovel the dielectric layer 14 is removed using, for example, an anisotropic etching back operation. The conductive layer 18, the spacers 24 and the residual hemispherical grained silicon laver 26 toaether constitute the lower electrode of a capacitor. The reason for removing the portion of hemispherical grained polysilicon layer above the dielectric layer 14 is for preventing any electrical connection between two adjacent conductive io layers 18. In other words, avoiding any damage to the semiconductor device caused by the electrical connection between any two lower electrodes of adjacent capacitors- However, the whole hemispherical grained silicon layer 26 'Is exposed to the etchants when portions of the hemispherical layer 26 that lies over the dielectric layer 14 is removed in an etching back operation- Consequently, the remaininc, hemispherical gralned silicon layer 26 will be damaged as--- well. Damage to that portion of the hemispherical grained silicon layer 26 that lies above the conductive layer 18 is especially serious, and may easily lead to leakage current firom the subsequently deposited dielectric layer. Therefore, the etching operation must be carefully controlled in order to avoid too much damage to the hemispherical grained silicon layer 26.
Furthermore, if the back etching operation is not properly controlled, there may be residual electrical connection called micro-bridges linking up adjacent lower 0 -1 electrodes. These micro-bridges may cause short-circuiting path damaging both 0 1 adjacent capacitors.
4 In light of the forecoine, there is a need for improving the method of form' 1 ing W C 0 the hemispherical grained silicon layer.
SLMMARY OF THE I7N7VENTION Accordingly, the present invention Is to provide a method for manufacturin. the lower electrode of a capacitor such that the over- etching of hemispherical grained silicon layer and the formation of micro- bridges in a conventional fabricating method are prevented.
To achieve these and other advantaces and in accordance with the purpose of the io invention, as embodied and broadly described herein, the invention provides a method for manufacturina the lower electrode of a capacitor. The method comprises-the steps of providing a semiconductor substrate, and then formine, a first dielectric layer over the substrateNext, a silicon nitride layer is formed over the first dielectric layer, and then, an oxide layer is formed over the silicon nitride layer. Thereafter, the oxide layer, the silicon nitride layer and the first dieleciric layer are patterned to form a contact opening exposing a spec ied region of the substrate.
In the subsequent step, a first conductive layer is deposited over the oxide layer and into the contact opening making electrical connection with the specified region of 0 the substrate. Next, a first hemispherical grained silicon layer is formed over the first 20 conductive layer, and then a second dielectric layer is formed over the first hemispherical grained silicon layer. Then, the second dielectric layer, the first hemispherical grained silicon layer and the first conductive layer are patterned to expose a portion of the oxide layer. After that, a second conductive layer is formed over the second dielectric layer, the first conductive layer and the oxide layer.
Thereafter, a second hemispherical grain silicon layer is formed over the second conductive layer. Portions of the second conductive layer and the second hemispherical grained layer that lies above the oxide layer and the second dielectric layer are then removed to expose portions of the oxide layer and the second dielectric layer. However, portions of the second conductive layer and the second hemispherical grained silicon layer on the sidewalls of the second dielectric layer and the first conductive layer are retained. Finally, the second dielectric layer and the oxide layer are removed and the lower electrode of a capacitor is formed. The lower electrode is made up of the second hemispherical grained silicon layer, the second conductive layer, the first hemispherical grained silicon laver and the first conductive layer.
The invention uses the second dielectric layer as a mask for protecting the first hemispherical grained silicon!ayer against etching back operation so that any possible damages to the first hemispherical grained silicon layer can be avoided. Hence,,eakae,e current forn subsequently deposited dielectric layer above the lower electrode of a capacitor can be prevented.
In another aspect of this invention, the etching back operation of the first hemispherical grained silicon layer can be effectively controlled so that micro-bridge formation between lower electrodes are eliminated.
In yet another aspect of this invention, the removal of the oxide layer can increase the surface area of the lower electrode, thereby increasing the capacitance of the capacitor.
It is to be understood that both the foregoing general description and the following, detailed description are exemplary, and are to provide further explanation of the invention as claimed.
6 BRIEF DESCRIPTION OF THE MAWINGS
The accompanying drawings are included to provide a further understandin. of the invention, and are incorporated in and constitute a part of this 0 on. 1 specl icati The drawings 'Illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention- In the drawings,
Flas. IA through IF (Prior Art) are cross-sectional views showing the progression of manufacturing steps in producing the lower electrode of a capacitor according to a conventional method. and Figs. 2A through 2D are cross-sectional views showing the progression of manufacturing steps in producing the lower electrode of a capacitor accordinc, to one preferred embodiment of this invention.
DESCRIPTION OF THE PREFERRED Ei\/úBODLvENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illusirmed in -e accompanying drawings. Wherever possible, the same reference numbers are used in the drawicys and the description to refer to the same or like parts.
Flas. 2A throuah 21) are cross-sectional views showincr the progression of CP _n manufacturing steps in producing the lower electrode of a capacitor according to one preferred embodiment of this invention. First, as shown in FIR. 2A, a semiconductor substrate 30 having field oxide layers 32 defining a device region is provided. Details of the devices within the device region are not shown in the figure. Next, a dielectric layer 34, for example, a silicon oxide layer, is formed over the whole substrate structure, and then a silicon nitride layer 35 is deposited over the dielectric layer 34. Thereafter, 7 ide layer 36 is formed over the silicon nitride laver 35. The oxide layer 36 can be an oxl _) 1 1 made, for example, from borophosphosilicate glass (BPSG). In the subsequent step, photolithographic and etching processes are used to pattern the oxide layer 36, the silicon nitride layer and the dielectric layer 34. Consequently, contact openings 38 that expose a source/drain region of a transistor within the device region (not shown in the W fiaure) are formed.
Next, as shown in Fig. 2B, a conductive layer 40 is deposited over the oxide layer 36 and into the contact openings 38 making electrical connection with the source/drain region of the transistor. The conductive layer 40 can be an ion-doped io polysilicon layer formed using, for example, a low-pressure chemical vapor deposition (LPCVD) method. Thereafter, a hemispherical grained silicon layer 42 is formed over the conductive layer 40. The hemispherical grained silicon layer 42 can be deposited, for example, by a low pressure vapor deposition (LPCVD) method using a si- lane 51H, or SI,'-- as the source of reactive gas. The deposition of hemispherical grained silicon ij is preferably conducted at a temperat-ure bet---ween the growth of amorphous silicon and the crol.x,-th of polysilicon. Next, a cap dielectric layer 44, for example, a borophosphosilicate glass layer, is deposited over the hemispherical grained silicon layer! 42 using a chemical vapor deposition method, for example- Subsequently, photolithographic and etching processes are used to pattern the cap dielectric 44, the hemispherical grained silicon layer 42 and the conductive layer 40 exposing a portion of the oxide layer 36. Finally, a structure as shown in Fig. 2B is obtained.
Next, as shown in Fig. 2C, a conductive layer 46 made from an ion-doped polysilicon material is deposited over the whole substrate structure including the cap dielectric layer 44 and the oxide [aver 36 using, for example, a low- pressure chemical 8 vapor deposition method. Thereafter, another hemispherical grained silicon layer 48 Is 0 formed over the conductive layer 46 using the same method as in forming the hemispherical grained silicon layer 42.
0 Next, as shown in Fig. 2D, the hemispherical grained silicon layer 48 and the CP conductive layer 46 are etched back using, for example, an anisotropic etching method, After the etchine, back operation, the conductive layer 46 will turn into a spacer structure over the sidewalls of the dielectric layer 44 and the conductive layer 40, and exposing a portion of the oxide layer 36, Since an anisotropic etching back operation 0 W is employed, portions of the hemispherical grained silicon layer 48 that forms over the io conductive spacers 46 are retained. In the subsequent step, the cap dielectric layer 44 is removed until the hemispherical grained silicon layer 42 is exposed. The cap dielectric layer 44 is removed, for example, by a reactive ion etching (RIE) method employing gaseous hydrogen fluoride or hydrofluoric acid solution. Since the oxide layer 36 is composed of the same material as the cap dielectric layer 44, the oxide layer u 36 will also be removed in the RIE as well. Up to this stage, the lower electrode of a capacitor, which comprises the hemispherical grained silicon layer 42, the hemispherical grained silicon layer 48, the conductive layer 40 and the conductive layer 46, is formed.
This invention uses the cap dielectric layer 44 as a mask for protecting the 20 hemispherical grained silicon layer 42 against etching back operation such that damages to the hemispherical grained silicon layer are minimized. Hence, leakage current &om C) subsequently deposited dielectric layer above the lower electrode of a capacitor can be prevented.
9 Anothel- aspect of this invention is the effective control of etchin. the hemispherical grained silicon laver 48 so that micro-bridaes between lower electrodes are rarely formed.
A third aspect of this invention is that the removal of the oxide layer can increase the surface area of the lower electrode. Therefore, the capacitance of the capacitor can be increased.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
0
Claims (15)
1. A method for forming the lower electrode of a capacitor comprisi providing a semiconductor substrate,. forming a first dielectric layer over the substrate.
forming a silicon nitride layer over the first dielectric layerforming an oxide layer over the silicon nitride layer- patterning the oxide laver, the silicon nitride layer and the first dielectnic layer to form a contact opening exposing a specified region of semiconductor substrate.
depositing a first conductive layer over the oxide layer and nto the contact opening making electrical connection with the specified region in the substrate.
forming a first hemispherical grained silicon layer over the first conductive layer; forming, a second dielectric layer over the first hemispherical grained silicon layer; patterni ing the secord dielectric layer, the first hemispherical a aLined silicon layer and the first conductive layer to expose a portion of the oxide layer, for-mina a second conductive layer over the second dielectric layer, the first conductive layer and the oxide layer; forming a second hemispherical grained silicon layer over the second conductive layer; removing a portion of the second conductive layer and the second hemispherical grained silicon layer that lies above the oxide layer and the second dielectric layer to expose the oxide layer and the second dielectric layer, and resulting Lia a portion of the second conductive layer and the second hemispherical grained silicon layer that remains attached to the sidewalls of the second dielectric layer and the first conductive layer., and removina the second dielectric layer and the oxide layer.
2. The method of claim 1, wherein the step of forming the first conductive layer 3 includes a low-pressure chemical vapor deposition method.
3. The method of claim 1, wherein the step of forming the second conductive W layer includes a low-pressure chemical vapor deposition method.
4. The method of claim 1, wherein the step of formina the first hemispherical grained silicon layer includes a low-pressure chemical vapor deposition method.
5. The method of claim 1, wherein the step of forming the second hemispherical grained silicon layer includes a low-pressure chernical vapor deposition method.
6. The method of claim 1, wherei n the step of removing the oxide layer, the second conductive layer and the second hemispherical a ained silicon layer an anisotropic etching method.
7. The method of claim 1, wherein the step of removing the second dielectric layer includes using hydrofluoric acid solution.
8. The method of claim 1, wherein the step of removing the second dielectric layer includes using, gaseous hydrogen fluoride.
9. The method of claim 1, wherein the step of removing the second dielectric 20 layer includes using a reactive ion etching method.
10. The method of claim 1, wherein the specified region is a source/drain region of a transistor.
11. The method of claim 1, wherein the step of forming the first conductive layer includes depositing ion-doped polysilicon.
Z:1
12. The method of claim 1, wherein the step of forming the second conductive [aver includes depositing ion-doped polysilicon.
1 W 1
13. The method of claim 1, wherein the step of forming the first dielectric layer depositing silicon oxide.
14. The method of claim 1, wherein the step of formin=g the second dielectric layer incl
15. A method for formincr a lower electrode of a capacitor, substantially as hereinbefore described with reference to andlor substantially as illustrated in any one of or any combination of Figs. 2A to 2D of the accompanying drawings.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9809770A GB2337159B (en) | 1998-02-07 | 1998-05-07 | Method for manufacturing capacitor's lower electrode |
| DE19823253A DE19823253C1 (en) | 1998-02-07 | 1998-05-26 | Capacitor lower electrode is produced especially for a DRAM capacitor |
| FR9806657A FR2774804B1 (en) | 1998-02-07 | 1998-05-27 | METHOD FOR FORMING THE LOWER ELECTRODE OF A CAPACITOR |
| JP10146282A JP2936326B1 (en) | 1998-02-07 | 1998-05-27 | Method of manufacturing lower electrode of capacitor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW087101622A TW374242B (en) | 1998-02-07 | 1998-02-07 | Method for manufacturing an underside electrode of a capacitor |
| GB9809770A GB2337159B (en) | 1998-02-07 | 1998-05-07 | Method for manufacturing capacitor's lower electrode |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9809770D0 GB9809770D0 (en) | 1998-07-08 |
| GB2337159A true GB2337159A (en) | 1999-11-10 |
| GB2337159B GB2337159B (en) | 2000-12-06 |
Family
ID=26313614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9809770A Expired - Fee Related GB2337159B (en) | 1998-02-07 | 1998-05-07 | Method for manufacturing capacitor's lower electrode |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2936326B1 (en) |
| DE (1) | DE19823253C1 (en) |
| FR (1) | FR2774804B1 (en) |
| GB (1) | GB2337159B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2359926A (en) * | 1999-10-01 | 2001-09-05 | Nec Corp | Stacked capacitor memory structure which reduces short circuits due to dislodged hemispherical grains |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4731025B2 (en) * | 2001-02-07 | 2011-07-20 | Ｏｋｉセミコンダクタ株式会社 | Cylinder type capacitor and method of manufacturing cylinder type capacitor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5622889A (en) * | 1995-01-26 | 1997-04-22 | Samsung Electronics Co., Ltd. | High capacitance capacitor manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278091A (en) * | 1993-05-04 | 1994-01-11 | Micron Semiconductor, Inc. | Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node |
| KR970054170A (en) * | 1995-12-25 | 1997-07-31 |
-
1998
- 1998-05-07 GB GB9809770A patent/GB2337159B/en not_active Expired - Fee Related
- 1998-05-26 DE DE19823253A patent/DE19823253C1/en not_active Expired - Fee Related
- 1998-05-27 JP JP10146282A patent/JP2936326B1/en not_active Expired - Lifetime
- 1998-05-27 FR FR9806657A patent/FR2774804B1/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5622889A (en) * | 1995-01-26 | 1997-04-22 | Samsung Electronics Co., Ltd. | High capacitance capacitor manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2359926A (en) * | 1999-10-01 | 2001-09-05 | Nec Corp | Stacked capacitor memory structure which reduces short circuits due to dislodged hemispherical grains |
| US6426527B1 (en) | 1999-10-01 | 2002-07-30 | Nec Corporation | Semiconductor memory and method for fabricating the same |
| GB2359926B (en) * | 1999-10-01 | 2004-03-31 | Nec Corp | Semiconductor memory and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2936326B1 (en) | 1999-08-23 |
| GB2337159B (en) | 2000-12-06 |
| FR2774804A1 (en) | 1999-08-13 |
| FR2774804B1 (en) | 2000-08-11 |
| DE19823253C1 (en) | 1999-07-15 |
| JPH11238848A (en) | 1999-08-31 |
| GB9809770D0 (en) | 1998-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5677221A (en) | Method of manufacture DRAM capacitor with reduced layout area | |
| US5573968A (en) | Method for fabricating stacked capacitors of semiconductor device | |
| US6037219A (en) | One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications | |
| US5985676A (en) | Method of forming capacitor while protecting dielectric from etchants | |
| US5981334A (en) | Method of fabricating DRAM capacitor | |
| US5104821A (en) | Method for fabricating stacked capacitors in a DRAM cell | |
| US5770510A (en) | Method for manufacturing a capacitor using non-conformal dielectric | |
| US5913129A (en) | Method of fabricating a capacitor structure for a dynamic random access memory | |
| JP2905314B2 (en) | Method for manufacturing semiconductor device | |
| US5918123A (en) | Method for fabricating capacitor of semiconductor device | |
| US5346846A (en) | Method of manufacturing a highly integrated semiconductor device | |
| US20030183865A1 (en) | Capacitor structure and method for fabricating the same | |
| GB2337159A (en) | Method for manufacturing capacitor lower electrode | |
| US5874334A (en) | Method for fabricating DRAM capacitor | |
| GB2285338A (en) | Method for fabricating capacitor | |
| US6080633A (en) | Method for manufacturing capacitor's lower electrode | |
| US6191042B1 (en) | Method of forming node contact opening | |
| US6121109A (en) | Method of forming hemispherical grain polysilicon over lower electrode capacitor | |
| KR0154195B1 (en) | Storage electrode fabrication method of semiconductor device | |
| US7052956B2 (en) | Method for forming capacitor of semiconductor device | |
| US5877053A (en) | Method of fabricating DRAM cell with capacitor having multiple concave structure | |
| US6232240B1 (en) | Method for fabricating a capacitor | |
| KR0144422B1 (en) | Semiconductor device and manufacturing method | |
| US6080619A (en) | Method for manufacturing DRAM capacitor | |
| KR100370169B1 (en) | Method for manufacturing capacitor of semiconductor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030507 |