GB2285338A

GB2285338A - Method for fabricating capacitor

Info

Publication number: GB2285338A
Application number: GB9426360A
Authority: GB
Inventors: Yeong Jin Park
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1993-12-29
Filing date: 1994-12-29
Publication date: 1995-07-05
Anticipated expiration: 2014-12-29
Also published as: GB9426360D0; GB2285338B; KR0120547B1

Abstract

A method for fabricating a capacitor of a semiconductor device, capable of achieving an increase in effective surface area of a storage electrode in a limited area and thereby fabricating a semiconductor device having a very high integration degree. The method includes the steps of repeatedly forming a silicon layer doped with impurity ions and an undoped silicon layer at least once on a predetermined area where a storage electrode is to be formed, selectively etching the undoped and doped silicon layers, thereby forming a contact hole, forming an upper undoped silicon layer over the entire exposed surface of the resulting structure obtained after the formation of the contact hole, annealing the resulting structure obtained after the formation of the upper undoped silicon layer, and removing the doped silicon layer by use of an etch selectivity difference between the doped silicon layer and each of the undoped silicon layer. <IMAGE>

Description

METHOD FOR FABRICATING CAPACITOR The present invention relates to a method for fabricating a capacitor of a semiconductor device.

Recent high integration trend of semiconductor devices such as dynamic random access memories (DRAMs) involves inevitably an abrupt reduction in cell dimension. However, such a reduction in cell dimension results in a difficulty to form capacitors having a sufficient capacitance per cell to enable an operation of a semiconductor device.

In order to obtain the capacitance of a certain level or greater, it is very important to development sophisticated techniques and achieve the reliability of semiconductor devices.

For meeting such a demand, there have been proposed various three dimensional storage electrode structures. Among the known storage electrode structures, the pin structure has been widely used because its fabrication is relatively simple.

However, this pin structure involves an increase in the number of pins for obtaining a sufficient capacitance in spite of a reduced cell area. For such an increase in the number of pins, a chemical vapor deposition (CVD) oxide film and a conduction film should be repeatedly formed in an alternating manner to form a multilayer structure. As a result, the pin structure involves an increase in cost caused by an increase in the number of process steps and a degradation in yield caused by particles and defects generated at an increased rate due to frequent CVD process steps.

A feature of an arrangement to be described is that it provides a method for fabricating a capacitor, capable of achieving an increase in effective surface area of a storage electrode in a limited area and thereby fabricating a semiconductor device having a very high integration degree.

In a particular arrangement to be described by way of example a method for fabricating a capacitor of a semiconductor device, comprises the steps of: repeatedly forming a silicon layer doped with impurity ions and an undoped silicon layer at least one time on a predetermined area where a storage electrode to be formed; selectively etching the undoped and doped silicon layers, thereby forming a contact hole; forming an upper undoped silicon layer over the entire exposed surface of the resulting structure obtained after the formation of the contact hole; annealing the resulting structure obtained after the formation of the upper undoped silicon layer; and removing the doped silicon layer by use of an etch selectivity difference between the doped silicon layer and each of the undoped silicon layer.

A particular embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Figs. 1A to 1D are sectional views respectively illustrating steps in a method for fabricating a capacitor of a semiconductor device.

The method to be described is a technique for fabricating a storage electrode having a pin structure by forming a multi layer structure obtained by repeatedly alternating a doped polysilicon layer and an undoped polysilicon layer in a process chamber while controlling the injection amount of an impurity source gas, annealing the multilayer structure under a predetermined condition capable of sufficiently activating the impurity doped in the multilayer structure, for example, at a temperature of 6500C for 60 minutes in the case that the multilayer structure is doped with PH3, and selectively removing the doped layers of the multilayer structure by use of a wet etchant for a polysilicon layer etch In FIGS. 1A to lD, there are illustrated steps of the fabrication of the storage electrode in accordance with the embodiment of the present invention, respectively In accordance with the embodiment of the present invention, first, silicon layers 1, 11 and 111 doped with impurity ions and silicon layers 2 and 22 doped with no impurity ions are formed in an alternating manner over an insulating layer 4 formed on a silicon substrate 3 at a region where a storage electrode is to be formed, as shown in FIG. 1A. This formation of silicon layers is carried out in a single process tube. The number of alternating doped silicon layers and undoped silicon layers and the thickness of each layer can be appropriately adjusted. The illustrated case has a multilayer structure obtained by repeating the formation of alternating doped and undoped silicon layers three times.

In order to form a contact for an electrical connection between elements, the doped silicon layers 111, 11 and 1, the undoped silicon layers 22 and 2 and the insulating film 4 are then subjected to an etch using a lithography process, thereby forming a contact hole, as shown in FIG. 1B.

Over the entire exposed surface of the resulting structure, an undoped silicon layer 222 is then deposited, as shown in FIG. 1C. Using a mask for an electrode formation, the doped and undoped silicon layers on the insulating film 4 are etched, as shown in FIG. 1C.

Finally, the resulting structure is subjected to an annealing at a temperature of 650'C for an hour in an N2 atmosphere. The gas atmosphere and the temperature used at this time are appropriately determined depending on the use purpose. At this step, the impurity ions of the doped silicon layers 1, 11 and 11 are sufficiently activated without being diffused in the undoped silicon layers. For selecting an annealing condition satisfying such a requirement, a carefulness is needed. As the doped silicon layers are sufficiently activated, the etch selectivity of the doped silicon layers to the undoped silicon layers is increased.

Upon subjecting the multilayer structure to an etch for polysilicon layer, accordingly, only the doped-silicon layers can be selectively removed. The result obtained after completion of this etch step is shown in FIG. 1D. As shown in FIG. 1D, a storage electrode 10 having a pin-shaped structure is obtained. In order to obtain an improved electrical characteristic of the storage electrode, impurity ions may be doped in the undoped silicon layers. The doping of impurity ions may be achieved by carrying out flowing of POC13 at a high temperature to dope phosphorous (P) ions in the undoped silicon layers or by annealing the multilayer structure at a temperature of not less than 600-C such that the impurity ions from the doped silicon layers are diffused in the undoped silicon layers.

As apparent from the above description, the present invention provides a method for fabricating a capacitor, capable of forming a storage electrode having a desired number of pins only by forming simple silicon layers without forming a multilayer structure of insulating layers and polysilicon layers. Accordingly, it is possible to achieve a simplified fabrication and a reduction in cost.

Since the multilayer of doped and undoped silicon layers is formed in a single chamber, it is also possible to eliminate factors causing a degradation in yield due to generation of particles and defects at an increased rate and thereby greatly improve the yield. Moreover, a large capacitance can be obtained in a small cell area.

Accordingly, the operation characteristic of a semiconductor device finally obtained can be greatly improved.

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the invention as defined in the accompanying claims.

Claims

1. A method for fabricating a capacitor of a semiconductor device, comprising the steps of: repeatedly forming a silicon layer doped with impurity ions and an undoped silicon layer at least one time on a predetermined area where a storage electrode to be formed; selectively etching the undoped and doped silicon layers, thereby forming a contact hole; forming an upper undoped silicon layer over the entire exposed surface of the resulting structure obtained after the formation of the contact hole; annealing the resulting structure obtained after the formation of the upper undoped silicon layer; and removing the doped silicon layer by use of an etch selectivity difference between the doped silicon layer and each of the undoped silicon layer.

2. A method in accordance with claim 1, wherein the step of repeatedly forming the doped and undoped silicon layers is carried out at a temperature of 400 to 600" in a single process tube.

3. A method in accordance with claim 1, wherein the step of removing the doped silicon layer is carried out using a wet etchant.

4. A method in accordance-with any one of claims 1 to 3, further comprising the step of doping impurity ions in the undoped silicon layers after the removal of the doped silicon layer.

5. A method for fabricating a capacitor of a semiconductor device, substantially as described herein with reference to the accompanying drawings.

6. A capacitor of a semiconductor device when made by a method as claimed in any one of the preceding claims.