JP3252980B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a wiring and a contact hole.

[0002]

2. Description of the Related Art FIG. 3A shows a semiconductor device having a gate electrode as a wiring and a contact hole, which is manufactured by a first conventional example of the present invention called a self-aligned contact method. Is shown. In this first conventional example, Si
After forming the SiO ₂ film 12 as a gate oxide film on the surface of the element active region of the substrate 11, and a SiO ₂ film 14 for the polycide film 13 or polycrystalline Si film and the offset are sequentially stacked, these SiO ₂ Film 14 and polycide film 1
Is processed into a pattern of a gate electrode.

Thereafter, an SiO ₂ film 15 is deposited on the entire surface, and the entire surface of the SiO ₂ film 15 is etched back to form an S 2
The side wall made of the iO ₂ film 15 is
At the same time as forming on the side surface of the O ₂ film 14, a contact hole 17 reaching the diffusion layer 16 in the Si substrate 11 is opened. Then, an upper layer wiring that contacts the diffusion layer 16 through the contact hole 17 is formed by the polycrystalline Si film 18.

In such a first conventional example, the contact hole 1
No mask is required for opening the contact hole 7 and the contact hole 1 is not required.
7 can be opened in a self-aligned manner with respect to the polycide film 13. For this reason, if the interval between the polycide films 13 is set to the limit of lithography, a contact hole 17 smaller than the limit of lithography can be formed, so that a highly integrated semiconductor device can be manufactured.

FIG. 4 shows a semiconductor device having a gate electrode as a wiring and a contact hole, which is manufactured by a second conventional example of the present invention called a matching contact system. In this second conventional example, the polycide film 13
After the gate electrode is formed, the interlayer insulating film 21 and the reduced pressure CV
The SiN film 22 by the D method is sequentially laminated. Then, a contact hole 17 is formed in the SiN film 22 and the interlayer insulating film 21 by etching using a resist (not shown) as a mask, and an upper wiring is formed by the polycrystalline Si film 18.

[0006]

However, FIG. 3 (a)
In the first conventional example shown in FIG.
Most of the interlayer isolation film between the i layer 18, a SiO ₂ film 15 sidewall-shaped film quality is inferior to that formed by etching back polycrystalline polycide film 13 via the SiO ₂ film 15 The area where the Si film 18 faces is large.
For this reason, in the first conventional example, the yield of the interlayer breakdown voltage between the polycide film 13 and the polycrystalline Si film 18 is low, and the semiconductor device cannot be manufactured with a high yield.

Further, as shown in FIG. 3 (b), when there is a protrusion 13a or an abnormal pattern in the polycide film 13, the thickness of the side wall-shaped SiO ₂ film 15 formed by the etch back is reduced at this portion. Polycide film 13 and polycrystalline Si film 18
In this portion, the yield of the interlayer breakdown voltage is particularly low.

On the other hand, in the second conventional example shown in FIG.
The film quality of the N film 22 is dense, and pinholes are less likely to occur in the portion where the SiN film 22 and the interlayer insulating film 21 are laminated. For this reason, in the interlayer insulating film 21, a portion having poor film quality is formed in the contact hole 17 opened by etching.
Only the part that faces. However, since the area of this portion is small, the yield of the interlayer breakdown voltage between the polycide film 13 and the polycrystalline Si film 18 is high.

However, in the second conventional example, since the contact hole 17 is formed by etching using a resist as a mask, the contact hole 17 cannot be made smaller than the limit of lithography.
The contact hole 17 needs a margin for positioning. Therefore, in the second conventional example, a semiconductor device with a high degree of integration could not be manufactured.

[0010]

In the method of manufacturing a semiconductor device according to the present invention, the conductive film 13, the first insulating film 24, and the first coating film 25, which are sequentially laminated, are processed into a wiring pattern. A step of forming a second insulating film 26 having an etching characteristic different from that of the first coating film 25 over the entire surface after the processing, and a step of forming the second insulating film 26 covering the pattern. Forming a second coating film 27 having a different etching characteristic from that of the second insulating film 26 in a side wall shape on the side, and using the first and second coating films 25 and 27 as masks; The second insulating film 26 is etched to
Forming a contact hole 17 in the insulating film 26 of FIG.

[0011]

In the method of manufacturing a semiconductor device according to the present invention, when etching the second insulating film for forming the contact hole, the second insulating film on the side of the wiring is covered with the second coating film. And the first insulating film 24 on the wiring
Are also masked by the first coating film 25. Therefore, when forming the contact hole 17, the first and second insulating films 2 are formed.
Portions of the wirings 4 and 26 that cover the wiring are not etched, and the film quality of the first and second insulating films 24 and 26 can be maintained to prevent a decrease in the yield of interlayer breakdown voltage. .

Moreover, the side wall-shaped second coating film 27 can be formed in self-alignment with the wiring by etching back the entire surface after the deposition, and the contact hole 17 is formed in the side wall-shaped second cover film. Since the contact hole 17 is formed by etching using the coating film 27 and the like as a mask, the contact hole 17 can be formed in a self-aligned manner with respect to the wiring. Therefore,
If the distance between the wirings is set to the limit of lithography, the contact hole 17 is smaller than the limit of lithography.
Can be formed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention applied to the manufacture of a DRAM will be described below with reference to FIGS. Components corresponding to those of the first and second conventional examples shown in FIGS. 3 and 4 are denoted by the same reference numerals.

In this embodiment, as shown in FIG.
Si for element isolation is formed on the surface of the Si
An O ₂ film 23 is formed, and an SiO ₂ film 1 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 23.
Form 2 Then, a polycide film 13 or a polycrystalline Si film, an interlayer insulating film 24 which is a SiO ₂ film having a thickness of about 1000 ° and containing no impurities,
A polycrystalline Si film 25 of about 3000 ° is sequentially deposited.

Thereafter, the polycrystalline Si film 25 and the interlayer insulating film 2
4 and the polycide film 13 are continuously subjected to RIE using the same resist (not shown) having the same gate electrode pattern as a mask. Then, using the polycide film 13, the interlayer insulating film 24 and the polycrystalline Si film 25 of the gate electrode pattern as a mask, for example, phosphorus is applied at an energy of about 20 to 40 keV to about 1 × 10 ^{13 to} 5 × 10 ¹³ cm ^−2. The N type diffusion layer 16 is ion-implanted to a dose of
Is formed in the element active region.

Next, a PSG film or a SiO ₂ film containing no impurities is deposited to a thickness of several hundred to several thousand ＣＶＤ by a CVD method, and a SiN film is deposited to a thickness of several hundred Å by a low pressure CVD method. Then, an interlayer insulating film 26 is formed of these two layers as shown in FIG. Then, a polycrystalline Si film 27 is deposited to a thickness of several hundred to several thousand Å by a low pressure CVD method. However,
In order to increase the degree of integration, it is preferable that the thickness of the polycrystalline Si film 27 be thin.

Next, RI is applied until the interlayer insulating film 26 is exposed.
E, the polycrystalline Si film 27 is anisotropically etched to form a polycrystalline Si film 27 on the side of the interlayer insulating film 26 covering the polycide film 13 and the like, as shown in FIG. Leave.

Then, RIE is performed on the interlayer insulating film 26 using the polycrystalline Si film 27 as a mask, and a contact hole 17 reaching the diffusion layer 16 is opened in a self-aligned manner with the polycide film 13 and the like. At this time, even if the interlayer insulating film 26 on the polycrystalline Si film 25 is etched, the polycrystalline Si film 2
5 serves as a stopper, so that the interlayer insulating film 24 is not etched. That is, the polycrystalline Si film 25 serves as a mask for the interlayer insulating film 24.

After that, the diffusion layer 16 and the polycrystalline Si film 27,
25, the polycrystalline Si film 28 is
It is deposited to a thickness of several hundreds of mm by the D method. Then, the polycrystalline Si films 28, 27, 2 are formed by ion implantation or pre-deposition.
After doping 5 with phosphorus or arsenic, a resist 29 is drawn out on the polycrystalline Si film 28 and processed into an electrode pattern.

Next, the polycrystalline Si films 28, 27 and 25 are sufficiently anisotropically etched using the resist 29 as a mask to store the capacitors constituting the memory cells as shown in FIG. An extraction electrode for the node electrode and an extraction electrode for the bit line are formed. Thereafter, the DRAM is completed through conventionally known steps.

In this embodiment as described above, the contact hole 1
During the RIE of the interlayer insulating film 26 for opening the holes 7, the polycrystalline Si films 27 and 25 form the interlayer insulating films 26 and 24.
Is masked. Therefore, the portions of the interlayer insulating films 26 and 24 covering the polycide film 13 are not etched, and the film quality of the interlayer insulating films 26 and 24 in this portion does not deteriorate.

Since the portions of the interlayer insulating films 26 and 24 covering the polycide film 13 are not etched, as shown in FIG. Does not become thin in this portion. Therefore, the yield of the interlayer breakdown voltage between the polycide film 13 and the polycrystalline Si films 28, 27, 25 is high.

[0023]

In the method of manufacturing a semiconductor device according to the present invention, when forming a contact hole, it is possible to prevent a decrease in the yield of the interlayer withstand voltage of the insulating film covering the wiring and to reduce the yield below the lithographic limit. Since the contact hole can be formed, a highly integrated semiconductor device can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing one embodiment of the present invention.

FIG. 2 is a side sectional view for explaining one embodiment.

3A and 3B show a first conventional example of the present invention, in which FIG. 3A is a side sectional view of a DRAM manufactured by the first conventional example, and FIG. 3B is a side sectional view for explaining the first conventional example; It is.

FIG. 4 is a side sectional view of a DRAM manufactured in a second conventional example of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 13 Polycide film 17 Contact hole 24 Interlayer insulating film 25 Polycrystalline Si film 26 Interlayer insulating film 27 Polycrystalline Si film

Claims (1)

(57) [Claims] A step of processing a conductive film, a first insulating film, and a first coating film, which are sequentially laminated, into a wiring pattern; and after the processing, the first coating film Forming a second insulating film having different etching characteristics on the entire surface; and forming a second insulating film on a side portion of the second insulating film covering the pattern,
Forming a second covering film having an etching characteristic different from that of the second insulating film in a side wall shape; and etching the second insulating film using the first and second covering films as a mask. Forming a contact hole in the second insulating film.