315510 A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明（1 ) 本發明有關於一種半導體記億裝置及其之製造方法， 更待別地，傜有關於具有由一選擇半球形粒狀矽層構成之 圓柱形儲存電極之半導體記億裝置的電容器及其製造方法 〇 隨著如動態隨機存取記億體DRAM般之半導體記憶裝置 的集積密度增加，由一電晶體和一細胞電容器所構成之一 單胞Un i t ce丨丨）所佔用的面積像逐漸減少。由於一記憶 細胞之面積減少所引起之細胞電容的減少嚴重限制該DRAM 的集積密度。細胞電容的減少進一步使從該記憶細胞讀取 資料的能力.變壞、增加軟錯誤率、妨礙一裝置在低電壓狀 態的蓮作、及使恢復特性變壞，因此增加電流的消耗。因 此*由細胞電容之減少所引起的問題應該被解決俾可獲得 高密度半導體記億裝置集積度。 目前傺有用於利用具有高介電常數之材料形成一介電 薄膜及用於形成一薄介電薄膜俾可增加細胞電容的方法。 然而，該用於以一具有高介電常數之材料形成該介電薄膜 的方法大致上具有漏電流大且崩潰電壓低的問題，而該用 於形成薄介電薄膜的方法則因漏電流增加而使得該半導髏 裝置的可靠度變壞。 因此，一種藉著增加該電容器電極之表面面積來增加 電容的方法已被建議。作為一典型例子，如果具有半球形 形狀顆粒的HSG矽層係被選擇地形成於一低霄極表面上的 話，輕易地增加一低電極的表面面積以提升其之電容傜有 可能的。 ' -4 - 本紙張尺度逍用中國國家標準（CNS ) A4规格（210X297公釐） I—h — u——f -裝-- (請先閲讀背面之注意事項再填寫本頁)315510 A7 B7 Central Government Bureau of Economic Affairs Employee Consumer Cooperation Du Printing 5. Description of the invention (1) The present invention relates to a semiconductor billion memory device and its manufacturing method, more specifically, Tong has a choice of a hemisphere Capacitor of semiconductor memory device with cylindrical storage electrode composed of granular silicon layer and its manufacturing method. As the packing density of semiconductor memory devices like dynamic random access memory DRAM increases, it consists of a transistor and a cell The area occupied by the unit cell formed by the capacitor (Un it ce 丨 丨) gradually decreases. The reduction in cell capacitance due to the reduction in the area of a memory cell severely limits the accumulation density of the DRAM. The reduction in cell capacitance further deteriorates the ability to read data from the memory cell. It deteriorates, increases the soft error rate, prevents a device from operating in a low-voltage state, and deteriorates the recovery characteristics, thereby increasing current consumption. Therefore, the problems caused by the reduction of the cell capacitance should be solved so as to obtain a high-density semiconductor high-density device. At present, there are methods for forming a dielectric thin film using a material having a high dielectric constant and a method for forming a thin dielectric thin film to increase the cell capacitance. However, the method for forming the dielectric film with a material having a high dielectric constant generally has problems of large leakage current and low breakdown voltage, and the method for forming a thin dielectric film increases due to leakage current As a result, the reliability of the semi-conductive skull device is deteriorated. Therefore, a method of increasing the capacitance by increasing the surface area of the capacitor electrode has been suggested. As a typical example, if an HSG silicon layer having particles of hemispherical shape is selectively formed on a low-electrode surface, it is possible to easily increase the surface area of a low-electrode to increase its capacitance. '-4-This paper standard uses Chinese National Standard (CNS) A4 specification (210X297mm) I—h — u——f -installed (please read the precautions on the back before filling this page)
、tT 經濟部中央梂準局—工消费合作社印策 A7 _^_B7__ 五、發明説明（2 ) 第1至3圖偽用以說明根據一習知技術之用於選擇地 只形成該HSG矽層於該半導髏裝置之電容器之低電極中之 方法的剖視圖。 請參閲第1圖所示，一絶緣薄膜，例如，一氣化薄膜 3係被形成於一半導體基體1上且傺被定以圔型來形成一 接觸孔Fu，該接觸孔Fu暴露該半導體基髏1的一預定面積 〇 請參閲第2圖所示，一非晶質矽僳被沉積在被顯示於 第1圖中的最終結構上侔形成充填該接觸孔hi的一導電層 5 0 請參閲第3圖所示，用於覆蓋該接觸孔hi的一低電極 7係藉著將該導電層5定以圖型來被形成且一 HSG層9係 被形成在該低電極7的表面上。在這情況中，該低電極7 應該在非晶質狀態且其之雜質濃度應該被增加以降低其之 電阻。 然而，當該低電極7的雜質濃度被增加時，雜質傜被 擴散至接觸該低電極7的半導體基體1内。據此，該半導 體基體1的雜質濃度，那就是，其之源極面積或者汲極面 積傜被改變，因此使該電晶體的特性變壊。 如上所述，該半導髏基醱1之源極和汲極面積的雜質 濃度偽直接受該下電極7的雜質濃度影響。因此，該T轚 極7的雜質濃度越低，該源極和汲極面積之雜質濃度在後 面之熱處理期間之改變的董越少。然而，當該下電極7的 雜質濃度被降低時，一現象偽發生於一 MOS電容器結構， 本紙張尺度適用中鬮國家揉率（CNS > A4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 315510 A7 經濟部中央橾準局員工消費合作社印製 B7 五、發明説明（3 ' 那就是，電容根據被施加至該電容器之電極之電壓之大小 改變的現象發生。待別地，在該HSG薄膜9被形成在該下 電極7之表面上的電容器結構中，該電容之改變的童增加 得比在没有該HSG薄膜9之一般電容器結構中的多。這是 因為被形成於構成該HSG薄膜9之半球形顆粒的空乏層互 相重疊，其增加一實際空乏層的寬度。當該一種現象發生 時，由於電容像根據被施加至該電容器之電極的電壓改變 ，一最小電容Cm in和一最大電容Cmax存在於某電壓範圍之 内。 第4圖偽顯示當一 HSG層被形成於該電容器之低電搔 上時和當一 HSG層没有被形成於該電容器之低電極上時， 根據一雜質摻雜濃度之Cmin和Cmax之改變的圖表。 在第4圖中，磷（P)傜被使用作為被摻雜於該低電極 中的雜質。在這裡，當無HSG層傺被形成於該低電極之表 面上時所獲得的Cmin/Cmax *以（)表示，係與當HSG 層像被形成於該低電極之表面上時所獲得的Cmin/Cmax ， 以（籲）表示，在PH3被使用作為一磷來源氣體及其之流 動速率分別改變至5,7,和15scem的條件下做比較。當該 HSG被形成於該低電極的表面上時，Cmin/Cmax僳隨著該 PH3之流動速率的降低而急速地降低，當無HSG層披形成 時，Cmin/Cmax傷不管該PH3之流動速率的改變而不急速 地降低。 根據以上的結果，形成一値具有新結構的低電極傺需 要的，在該新結構中，當HSG層被形成於該低電極表面上 -6 - 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） ------------F--Λ----装 --------訂 I-----ΛΊ » Ϊ r ϊ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央揉準局员工消费合作社印製 A7 B7 五、發明説明（為厂 時，Cfflin/Cmax偽不被降低。 本發明之一目的傺來提供一種半導體記億裝置的電容 器，其中，Cm in/Cmax之滿意的值能夠被獲得且雜質自該 電容器之低電極的擴散出來能夠被防止。 本發明之另一目的像來提供一種用於製造以上所述之 半導體記億裝置之電容器的方法。 為了達到第一目的，一種具有低電極之半導體記憶裝 置的電容器偽被提供，在其中，一第一導電層和一第二導 電層傜分別被沉積且一 HSG層像被選擇地形成於該低電極 的表面上，其中，該第一導電層傺由具有一第一雜質濃度 的一非晶質矽薄膜形成而該第二導電層僳由具有一第二雜 質濃度的一非晶質矽薄膜形成，該第二雜質濃度僳比該第 一雜質濃度高。 . 該等雜質最好僳磷（P)或者偽砷（As)。 . 一種具有低電極之半導體記億裝置的電容器係被提供 ’在其中，一第一導電層和一第二導電層像分別被沉積且 一HSG層偽被選擇地形成於該低電極的表面上，其中，該 第一導電層像由具有一第一雜質濃度的一多晶矽薄膜構成 而該第二導電層僳由具有一第二雜質濃度的一非晶質矽薄 膜構成，該第二雜質湊度傜比該第一雜質濃度高。 一結晶切除薄膜最好儀進一步被設置於該第一導電層 與該第二導電層之間。該結晶切除薄膜最好傺為一氧化層 0 為了逹到該第二目的，一種用於製造半導體記憶裝置 -7 - 本紙張又度適用中國國家橾準（CNS ) A4規格（210X297公釐） --------U,---^裝-------訂-----A 冰 *τ fc. ** (請先閲讀背面之注^^項再填寫本頁) A7 315510 ___B7___ 五、發明説明（S ) 之電容器的方法傜被提供，該方法包含如下之步驟：藉著 部份地蝕刻被形成於一半導體基體上的絶緣層來形成部份 地暴露該半導體基體的一接觸孔；分別形成一第一導電層 和一第二導電層於具有該接觸孔的半導體基體上；藉著將 該第二導電層和該第一導電層定以圖型來形成一低電極圖 型，在其中，一第一導電層圖型和一第二導電層圖型偽分 別被沉積；及藉由一選擇HSG形成過程來形成一HSG砂層 • 於該低電極圖型的表面上。該第一導電層最好像由具有一 第一雜質濃度的一非晶質矽薄膜形成，而該第二導電層最 好傜由具有一第二雜質濃度的一非晶質矽薄膜形成，該第 二雜質濃度僳比該第一雜質濃度高。該第一導電層可以由 具有一第一雜質濃度的一多晶矽薄膜形成，而該第二導電 層可以由具有一第二雜質濃度的^非晶質矽薄膜形成，該 第二雜質濃度傺比該笫一雜質濃度高。 一種用於製造半導體記億裝置之電容器的方法像被提 供，該方法包含如下之步驟：藉著部份地蝕刻被形成於一 半導體基體的絶緣層來形成部份地暴露該半導體基體的一 接觸孔；連绩地形成一第一導電層、一結晶切除薄膜、和 一第二導電層於具有該接觸孔的半導體基髏上；藉著將該 第二導電層、該結晶切除薄膜、和該第一導電層定以圖型 來形成一低電極圖型，在其中，一第一導電層圖型、一結 晶切除薄膜圖型、和一第二導電層圖型係連續被沉積；藉 由濕蝕刻被置放於該低電極圖型之第一與第二導電層圖型 之間的結晶切除薄膜圖型至一預定寛度來形成一側凹區域 -8 - 本紙張尺度逍用中國國家標準（CNS ) A4规格（210X 297公釐）~~ ~ ----K---:---C 裝-- (請先閏讀背面之注意事項再填寫本頁) 訂 Λ 經濟部中央標準局員工消費合作社印製 經濟部中央橾準局貝工消費合作社印袋 A7 ^^_ B7_一 五、發明説明（6 ) ;及透過一選擇HSG沉積法來形成一 HSG矽層於該第二導 電層圔型的表面上和於該側凹區域內。 該第一導電層最好僳由具有一第一雜質濃度的一多晶 矽薄膜形成，該結晶切除薄膜最好傜由一氧化薄膜形成， 而該第二導電層最好傜由具有一第二雜質濃度的非晶質矽 薄膜形成，該第二雜質濃度僳比該第一雜質濃度高。該氣 化薄膜傷可以由化學蒸氣沅積法（CVD)或者由熱氧化法來 形成。 用於形成該第一導電層的步驟最好係包含沉積具有一 第一雜質濃度之非晶質矽薄膜及透過熱處理結晶該非晶質 矽薄膜的步驟。 根據本發明，在具有該HSG砂層結構之電容器的低電 極中得到Cmiti/Cmax之滿足的值及防止雜質自該電容器之 低電極擴散出來傺有可能的。 本發明之以上目的和優點藉由配合附圖詳細描述其之 較佳實施例而像會變得更清楚，其中： 第1至3圖像用以說明根據習知技術之用於製造半導 體記憶裝置之電容器之方法的剖視圖； 第4圖僳顯示在形成一 HSG層於該電容器之低電極中 的情況中及在不形成該HSG層的一般情況中*根據雜質摻 雜濃度之Cisin/Cmax之改變的圖表； 第5至7圖傺用以説明本發明之第一實施例之用於製 造半導體記億裝置之電容器之方法的剖視圖； 第8至1◦圖傺用以説明本發明之第二實施例之用於 本紙張尺度逋用中國國家揉準（CNS ) Α4規格（210X297公釐） 《装—-----訂------ * ί 一锖先閲讀背面之注意事項再填寫本頁) 經濟部中央椟率局男工消費合作社印製 A7 B7 五、發明説明（，） 製造半導體記憶裝置之電容器之方法的剖視圖； 第1 1至1 3圖傈用以說明本發明之第三實施例之用 於製造半導體記億裝置之電容器之方法的剖視圖； 第1 4圖傷比較根據習知技術在該低電極中之 Cmin/Cmax與根據本發明在該低電極中之Cmin/Cmax的圖 表；及 第15圖係顯示根據該習知技術與本發明在該低電極 中之雜質濃度之絶緣區域中之崩潰電壓分佈的圖表。 於此後，本發明的較佳實施例傷配合該等附圖被詳細 描述。 在本發明中，為了防止雜質自一電容器擴散出來及為 了在具有一 HSG矽層之電容器中獲得一穩定的Cmi n/Cmax ，當形成一低電極時，具有一低雜質濃度的一矽層傷被形 成在接觸一矽基體之該電容器的一部份中，因此藉由抑制 該等雜質在一後面之熱處理期間的再擴散來防止一絶緣特 性和一電晶體持性的變壞*而然後具有一高雜質濃度的矽 層係被形成於具有一低雜質濃度的矽層上。 窨旃例1 第5至7圖傜用以描述本發明之第一實施例之一種藉 著選擇地只形成一 HSG矽層於一低電極上來製造半導體記 億裝置之電容器之方法的剖視圖。 請參閲第5圖所示，一絶緣層像被形成於一半導體基 體10上，在該半導體基體10上，如一電晶髏般的一次結構 係被形成。然後，暴露該半導體基體10之一部份的一接觸 -- 10 - 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ----i---1---C 裝-------訂------^ 私 ··s (请先閎讀背面之注意事項再填寫本頁) 經潦部中央揉準局員工消费合作社印裝 315510 五、發明説明u ) 孔h2，傜藉著利用一照相平販印刷法（Phot〇l ith〇sraPhy process)來形成一光致抗蝕圖型（P“t〇resist pattern) (圖中未示）於該絶緣層上，及藉著利用該光致抗蝕圖型 作為一蝕刻光罩以蝕刻該絶緣層俾形成一絶緣層圖型12 ’ 來被形成。 _參閲第6圖所示*在該光致抗蝕圖型被移去之後， 一第一導電層14僳藉著沉積具有一第一雜質濃度的一非晶 質矽薄膜於具有該接觸孔“的最終結構上來被形成俥降低 擴散至該半導體基體10之雜質的量*那就是，降低擴散至 如一電晶體之源極或者汲極區域般之有源區域（act ive region)之 雜質的量。然後，一第二導電層16傜藉著沉積 具有一第二雜質濃度的一非晶質矽薄膜來被形成，該第二 雜質濃度僳比該第一導電層14的第一雜質濃度高。'在這裡 ，磷（P)或者砷（As)能夠被使用作為雜質。 請參閲第7圖所示，由一第一導電層圖型14a和一第 二導電層圖型16a所構成的一低電極圖型傺藉著塗覆一光 致抗蝕材料於該第二導電層16上、形成一光致抗蝕圖型（ 圖中未示）、及利用該光致抗蝕圖型作為一蝕刻光罩來連 鑛蝕刻該第二導電層16和該第一導電層14，來被形成。 然後，一 HSG矽層22係藉著應用一選擇HSG處理來被 形成於包括該第一導電層圖型14a和該第二導電層圖型 16a之該低電極圖型的表面上，俥可形成具有其之增加表 面面積的低電極。然後，一介電薄膜（圖中未示）和一上 電極（圖中未示）傜被形成且一普遍的CMOS形成法偽被執 - -11 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----·----：---^ 裝— (請先閲讀背面之注意事項再填寫本頁) 訂、 TT Ministry of Economics Central Bureau of Industry and Commerce-Industry and Consumer Cooperative Institution A7 _ ^ _ B7__ V. Description of Invention (2) Figures 1 to 3 are used to illustrate that only the HSG silicon layer is selectively formed according to a known technique A cross-sectional view of the method in the low electrode of the capacitor of the semiconductor device. Please refer to FIG. 1, an insulating film, for example, a vaporized film 3 is formed on a semiconductor substrate 1 and is formed in a sigmoid shape to form a contact hole Fu, which exposes the semiconductor substrate A predetermined area of the skull 1 is shown in FIG. 2, an amorphous silicon layer is deposited on the final structure shown in FIG. 1 to form a conductive layer 5 filling the contact hole hi Referring to FIG. 3, a low electrode 7 for covering the contact hole hi is formed by patterning the conductive layer 5 and an HSG layer 9 is formed on the surface of the low electrode 7 on. In this case, the low electrode 7 should be in an amorphous state and its impurity concentration should be increased to reduce its resistance. However, when the impurity concentration of the low electrode 7 is increased, the impurity is diffused into the semiconductor substrate 1 contacting the low electrode 7. According to this, the impurity concentration of the semiconductor substrate 1, that is, its source area or drain area is changed, so that the characteristics of the transistor are changed. As described above, the impurity concentration of the source and drain areas of the semiconductor base 1 is virtually directly affected by the impurity concentration of the lower electrode 7. Therefore, the lower the impurity concentration of the T-electrode 7, the less the change in the impurity concentration of the source and drain areas during the subsequent heat treatment. However, when the impurity concentration of the lower electrode 7 is reduced, a phenomenon pseudo-occurs in a MOS capacitor structure. This paper scale applies to the national rubbing rate (CNS > A4 specification (210X297mm) (please read the back (Notes to fill out this page) 315510 A7 Printed by the Ministry of Economic Affairs, Central Bureau of Commerce and Industry Consumer Cooperative B7 5. Description of the invention (3 'That is, the phenomenon that the capacitance changes according to the magnitude of the voltage applied to the electrode of the capacitor Occurred. To be noted, in the capacitor structure where the HSG film 9 is formed on the surface of the lower electrode 7, the change in the capacitance increases more than in the general capacitor structure without the HSG film 9. This This is because the depletion layers formed on the hemispherical particles constituting the HSG film 9 overlap each other, which increases the width of an actual depletion layer. When this phenomenon occurs, the capacitance image changes according to the voltage applied to the electrodes of the capacitor , A minimum capacitance Cmin and a maximum capacitance Cmax exist within a certain voltage range. Figure 4 pseudo-shows that when an HSG layer is formed on the low voltage of the capacitor And when an HSG layer is not formed on the lower electrode of the capacitor, according to a graph of the change in the impurity doping concentration Cmin and Cmax. In Figure 4, phosphorus (P) is used as being doped Impurities in the low electrode. Here, Cmin / Cmax * obtained when no HSG layer is formed on the surface of the low electrode is represented by (), which is the same as when the HSG layer image is formed on the low electrode The Cmin / Cmax obtained on the surface is expressed as (Xu), when PH3 is used as a phosphorus source gas and its flow rate is changed to 5, 7, and 15 scem for comparison. When the HSG is formed On the surface of the low electrode, Cmin / Cmax decreases rapidly as the flow rate of the PH3 decreases. When no HSG layer is formed, the Cmin / Cmax injury does not change rapidly regardless of the change in the flow rate of the PH3 According to the above results, it is necessary to form a low electrode with a new structure. In this new structure, when the HSG layer is formed on the surface of the low electrode -6-This paper scale is applicable to the Chinese National Standard ( CNS) A4 specification (210X297mm) ------------ F-- Λ ---- 装 -------- 訂 I ----- ΛΊ »Ϊ r ϊ (Please read the precautions on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Ministry of Economic Affairs A7 B7 V. Description of the invention (When it is a factory, Cfflin / Cmax is not reduced. One of the purposes of the present invention is to provide a capacitor for a semiconductor billion device, in which a satisfactory value of Cmin / Cmax can be obtained and impurities Diffusion from the low electrode of the capacitor can be prevented. Another object of the present invention is to provide a method for manufacturing the capacitor of the semiconductor billion device described above. In order to achieve the first object, a capacitor of a semiconductor memory device with a low electrode is pseudo provided, in which a first conductive layer and a second conductive layer are separately deposited and an HSG layer image is selectively formed on the low On the surface of the electrode, wherein the first conductive layer is formed of an amorphous silicon film with a first impurity concentration and the second conductive layer is formed of an amorphous silicon film with a second impurity concentration , The second impurity concentration is higher than the first impurity concentration. . These impurities are best to be phosphorus (P) or pseudo-arsenic (As). . A capacitor of a semiconductor billion device with a low electrode is provided in which a first conductive layer and a second conductive layer are deposited separately and an HSG layer is pseudo-selectively formed on the surface of the low electrode , Wherein the first conductive layer image is composed of a polycrystalline silicon film with a first impurity concentration and the second conductive layer is composed of an amorphous silicon film with a second impurity concentration, the second impurity concentration Yi is higher than the first impurity concentration. A crystal removal film is preferably further disposed between the first conductive layer and the second conductive layer. The crystal removal film is preferably an oxide layer. 0 For the purpose of this second purpose, it is used to manufacture semiconductor memory devices-7-This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)- ------- U, --- ^ installed ------- order ----- A Bing * τ fc. ** (please read the note ^^ on the back before filling this page) A7 315510 ___B7___ Fifth, the invention description (S) of the capacitor method is provided, the method includes the following steps: by partially etching the insulating layer formed on a semiconductor substrate to form a partially exposed semiconductor substrate A contact hole; respectively forming a first conductive layer and a second conductive layer on the semiconductor substrate having the contact hole; by patterning the second conductive layer and the first conductive layer to form a low Electrode pattern, in which a first conductive layer pattern and a second conductive layer pattern are deposited separately; and a HSG sand layer is formed by a selective HSG formation process on the surface of the low electrode pattern . The first conductive layer is preferably formed by an amorphous silicon film having a first impurity concentration, and the second conductive layer is preferably formed by an amorphous silicon film having a second impurity concentration. The second impurity concentration is higher than the first impurity concentration. The first conductive layer may be formed of a polysilicon thin film having a first impurity concentration, and the second conductive layer may be formed of an amorphous silicon thin film having a second impurity concentration, the second impurity concentration is greater than the The first impurity concentration is high. A method for manufacturing a capacitor of a semiconductor billion device is provided. The method includes the steps of forming a contact partially exposing the semiconductor substrate by partially etching an insulating layer formed on the semiconductor substrate Hole; successively forming a first conductive layer, a crystal cut-out film, and a second conductive layer on the semiconductor substrate with the contact hole; by the second conductive layer, the crystal cut-out film, and the The first conductive layer is patterned to form a low electrode pattern, in which a first conductive layer pattern, a crystal-cut film pattern, and a second conductive layer pattern are continuously deposited; by wet Etching the crystal cut film pattern placed between the first and second conductive layer patterns of the low electrode pattern to a predetermined degree to form a concave region on one side-8 (CNS) A4 specification (210X 297mm) ~~~ ---- K ---: --- C pack-- (please read the notes on the back before filling in this page) Set the central standard of the Ministry of Economic Affairs Bureau employee consumer cooperatives print the shellfish of the central bureau of the Ministry of Economic Affairs Consumer Cooperative Printing Bag A7 ^^ _ B7_ 一 五. Description of the invention (6); and forming a HSG silicon layer on the surface of the second conductive layer by the selective HSG deposition method and in the undercut area . The first conductive layer is preferably formed of a polysilicon film having a first impurity concentration, the crystal removal film is preferably formed of an oxide film, and the second conductive layer is preferably formed of a second impurity concentration An amorphous silicon thin film is formed, the second impurity concentration is higher than the first impurity concentration. The vaporized film damage can be formed by chemical vapor deposition (CVD) or thermal oxidation. The step for forming the first conductive layer preferably includes the steps of depositing an amorphous silicon thin film having a first impurity concentration and crystallizing the amorphous silicon thin film by heat treatment. According to the present invention, it is possible to obtain a satisfactory value of Cmiti / Cmax in the low electrode of the capacitor having the HSG sand layer structure and to prevent impurities from diffusing out of the low electrode of the capacitor. The above objects and advantages of the present invention will become clearer by describing its preferred embodiments in detail with reference to the accompanying drawings, in which: the first to third images are used to illustrate the manufacture of semiconductor memory devices according to conventional techniques A cross-sectional view of the method of the capacitor; Figure 4 shows the change of Cisin / Cmax according to the impurity doping concentration in the case of forming an HSG layer in the low electrode of the capacitor and in the general case of not forming the HSG layer Figures 5 to 7 of Ye are used to explain the first embodiment of the present invention, a cross-sectional view of a method for manufacturing a capacitor of a semiconductor memory device; Figures 8 to 1 are used to illustrate the second embodiment of the present invention For example, this paper is used in the Chinese National Standard (CNS) Α4 specification (210X297mm) "installed ------ ordered ----- * ί 锖 first read the precautions on the back and then fill in This page) A7 B7 printed by the Male Workers ’Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy V. Description of the invention (,) A cross-sectional view of a method of manufacturing a capacitor for a semiconductor memory device; FIGS. 1 1 to 1 3 FIG. Three embodiments are used to manufacture semi A cross-sectional view of a method of recording a capacitor of a billion device; FIG. 14 shows a graph comparing Cmin / Cmax in the low electrode according to the conventional technology and Cmin / Cmax in the low electrode according to the present invention; It is a graph showing the breakdown voltage distribution in an insulating region with an impurity concentration in the low electrode according to the conventional technology and the present invention. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the present invention, in order to prevent impurities from diffusing out of a capacitor and to obtain a stable Cmin / Cmax in a capacitor with an HSG silicon layer, when forming a low electrode, a silicon layer with a low impurity concentration is damaged Is formed in a part of the capacitor that contacts a silicon substrate, and thus prevents deterioration of an insulating property and a transistor holding property by suppressing redistribution of the impurities during a subsequent heat treatment * and then has A silicon layer with a high impurity concentration is formed on the silicon layer with a low impurity concentration. Example 1 Figures 5 to 7 are used to describe a cross-sectional view of a method of manufacturing a capacitor for a semiconductor billion device by selectively forming only a HSG silicon layer on a low electrode in the first embodiment of the present invention. As shown in FIG. 5, an insulating layer image is formed on a semiconductor substrate 10 on which a primary structure like an electric crystal is formed. Then, expose a part of the semiconductor substrate 10 to a contact-10-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ---- i --- 1 --- C ------ Subscribe ------ ^ Private · s (please read the precautions on the back first and then fill out this page) Printed by the Central Committee of the Ministry of Industry and Commerce, Consumer Cooperatives 315510 V. Description of invention u ) Hole h2, a photoresist pattern (P "t〇resist pattern) (not shown) is formed on the insulating layer by using a photo-printing method (Photol ith〇sraPhy process) And formed by using the photoresist pattern as an etch mask to etch the insulating layer to form an insulating layer pattern 12 '. _Refer to FIG. 6 * in the photoresist After the etching pattern is removed, a first conductive layer 14 is formed by depositing an amorphous silicon thin film with a first impurity concentration on the final structure with the contact hole to reduce diffusion to the semiconductor substrate The amount of 10 impurities * that is, to reduce the impurities that diffuse into the active region (act ive region) like the source or drain regions of a transistor的 量。 The amount. Then, a second conductive layer 16m is formed by depositing an amorphous silicon thin film having a second impurity concentration, which is higher than the first impurity concentration of the first conductive layer 14. 'Here, phosphorus (P) or arsenic (As) can be used as impurities. Please refer to FIG. 7, a low electrode pattern composed of a first conductive layer pattern 14a and a second conductive layer pattern 16a is coated with a photoresist material on the second On the conductive layer 16, a photoresist pattern (not shown) is formed, and the photoresist pattern is used as an etching mask to continuously etch the second conductive layer 16 and the first conductive layer 14. Come to be formed. Then, a HSG silicon layer 22 is formed on the surface of the low electrode pattern including the first conductive layer pattern 14a and the second conductive layer pattern 16a by applying a selective HSG process, which can be formed Low electrodes with increased surface area. Then, a dielectric thin film (not shown in the figure) and an upper electrode (not shown in the figure) were formed and a common CMOS formation method was falsely executed--11-This paper scale is applicable to the Chinese National Standard (CNS) A4 Specifications (210X297mm) ---- · ----: --- ^ Pack — (please read the precautions on the back before filling in this page)
A 經濟部中央揉準局員工消費合作社印装 A7 B7 五、發明説明（*?) 行。 窨施例2 第8至1◦圖傷用以説明本發明之第二實施例之一種 利用一選擇HSG法來製造半導體記億裝置之電容器之方法 的剖視圖。 Η參閲第8圖所示，一絶緣層像被形成於一半導體基 體100上侔隔離如一電晶體般的次結構。然後，暴露該半 導體基體100之一部份的一接觸孔h3，僳藉著利用一光致 抗蝕型（圖中未示）作為一蝕刻光罩以蝕刻該絶緣層俥 可形成一絶線層圖型112 ，來被形成。 _參閲第9圖所示，在該光致抗蝕圖型被移去之後， •導電層，例如，由具有一第一雜質度之一多晶矽薄膜所 構成的一第一導電層114和由具有一第二離質濃度之一非 晶質矽薄膜所構成的一第二導電層116 ，傺連鑛地被沉積 於以上已形成有該接觸孔h3的最終結構上，該第二雜質濃 度傜比該第一雜質濃度高。或者，該第一導電層114藉著 沉積具有該第一雜質濃度的一非晶質矽薄膜替代多晶矽薄 膜，及藉著一熱處理、一電漿處理_者一電子束或一雷射 束的照射來結晶該非晶質矽薄膜而像能夠被形成。如此形 成的第一導電層114在一後面的HSG矽層形成步驟期間能 夠防止一HSG矽層形成於其上。 請參閲第1 0 .圖所示，由一第一導電層圖型114a和一 第二導電層圖型116a所構成的一低電極圖型傜藉著塗覆一 光致抗蝕材料於該第二導電層116上、形成一光致抗蝕圖 . -12 - 本紙張XJt適用中國國家標準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝- Λ A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（\〇 型（圖中未示）、及利用該光致抗蝕圖型作為一蝕刻光罩 來連續蝕刻該第二導電層116和該第一導電層114 ，來被 形成。 然後，一HSG矽層122傜只被形成於該第二導電層圖 型116a的表面上俾可形成一低電極。在這裡，由於該第— 導電層圖型114a僳由如以上所述之具有該低雜質濃度的多 晶矽所構成，雜質自該低電極至該半導體基體的擴散在後 面的熱處理期間傜被抑制。 窖掄例3 第1 1至15圖傺用以說明本發明之第三實施例之一 種利用一選擇HSG法來製造半導體記億裝置之電容器之方 法的剖視圖。 請參閲第1 1圖所示，用於隔離一基體的一絶'緣層圖 型212像以配合第8圖之第二實施例中所描述之相同的方 法被形成於一半導髏基體200上。 因此，導電層，例如，由具有一第一雜質濃度之多晶 矽薄膜所構成的一第一導電層214 、一結晶切除薄膜215 、由具有一第二雜質濃度之非晶質矽薄膜所構成的一第二 導電層216 ，傷輪流被沉積在以上的最終結構上，該第二 雜質濃度傜比該第一雜質濃度高。或者，與在該第一賁施 例中相同，該第一導電餍214藉著沉積具有該第一雜質濃 度的一非晶質矽薄膜，及藉著一熱處理、一電漿處理、或 者一電子束或一雷射束的照射而傷能夠被形成。而且，該 結晶切除薄膜215能夠由，例如，一氧化薄膜形成，該氧 -13 - 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ： .---f 裝-------訂------f | r r (請先閲讀背面之注意事項再填寫本頁) 經濟部中央樣率局ec工消费合作社印裝 A7 ___B7__五、發明説明（\丨） 化薄膜像藉著一化學蒸氣沉積法（CVD)或者一熱氣化法形 成到一小於100A的厚度。 請參閲第1 2圖所示，由一第一導電層圖型214a、一 第一結晶切除薄膜圖型（圖中未示）、和一第二導電層圖 型216a所構成的一低電極偽藉箸形成一光致抗蝕圖型（圖 中未示）於該第二導電層216上及連續地蝕刻該第二導電 層216 、該結晶切除薄膜215 、和該第一導電層214來被 形成。然後* 一側凹區域（undercut area) A擦被形成於 該第一導電層圖型214a與該第二導電層圔型216a之間，且 一第二結晶切除薄膜圖型215a像在同一時間藉由濕蝕刻法 移去該第一結晶切除薄膜圖型的一部份到一預定寬度來被 .形成。 請参閲第1 3画所示，一 HSG矽層/22傷只被形成於 該第二導電層圖型216a的表面上及在該侧凹區域A内。在 這裡，該第一導電層圖型214a和該第二導電層圖型216a僳 藉由被形成於該側凹區域A内的HSG矽層222來互相連接 。由於該第一導電層圖型214a傜與第二實施例一樣由具有 低雜質濃度的多晶矽薄膜形成，雜質自該低電極至該半導 體基體的擴散在後面的熱處理期間能夠被抑制。 通常*當沉積包括高濃度之雜質的一非晶質矽薄膜於 一値由具有低濃度之雜質之多晶矽薄膜形成的底層上時， 為了形成導電層給該半導體記憶裝置的低電層，該非晶質 矽薄膜的結晶因該多晶矽薄膜而可以加快。然而，根據該 第三實施例*由於該結晶切除薄膜215傜被形成於由該多 *14- --^ 裝-- (請先閲讀背面之注^h項再填寫本頁) L.A Printed and printed by the Employee Consumer Cooperative of the Central Bureau of Economic Cooperation of the Ministry of Economic Affairs A7 B7 V. Invention description (*?) OK. Example 2 Figures 8 to 1 are cross-sectional views for explaining a method for manufacturing a capacitor of a semiconductor memory device using a selected HSG method according to a second embodiment of the present invention. As shown in FIG. 8, an insulating layer is formed on a semiconductor substrate 100 to isolate a sub-structure like a transistor. Then, a contact hole h3 of a part of the semiconductor substrate 100 is exposed, and a insulating layer can be formed by using a photoresist type (not shown) as an etching mask to etch the insulating layer so as to form an insulating layer Pattern 112 is formed. _As shown in FIG. 9, after the photoresist pattern is removed, the conductive layer, for example, a first conductive layer 114 composed of a polysilicon film having a first impurity degree and A second conductive layer 116 composed of an amorphous silicon thin film having a second ion concentration, the Yelian ore field is deposited on the above final structure where the contact hole h3 has been formed, and the second impurity concentration is Nu Higher than the first impurity concentration. Alternatively, the first conductive layer 114 replaces the polycrystalline silicon film by depositing an amorphous silicon film with the first impurity concentration, and by a heat treatment, a plasma treatment, an electron beam or a laser beam irradiation The amorphous silicon thin film is crystallized to form an image. The thus formed first conductive layer 114 can prevent an HSG silicon layer from being formed thereon during a subsequent HSG silicon layer forming step. Please refer to Figure 10. As shown in the figure, a low-electrode pattern composed of a first conductive layer pattern 114a and a second conductive layer pattern 116a is coated with a photoresist material on the A photoresist pattern is formed on the second conductive layer 116. -12-This paper XJt is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page) Λ A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Invention description (\ 〇 type (not shown), and using the photoresist pattern as an etching mask to continuously etch the second conductive The layer 116 and the first conductive layer 114 are formed. Then, a HSG silicon layer 122 is only formed on the surface of the second conductive layer pattern 116a so that a low electrode can be formed. Here, due to the first — The conductive layer pattern 114a is composed of polysilicon with the low impurity concentration as described above, and the diffusion of impurities from the low electrode to the semiconductor substrate is suppressed during the subsequent heat treatment. 傡 抡 例 3 第 1 1 15 to 15 are used to illustrate an advantage of the third embodiment of the present invention A cross-sectional view of a method for manufacturing a capacitor of a semiconductor memory device by selecting the HSG method. Please refer to Figure 11 for an insulating layer pattern 212 image for isolating a substrate to match the first in Figure 8 The same method as described in the second embodiment is formed on the half of the guide base 200. Therefore, the conductive layer, for example, a first conductive layer 214 composed of a polysilicon film having a first impurity concentration, a crystal cut Film 215, a second conductive layer 216 composed of an amorphous silicon film with a second impurity concentration, wound alternately deposited on the above final structure, the second impurity concentration is higher than the first impurity concentration Or, as in the first embodiment, the first conductive material 214 is deposited by depositing an amorphous silicon film with the first impurity concentration, and by a heat treatment, a plasma treatment, or a Injury can be formed by the irradiation of an electron beam or a laser beam. Furthermore, the crystal removal film 215 can be formed of, for example, an oxide film, the oxygen-13-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification ( twenty one 0X297mm): .--- f installed ------- order ------ f | rr (please read the precautions on the back before filling out this page) ec industrial consumption of the Central Sample Bureau of the Ministry of Economic Affairs Cooperative cooperative printing A7 ___B7__ V. Description of the invention (\ 丨) The thin film is formed by a chemical vapor deposition method (CVD) or a thermal vaporization method to a thickness of less than 100A. Please refer to Figure 12 A photoresist pattern is formed by a low electrode consisting of a first conductive layer pattern 214a, a first crystal cut film pattern (not shown), and a second conductive layer pattern 216a A type (not shown) is formed on the second conductive layer 216 and the second conductive layer 216, the crystal cut film 215, and the first conductive layer 214 are continuously etched. Then, an undercut area A is formed between the first conductive layer pattern 214a and the second conductive layer pattern 216a, and a second crystal cut film pattern 215a appears to be borrowed at the same time. A part of the first crystal cut film pattern is removed to a predetermined width by wet etching to be formed. Please refer to the picture 13 shows that a HSG silicon layer / 22 wound is only formed on the surface of the second conductive layer pattern 216a and in the undercut area A. Here, the first conductive layer pattern 214a and the second conductive layer pattern 216a are connected to each other by the HSG silicon layer 222 formed in the undercut region A. Since the first conductive layer pattern 214a is formed of a polysilicon film having a low impurity concentration as in the second embodiment, the diffusion of impurities from the low electrode to the semiconductor substrate can be suppressed during the subsequent heat treatment. Usually * when depositing an amorphous silicon thin film including high concentration impurities on an underlayer formed of a polycrystalline silicon thin film with low concentration impurities, in order to form a conductive layer for the low electric layer of the semiconductor memory device, the amorphous The crystallization of the quality silicon film can be accelerated by the polycrystalline silicon film. However, according to the third embodiment * because the crystal removal film 215 is formed by the multiple * 14--^ pack-(please read the note ^ h on the back before filling this page) L.
、tT Λ 本紙張尺度逋用中國國家榡準（CNS ) A4规格（210 X 297公嫠） 315510 a? B7 五、發明説明（丨z ) 晶矽薄膜所構成的該第一導電層214與由該非晶質矽薄膜 所構成的該第二導電層216之間，該第二導電層216之非 晶質矽薄膜的結晶因該第一導電層214的多晶矽薄膜而能 夠被防止。 求倌例芊 第1 4和1 5圖顯示當一低電極之下和上部份之雜質 濃度傜從低值至高值改變時，在習知與本發明之間之一比 較測試的結果。第1 4圖傜一値比較一習知技術和本發明 之低電極之Cm in/Cmax比率的圖表。第1 5圖傺一個顯示 該習知技術與本發明根據該等低電極中之雜質濃度之絶緣 特性的圖表，那就是，在相鄰之有源區域之間之崩潰電壓 的分佈。 經濟部中央榡準局貞工消費合作社印繁 (請先閲讀背面之注意事項再填寫本頁) 在執行以上的測試中，磷（P)偽被使用作為被摻雜於 該低電極中的雜質而PH3僳被使用作為一磷來源氣體 (phosphorus source gas)俾形成一矽層，根據本發明， 該矽層的下和上部份在一實驗取樣中傜具有不同的雜質濃 度。首先，有一低雜質濃度的一第一矽層僳在該PH3的第 一輸入流動速率為3.5 seem之下被形成到大約該低電極之 整個厚度之8¾的厚度。然後，有一高雜質濃度的一第二矽 層傺藉著增加該PH 3的一第二輸入流動速率至1〇 seem來 被形成。一HSG層、一介電薄膜、和一上電極傷連鑛地以 所描述的順序被形成於該第二矽層的表面上。在這裡’該 第二矽層偽由一非晶質矽薄膜形成。在根據該習知技術的 實驗取樣中，一電容器的低電極偽由一單一層形成且該 -15 - 本紙張尺度逍用中國國家揉準（CNS ) A4規格（210X297公釐）、 TT Λ This paper scale uses the Chinese National Standard (CNS) A4 specification (210 X 297 gong) 315510 a? B7 V. Invention description (丨 z) The first conductive layer 214 composed of crystalline silicon film and Between the second conductive layer 216 formed by the amorphous silicon thin film, crystallization of the amorphous silicon thin film of the second conductive layer 216 can be prevented due to the polycrystalline silicon thin film of the first conductive layer 214. Seeking examples. Figures 14 and 15 show the results of a comparison test between the conventional and the present invention when the concentration of impurities below and above a low electrode changes from low to high. Fig. 14 is a graph comparing the Cm in / Cmax ratio of a conventional technique and the low electrode of the present invention. Fig. 15 is a graph showing the insulation characteristics of the conventional technology and the present invention according to the impurity concentration in the low electrodes, that is, the distribution of the breakdown voltage between adjacent active regions. The Ministry of Economic Affairs, Central Bureau of Prefectural Affairs, Jeonggong Consumer Cooperative Indica (please read the precautions on the back before filling out this page) In the above test, phosphorus (P) was used as an impurity doped in the low electrode PH3 is used as a phosphorus source gas to form a silicon layer. According to the present invention, the lower and upper parts of the silicon layer have different impurity concentrations in an experimental sample. First, a first silicon layer with a low impurity concentration is formed below the first input flow rate of PH3 to 3.5 seem to a thickness of about 8¾ of the entire thickness of the low electrode. Then, a second silicon layer with a high impurity concentration is formed by increasing a second input flow rate of the PH 3 to 10 seem. An HSG layer, a dielectric film, and an upper electrode are formed on the surface of the second silicon layer in the order described. Here, the second silicon layer is formed of an amorphous silicon thin film. In the experimental sampling according to the conventional technology, the low electrode of a capacitor is formed by a single layer and the paper size is -15-this paper standard is used in China National Standard (CNS) A4 specification (210X297mm)
A7 五、發明説明（G) · HSG層、該介電薄膜、和該上電極傷連鑛地以所描述的順 序被形成在其之表面上，該單一層藉著使得該PH3的輸入 流動速率均勻而傺具有一均勻的雜質濃度，那就是，1〇 seem ° 如從第1 4和1 5圖所顯示般，本發明之Cmin/Cnax tt率（□)與習知技術的Cmin/Cmax比率（〇）比較起來 像被降低大約5¾。然而，在該等低電極之下和上部份之雜 質濃度傜被形成到不同的情況中，即，本發明（□.)傜在 低和高濃度，在該絶緣區域中的崩潰與習知技術（〇}比 較起來侮被增加大約15¾:以上。在崩潰電壓特性上之如此 的改進增加一裝置的可靠度。 從第1 4和1 5圖之結果可見，當形成該HSG在該低 電極中來增加該半導體記億裝置之電容器的表面面積時， 如果該低電極之下和上部份的雜質濃度傺不同的話，該裝 置特性的變壤能夠被防止。 當該半導體記億裝置的電容器傺利用本發明之較佳實 施例的方法製造時，防止雜質從該電容器之低電極的擴散 及獲得希望的Cmin/Cmax比率像有可能的。 本發明並不受限於以上的實施例，且很清楚了解的傜 ，在本發明的範圍及精神之内，很多變化傺能夠由任何熟 知此項技藝的人仕來實行的。 元件標號對照表 1 半導體基髅 3 氧化薄膜 tu 接觸孔 5 導電層 -16 - 本^紙張又度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) —( 裝---- 1T------f 經濟部中央棣準局貝工消費合作杜印製 -—flli i ^m— e—^—— -m- ml m·^— Mm m 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（丨4 ) 7 低 电 極 9 HSG 矽 層 Cm I η m 取 小 電 容 Cm3》 :最 大 電 容 10 半 導 體 基 體 h 2 接觸 孔 12 絶 緣 層 圖 型 14 第一 導 電 層 16 第 二 導 電 層 14a 第一 電 層 圖 型 16a 第 二 導 電 層 圖 型 22 HSG 矽 層 100 半 導 體 基 a曲 歴 h 3 接觸 孔 112 絶 綠 層 圖 型 114 第一 導 層 116 第 二 導 電 層 114a .第 一 導 電 層 圖 型 116s [ 第 二 導 電 層 圖型 122 HSG 矽 層 200 半 導 體 基 體 212 絶綠 層 圖 型 214 第 導 層 215 結晶 切 除 薄 膜 216 第 — 導 電 層 214a 第 一 導 電 層 圖 型. 216a 第 二 導 電 層 圖型 215a 第 二 結 晶 切 除 薄膜圖型 222 HSG 矽 層 A 倒凹 區 域 —17 - (請先閲讀背面之注意事項再填寫本頁) m nnA7 5. Description of the invention (G) · The HSG layer, the dielectric film, and the upper electrode wound-connected mine are formed on the surface in the order described, and the single layer makes the input flow rate of the PH3 Uniform and Ye has a uniform impurity concentration, that is, 10 seem ° As shown in Figures 14 and 15, the Cmin / Cnax tt ratio (□) of the present invention and the Cmin / Cmax ratio of the conventional technology (〇) In comparison, it is reduced by about 5¾. However, the concentration of impurities in the lower and upper parts of the low electrodes is formed into different situations, that is, the collapse of the present invention (□.) At low and high concentrations in the insulating region and knowledge The technology (〇) is increased by approximately 15¾: more than this. Such improvements in breakdown voltage characteristics increase the reliability of a device. From the results of Figures 1 4 and 15 it can be seen that when the HSG is formed at the low electrode When increasing the surface area of the capacitor of the semiconductor billion device, if the impurity concentration of the lower and upper parts of the low electrode is different, the change of the characteristics of the device can be prevented. When the capacitor of the semiconductor billion device When manufactured by the method of the preferred embodiment of the present invention, it is possible to prevent the diffusion of impurities from the low electrode of the capacitor and obtain the desired Cmin / Cmax ratio. The present invention is not limited to the above embodiments, and It is clearly understood that, within the scope and spirit of the present invention, many changes can be carried out by anyone who is familiar with this skill. Reference Table of Component Numbers 1 Semiconductor Base 3 Oxidation Membrane tu contact hole 5 conductive layer -16-This ^ paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back and then fill out this page) — (Pack ---- 1T ------ f Printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs --- flli i ^ m— e — ^ —— -m- ml m · ^ — Mm m Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Printed A7 B7 5. Description of the invention (丨 4) 7 Low electrode 9 HSG Silicon layer Cm I η m Take small capacitance Cm3》: Maximum capacitance 10 Semiconductor substrate h 2 Contact hole 12 Insulation layer pattern 14 First conductive layer 16 Second conductive layer 14a First electric layer pattern 16a Second conductive layer pattern 22 HSG Silicon layer 100 Semiconductor substrate a Curved hole 3 Contact hole 112 Green layer pattern 114 First conductive layer 116 Second conductive layer 114a. First conductive layer pattern 116s [Second conductive layer pattern 122 HSG Silicon layer 200 Semiconductor substrate 212 Green layer pattern 214 First conductive layer 215 Crystal cut film 216 — Conductive layer 214a First conductive layer pattern. 216a Second conductive layer pattern 215a Second crystal cut film pattern 222 HSG Silicon layer A Undercut area — 17-(Please read the notes on the back before filling this page) m nn
、tT —1 ι^ϋ— -flm —^—^R m 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐）、 TT —1 ι ^ ϋ— -flm — ^ — ^ R m The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm)