515091 48 1 1 PlF.doc/0 02 A7 _B7_ 五、發明說明（I ) 發明背景 1. 發明領域 本發明是有關於一種半導體生產，並且特別是一種高 介電電容器及其製作方法。 2. 習知技藝 爲獲得具有巨大或更高規模的電鐵記憶元件 (ferroelectric memory device)，需要例如重力態隨機存耳又記 憶體元件（DRAM)內的位元線上電容器（capacitor on bit line， COB)。也就是說，在形成位元線後，在其上方形成絕緣 體。之後，在絕緣體上形成電容器而使其藉由絕緣體的接 觸窗插塞與基底的預定主動區域產生電性連接。 在此COB結構中，鄰近電容器之間的距離顯著地影 響特定晶胞的電容器面積。舉例來說，鄰近電容器之間的 距離是根據微影製程的數目、上電極、介電膜、以及下電 極的蝕刻輪廓、以及介層沉積的塡塞特性而定。 經濟部智慧財產局員工消費合作社印製 二-------------裝--- (請先閱讀背面之注意事項再填寫本頁) 一種解決的辦法乃是如第1圖所繪示的減少微影製 程。第1圖的鐵電電容器是藉由使用單一硬罩幕18進行 同時蝕刻上電極16、鐵電膜14、以及下電極12的一步驟 微影製程（one step photographic process)所形成。然而，此 一步驟微影製程具有一些問題。例如，在蝕刻該層16、14、 以及12時，鐵電膜14將遭受破壞（請見標號21)直到下電 極12的蝕刻終結。這將增加鐵電層14內的電流遺漏（cuirent leakage) 〇 另一個問題是活化氫氣的產生。在隨後的製程，例如， 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ' 515091 4 8 I 1 PI I· cioc/〇〇2 A7 _ B7 五、發明說明（〉） 利用化學氣相沉積（chemical vapor deposition，CVD)技術的 氧化矽沉積、利用CVD技術的鎢插塞製程、以及利用CVD 技術的氮化矽保護層沉積，產生了活化氫氣。此氫氣在鐵 電層14中擴散（diffusion)，因此破壞了電極與鐵電層之間 的介面（請見標號22與23)。氫氣增加了電流遺漏並且降 低電子特性。 爲解決與氫氣相關的問題，上電極可以由不與氫氣 化學作用的銥（iridium)所製成◦然而，當下電極的材質包 括銥時，卻產生了另一個問題。問題是在銥電極上不易獲 得具有所欲結晶構造的鐵電層。 於是，需要一種製造鐵電電容器而不產生上述問胃的 方法。 發明槪述 本發明是基於前述問題來完成，因此本發明之目的 爲提供了一種鐵電電容器的製造方法，其能以單一步驟微 影製程避免電容器特性的破壞。 本發明的目的、優點、以及特徵爲提供由下電極、 介電層、上電極、以及在上電極與介電層的側壁以及下電 極上所形成之間隙壁所製成的鐵電電容器。間隙襞是在上 電極與介電層的側壁以及下電極上所形成。在形成間隙壁 的同時圖案化下電極。因此，能減低蝕刻下電極而造成鐵 電膜的電漿蝕刻破壞（plasma etching damage)至最低。這也 能減少氫氣所造成的缺陷至最低。 寅特別的是，上電極與介電層是使用触刻覃幕Η案 (請先閱讀背面之注意_再填寫本頁) 裝 訂· 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 515091 4Κ 1 I PI Ι· .doc/002 A7 五、發明說明（> ) 進行圖案化卻並未鈾刻下電極。在下電極層以及圖案化上 電極與介電層上沉積材質層。進行非等向性蝕刻以在圖案 化上電極與介電層的側壁形成間隙壁。在形成間隙壁的同 時，圖案化下電極以形成電容器。 間隙壁的材質包括能避免在介電層中氫氣擴散的材 質。例如，可以使用氧化鈦、氧化鋁、以及氧化矽。間隙 壁也可以在蝕刻圖案化層時，避免介電層遭受破壞。 本發明的優點是使用單一步驟微影製程而未破壞電 容器特性。此單一步驟微影製程是使用由光阻或硬罩幕所 組成的蝕刻罩幕圖形。硬罩幕包括導電層、半導體層、絕 緣層、以及介電層。 配合所附圖式可瞭解本發明，且熟於此技人士可顯 見本發明之目的： 圖式之簡單說明： 第1圖是繪示由一步驟微影製程所形成的鐵電電容器 之剖面視圖，其顯示與鐵電電容器相關的問題；以及 第2A圖到第2E圖是根據本發明在製作鐵電電容器的 所選製程步驟繪示半導體基底的剖面視圖； 圖式之標記說明： 10、100 :絕緣層 12、102 :下電極 14 :鐵電層 16、106 :上電極 (請先閱讀背面之注意事«(再填寫本頁) --裝 .- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 515091 48 1 1 PI l;.doc/0 02 A7 _B7_ 五、發明說明（/ ) 18 :硬罩幕 102a :下電極圖案 104 :介電層 1 04a :介電層圖案 106a :上電極圖案 108 :蝕刻罩幕層 108a :蝕刻罩幕圖案 1 1 〇 :光阻圖案 120 :材質層 120a ··間隙壁 實施例 本發明將根據相關的圖示與較佳實施例進行詳細的說 明。然而，本發明將由不同的實施例所呈現而不應該限制 在此所表達的實施例。提供這些實施例是爲要完整且透徹 地揭露本發明，並且將對熟知此技藝者完全傳達發明的範 圍。爲求淸楚明確，在圖中放大了該層的厚度以及區域。 當提到一層是在另一層或基底的“上方”時，表示其可以 直接在其他層或基底的上方或也可以具有介入層 (intervening layers)。相反的來說，當提到一元件是在另一 元件的“正上方”時，就沒有介入元件。 本發明是有關於一種電容器及其製造方法。本發明提 供了由上與下電極、介電層、以及在上電極與介電層的側 壁以及下電極上形成的阻障層（barrier layer)所製成的一種 高介電電容器。第2E圖提供了本發明的電容器。介電層 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱Ί " (請先閱讀背面之注意^^再填寫本頁) 裝 訂·- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 515091515091 48 1 1 PlF.doc / 0 02 A7 _B7_ V. Description of the Invention (I) Background of the Invention 1. Field of the Invention The present invention relates to a semiconductor production, and in particular to a high-dielectric capacitor and a method for manufacturing the same. 2. Know-how To obtain a ferroelectric memory device with a huge or higher scale, for example, a capacitor on a bit line in a state of gravity random storage and a memory device (DRAM), COB). That is, after the bit line is formed, an insulator is formed thereon. After that, a capacitor is formed on the insulator so as to be electrically connected to a predetermined active area of the substrate through a contact plug of the insulator. In this COB structure, the distance between adjacent capacitors significantly affects the capacitor area of a particular unit cell. For example, the distance between adjacent capacitors is determined by the number of lithographic processes, the etched contours of the upper electrode, the dielectric film, and the lower electrode, and the plugging characteristics of the dielectric layer. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs II ------------- Installation --- (Please read the precautions on the back before filling out this page) One solution is as described in Section 1. The figure shows the lithography reduction process. The ferroelectric capacitor of FIG. 1 is formed by a one-step photographic process using a single hard mask 18 to simultaneously etch the upper electrode 16, the ferroelectric film 14, and the lower electrode 12. However, this one-step lithography process has some problems. For example, when the layers 16, 14, and 12 are etched, the ferroelectric film 14 will be damaged (see reference numeral 21) until the etching of the lower electrode 12 ends. This will increase the current leakage in the ferroelectric layer 14. Another problem is the generation of activated hydrogen. In subsequent processes, for example, 4 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) '515091 4 8 I 1 PI I · cioc / 〇〇2 A7 _ B7 V. Description of the invention (> ) Silicon oxide deposition using chemical vapor deposition (CVD) technology, tungsten plug process using CVD technology, and silicon nitride protective layer deposition using CVD technology generate activated hydrogen. This hydrogen diffuses in the ferroelectric layer 14 and thus destroys the interface between the electrode and the ferroelectric layer (see references 22 and 23). Hydrogen increases current leakage and reduces electronic characteristics. In order to solve the problems related to hydrogen, the upper electrode can be made of iridium which does not chemically react with hydrogen. However, when the material of the lower electrode includes iridium, another problem arises. The problem is that it is not easy to obtain a ferroelectric layer having a desired crystal structure on an iridium electrode. Therefore, there is a need for a method for manufacturing a ferroelectric capacitor without causing the above-mentioned stomach trouble. SUMMARY OF THE INVENTION The present invention is completed based on the foregoing problems, and an object of the present invention is to provide a method for manufacturing a ferroelectric capacitor, which can avoid the deterioration of capacitor characteristics in a single-step lithography process. It is an object, advantage, and feature of the present invention to provide a ferroelectric capacitor made of a lower electrode, a dielectric layer, an upper electrode, and a sidewall formed on a sidewall of the upper electrode and the dielectric layer, and a spacer formed on the lower electrode. The gap 襞 is formed on the sidewalls of the upper electrode and the dielectric layer, and on the lower electrode. The lower electrodes are patterned while forming the spacers. Therefore, plasma etching damage to the ferroelectric film caused by etching the lower electrode can be reduced to a minimum. This also minimizes defects caused by hydrogen. In particular, the upper electrode and the dielectric layer are printed using the Tanmu case (please read the note on the back _ and then fill out this page). Binding · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. This paper is suitable for China National Standard (CNS) A4 specification (210 x 297 mm) 515091 4K 1 I PI Ι. .Doc / 002 A7 V. Description of the invention (>) The electrode was not patterned with uranium. A material layer is deposited on the lower electrode layer and the patterned upper electrode and dielectric layer. Anisotropic etching is performed to form a spacer on the patterned upper electrode and the sidewall of the dielectric layer. Simultaneously with the formation of the spacer, the lower electrode is patterned to form a capacitor. The material of the partition wall includes a material that can prevent hydrogen diffusion in the dielectric layer. For example, titanium oxide, aluminum oxide, and silicon oxide can be used. The spacer also protects the dielectric layer from damage when the patterned layer is etched. An advantage of the present invention is that a single-step lithographic process is used without damaging the capacitor characteristics. This single-step lithography process uses an etched mask pattern consisting of a photoresist or a hard mask. The hard mask includes a conductive layer, a semiconductor layer, an insulating layer, and a dielectric layer. The invention can be understood with the accompanying drawings, and those skilled in the art can clearly see the purpose of the invention: Brief description of the drawings: Figure 1 is a cross-sectional view showing a ferroelectric capacitor formed by a one-step lithography process , Which shows problems related to ferroelectric capacitors; and FIGS. 2A to 2E are cross-sectional views showing a semiconductor substrate in a selected process step of manufacturing a ferroelectric capacitor according to the present invention; : Insulating layer 12, 102: Lower electrode 14: Ferroelectric layer 16, 106: Upper electrode (please read the precautions on the back «(Fill this page again)-installed.-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 515091 48 1 1 PI l; .doc / 0 02 A7 _B7_ V. Description of the invention (/) 18: Hard cover 102a: Lower electrode pattern 104: Dielectric layer 104a: Dielectric layer pattern 106a: Upper electrode pattern 108: Etching mask layer 108a: Etching mask pattern 1 10: Photoresist pattern 120: Material layer 120a Detailed according to related illustrations and preferred embodiments Explanation. However, the present invention will be presented by different embodiments and should not be limited to the embodiments expressed herein. These embodiments are provided to fully and thoroughly disclose the invention, and will fully convey the invention to those skilled in the art For the sake of clarity, the thickness and area of the layer have been enlarged in the figure. When a layer is referred to as being "above" another layer or substrate, it means that it can be directly above the other layer or substrate or There may be intervening layers. Conversely, when an element is referred to as being "directly above" another element, there is no intervening element. The present invention relates to a capacitor and a method for manufacturing the same. The present invention A high-dielectric capacitor made of upper and lower electrodes, a dielectric layer, and a barrier layer formed on the sidewalls of the upper and lower electrodes and the lower electrode is provided. Figure 2E provides The capacitor of the present invention. Dielectric layer 7 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love Ί " (Please read the note on the back ^^ before filling this page) Binding ·-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 515091
4 8 1 1 P I l· . doc/002 JSJ ____ B7 五、發明說明（夂） 104a是由具有高介電値的材質，如鐵電材質以及高介電材 質所製成。阻障層12〇a是用來避免以CVD技術的形成製 程在介電層104a中產生氫氣的擴散。阻障層也是用來包 護介電層不受蝕刻劑的破壞。阻障層120a的材質也可以 包括氧化鈦（Ti〇2)、氧化鋁（Al2〇3)、以及氧化矽（Si02)。 除此之外，可以使用與介電層相同的材質。 上述電容器的製造方法將參考第2A圖到第2E圖在以 下作詳細說明。請參照第2A圖，在一積體電路基底（未繪 示於圖中）上形成一絕緣層1〇〇。絕緣層可以是元件隔離 層。隨後形成下電極材質層102、介電材質層104、上電 極材質層106、以及蝕刻罩幕層1〇8。 每一下與上電極102與106能由任何導電材質或其組 合所製成。舉例來說，下電極1〇2的材質包括與隨後形成 的介電層104提供良好基礎結構的材質，如白金 (platinum)，而上電極的材質包括不與氫氣發生化學反應 的材質，如銥。介電層104的材質可以包括高介電材質或 鐵電材質，如PZT以及BST。 倉虫刻罩幕層108的材質可以包括光阻或硬罩幕材質 層。硬罩幕材質層包括導電層、半導體層、絕緣體、介電 層。舉例來說，可以使用鈦或氧化鈥。 利用光阻圖案110蝕刻蝕刻罩幕層108以形成如第2B 圖所繪示的蝕刻罩幕圖案l〇8a。利用蝕刻罩幕圖案108a 蝕刻上電極材質層106以及介電材質層1〇4以形成如第2C 圖所繪示的上電極106a以及介電層l〇4a的圖案。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） ----r--------- -裝· — I 再填寫本頁) 訂：4 8 1 1 P I l ·. Doc / 002 JSJ ____ B7 V. Description of the Invention (夂) 104a is made of materials with high dielectric 値, such as ferroelectric materials and high dielectric materials. The barrier layer 120a is used to avoid the diffusion of hydrogen gas generated in the dielectric layer 104a by the CVD formation process. The barrier layer is also used to protect the dielectric layer from damage by the etchant. The material of the barrier layer 120a may also include titanium oxide (Ti02), aluminum oxide (Al203), and silicon oxide (SiO2). Otherwise, the same material as the dielectric layer can be used. The manufacturing method of the above capacitor will be described in detail below with reference to FIGS. 2A to 2E. Referring to FIG. 2A, an insulating layer 100 is formed on a integrated circuit substrate (not shown). The insulating layer may be an element isolation layer. Subsequently, a lower electrode material layer 102, a dielectric material layer 104, an upper electrode material layer 106, and an etching mask layer 108 are formed. Each of the lower and upper electrodes 102 and 106 can be made of any conductive material or a combination thereof. For example, the material of the lower electrode 102 includes a material that provides a good basic structure with the dielectric layer 104 formed later, such as platinum, and the material of the upper electrode includes a material that does not react with hydrogen, such as iridium . The material of the dielectric layer 104 may include a high dielectric material or a ferroelectric material, such as PZT and BST. The material of the worm mask mask layer 108 may include a photoresist or a hard mask material layer. The hard mask material layer includes a conductive layer, a semiconductor layer, an insulator, and a dielectric layer. For example, titanium or oxide can be used. The photoresist pattern 110 is used to etch the etch mask layer 108 to form an etch mask pattern 108a as shown in FIG. 2B. The upper electrode material layer 106 and the dielectric material layer 104 are etched by using the etching mask pattern 108a to form a pattern of the upper electrode 106a and the dielectric layer 104a as shown in FIG. 2C. This paper size applies to China National Standard (CNS) A4 specification (21〇 X 297 public love) ---- r ----------installed · — I then fill out this page) Order:
515091 4 8 11 PI 1. doc/002 A7 __B7 五、發明說明（A ) 請參照第2D圖，爲形成間隙壁，在結果構造上沉積 一材質層120。材質層120的提供適用來保護圖案化介電 層104a不受電漿蝕刻。材質層也是用來避免在圖案化介 電層l〇4a中的氫氣擴散。例如，可以使用絕緣體、氧化 鈦、氧化鋁、以及氧化矽。接著回蝕材質層120以在圖案 化上電極l〇6a以及介電層104a的側壁形成間隙壁120a。 在此回蝕製程中必須注意的是下電極材質層也回蝕形成下 電極圖案102a。結果完成如第2E圖所繪示的鐵電電容器。 間隙壁120a能在蝕刻下電極材質層時減低蝕刻破壞。 (請先閱讀背面之注意再填寫本頁) Ι·Η 裝 ·- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）515091 4 8 11 PI 1. doc / 002 A7 __B7 V. Description of the Invention (A) Please refer to Figure 2D. In order to form the partition wall, a material layer 120 is deposited on the resulting structure. The material layer 120 is provided to protect the patterned dielectric layer 104a from plasma etching. The material layer is also used to avoid hydrogen diffusion in the patterned dielectric layer 104a. For example, insulators, titanium oxide, aluminum oxide, and silicon oxide can be used. Next, the material layer 120 is etched back to form a spacer 120a on the sidewall of the patterned upper electrode 106a and the dielectric layer 104a. It must be noted in this etchback process that the lower electrode material layer is also etched back to form the lower electrode pattern 102a. As a result, the ferroelectric capacitor shown in FIG. 2E is completed. The partition wall 120a can reduce etching damage when the lower electrode material layer is etched. (Please read the note on the back before filling in this page) Ι · Decoration ·-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)