」7Ι~Π〇468 Α7 一 ~" ~~— _Β7_ - 五、發明說明（/ ) 本發明是有關於—種動態隨機存取記憶體（Dynamic Rand〇m Access Mem〇ry ; DRAM)的製造方法，且特別是 有關於一種動態隨機存取記憶體之電容器的製造方法。 當半導體進入深次微米（Deep Sub-Micron)的製程時， 元件的尺寸逐漸縮小，使整個積體電路的運作速度將因此 而能有效地提昇。對具有相同電路佈局之半導體元件而 言’整個電路之運作速度和其內部元件密度有關。在高元 件密度下，以DRAM而言，爵了縮小DRAM電容器所佔 據的面積’必須縮小電容器的尺寸，但同時也減少了電容 器的儲存電荷量。如此會增加電容器週期性的充電頻率，’ 使得DRAM的資料處理速度降低。 一般在形成電容器時，通常是在第一層的絕緣層中先 形成自口點?女觸窗開口（n〇de contact window)，塡入導電材 質’形成節點接點（n〇de contact)，然後形成第二層絕緣層， 再定義出位在第二層的絕緣層中之容納電容器的冠狀 (crown)開口。g此節點接觸窗開口和冠狀開口是分兩次形 成的’所以需要兩個光罩來定義此二開口。如此一來，需 要較多的製程步驟才能完成整個電容器的製作，耗時且步 驟繁瑣。另外可容納電容器的空間只限於第二層的絕緣 層，使所形成的電容器之面積大小受到限制。所以需要較 簡化的步驟來~次定義節點接觸窗開口和冠狀開口，並可 形成面積較大的電容器。 . 因此本發明提供一種動態隨機存取記憶體之電容器的 製造方法。基底上至少形成有閘極，閘極一側之基底中形 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · 線- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 47 1 4uv r.di)c/002 A7 _4Ϊ 0468_B7______ 五、發明說明（2) 成有汲極以及基底上形成有第一絕緣層，此方法包括：形 成終止層於第一絕緣層之上，並圖案化終止層以形成開 口，暴露出位於汲極上方之第一絕緣層。接著形成第二絕 緣層於終止層之上以及開口中。然後去除位於開口上方及 其周圍部份之第二絕緣層至終止層爲止，以形成冠狀開 口，並去除位於開口下方之部份第一絕緣層，以形成接觸 窗開口來暴露出汲極。接下來，形成共形之第一導電層於 冠狀_開口和接觸窗開口中，以形成電容器之第一電極。然 後形成共形之介電層於第一導電層上，再形成共形之第二 導電層於介電層以及冠狀開口周圍之第二絕緣層之上，以 形成電容器之第二電極。其中第一絕緣層和第二絕緣層的 材質爲相同的，終止層和第一絕緣層、第二絕緣層的材質 則不同。 在上述方法中，亦可應用在形成有絕緣層，且絕緣層 中已形成有接觸插塞的基底上。如此，上述方法中接觸窗 開口所暴露出來的不爲汲極，而爲接觸插塞，而接觸插塞 和汲極彼此互相電性連接。其他的實施部份皆相同。 依據本發明的方法，其中一個特徵爲利用終止層爲第 二絕緣層的去除終點，以定義出電容器下電極在第二絕緣 層中的位置大小。並利用終止層爲蝕刻第一絕緣層之罩 幕，在第一絕緣層中形成接觸窗開口。所以具有下述優點。 一、在同一步驟中即可同時形成冠狀開口以及接觸窗開 口。二、電容器的下電極和接觸窗開口中的節點接點可以 —次形成，二者之間沒有界面接觸阻値之問題。三、可增 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閒讀背面之注意事項再填寫本頁) 線"7Ι ~ Π〇468 Α7 I ~ " ~~ — _Β7_-V. Description of the Invention (/) The present invention relates to the manufacture of a dynamic random access memory (Dynamic Random Access Memory; DRAM). Method, and in particular, a method for manufacturing a capacitor of a dynamic random access memory. When the semiconductor enters the process of deep sub-micron, the size of the components is gradually reduced, so that the operation speed of the integrated circuit can be effectively improved accordingly. For semiconductor devices with the same circuit layout, the operating speed of the entire circuit is related to its internal component density. With high component density, in terms of DRAM, reducing the area occupied by a DRAM capacitor 'must reduce the size of the capacitor, but at the same time reduce the amount of charge stored in the capacitor. This will increase the periodic charging frequency of the capacitor, which will reduce the data processing speed of the DRAM. Generally, when forming a capacitor, a self-contact point is first formed in the first insulating layer. A female contact window opening is inserted into the conductive material to form a nodal contact. A second insulating layer is then formed, and a crown opening for the capacitor is defined in the second insulating layer. g The contact window opening and the coronal opening of this node are formed in two 'so two photomasks are needed to define these two openings. As a result, more manufacturing steps are required to complete the entire capacitor manufacturing process, which is time consuming and cumbersome. In addition, the space for accommodating capacitors is limited to the second insulating layer, which limits the area of the formed capacitor. Therefore, more simplified steps are needed to define the node contact window opening and the crown opening, and a capacitor with a larger area can be formed. Therefore, the present invention provides a method for manufacturing a capacitor of a dynamic random access memory. Gates are formed on the substrate at least. The medium size of the substrate on the gate side is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). -Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 47 1 4uv r.di) c / 002 A7 _4Ϊ 0468_B7______ V. Description of the invention (2) The drain is formed and the substrate is formed The first insulating layer includes: forming a termination layer on the first insulating layer; and patterning the termination layer to form an opening, exposing the first insulating layer above the drain electrode. A second insulation layer is then formed over the termination layer and in the opening. Then remove the second insulating layer above and around the opening to the termination layer to form a crown opening, and remove the first insulating layer below the opening to form a contact window opening to expose the drain electrode. Next, a conformal first conductive layer is formed in the crown opening and the contact window opening to form a first electrode of the capacitor. Then, a conformal dielectric layer is formed on the first conductive layer, and then a conformal second conductive layer is formed on the dielectric layer and the second insulating layer around the crown opening to form a second electrode of the capacitor. The materials of the first insulation layer and the second insulation layer are the same, and the materials of the termination layer, the first insulation layer, and the second insulation layer are different. In the above method, it can also be applied to a substrate on which an insulating layer is formed and a contact plug has been formed in the insulating layer. In this way, the contact window opening exposed in the above method is not the drain but the contact plug, and the contact plug and the drain are electrically connected to each other. The other implementations are the same. According to the method of the present invention, one of the characteristics is to use the termination layer as the removal end point of the second insulating layer to define the position of the lower electrode of the capacitor in the second insulating layer. A contact window opening is formed in the first insulating layer by using the termination layer as a mask for etching the first insulating layer. Therefore, it has the following advantages. First, the coronal opening and the contact window opening can be formed at the same time in the same step. 2. The lower electrode of the capacitor and the node contact in the opening of the contact window can be formed at one time, and there is no problem of interface contact resistance between the two. 3. The paper size can be added to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling this page)
I 47]4l'、.1'cUW〇iH〇 468 A7 _____B7___ 五、發明說明（,） 。加電谷器的面積’—固—重養_歷直JS_EL也_成_·爲l容納部彳分麗容器 之空間。 -一 . 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第ΙΑ - 1E圖是依照本發明較佳實施例的一種動態隨 機存取記憶體之電容器的製造流程剖面圖；以及 第2A - 2C圖是是依照本發明另一較佳實施例的一種 動態隨機存取記憶體之電容器的製造流程剖面圖。 圖式之標記說明： 100、200 :基底 102、202 :閘極 104、204 :汲極 106、206 :源極 .108、208 :第一絕緣層 1 10、118、216、224 :開口 112、218 :位元線 114、214 :第二絕緣層 ， 116、220 :第三絕緣層 12〇、:第四絕緣層 122a、228a :冠狀開口 122b、22Sb :節點接觸窗開口 124、234 :第二導電層 木紙張尺度適用中國國家標準（CNS)A4規格<210 X 297公釐） ------.---j-----— (請先閱讀背面之注意事項再填寫本頁) 幻· --線· 經濟部智慧財產局員工消費合作社印製 /〇fl24iQ468 B7_ 五、發明說明（/) 126、232 :介電層 128 :第三導電層 2 1 0、2 1 2 :插塞 (請先閱讀背面之注意事項再填寫本頁) 2 2 6 :第五絕緣層 230 :第一導電層 實施例一 請參照第ΙΑ - 1E圖，其繪示依照本發明較佳實施例 的一種動態隨機存取記憶體之電容器的製造流程剖面圖。 請參照第1A圖，基底100上，形成有閘極102，在 閘極102 —側之基底100中形成有汲極104，閘極102之 另一側基底1〇〇中形成有源極106。 在基底100上形成第一絕緣層108，然後圖案化第一 絕緣層108,形成開口 110以暴露出源極106。第一絕緣 層108的材質例如可爲氧化矽，其形成的方法例如可爲化 學氣相沈積法。 經濟部智慧財產局員工消費合作社印製 請參照第1B圖，形成第一導電層於第一絕緣層108 之上以及開口 110之中，再進行例如微影蝕刻製程，將第 一導電層圖案化以在開口 110以及開口 Π〇周圍部份之第 一絕緣層〖08之上形成112。位元線112的材質例如可爲 摻雜多晶矽，而形成的方法例如可爲化學氣相沈積法。 接下來，依序形成第二絕緣層U4和第三絕緣層116。 第二絕緣層Π4的材質例如可爲氧化矽，其形成的方法例 如可爲化學氣相沈積法。第三絕緣層Π6的材質和第二絕 緣層114的材質不一樣，例如可爲氮化矽，其形成的方法 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 A7\A\w Γ dot:/(KJ2 410468 五、發明說明（厂） 例如亦可爲化學氣相沈積法，而其厚度約200 - 500埃。 請參照第1C圖，圖案化第三絕緣層116，形成開口 11 8 以暴露出位於汲極104上方之第二絕緣層Π4。形成開口 118的方法例如可用微影蝕刻法。 請參照第〗D圖，形成第四絕緣層120於第三絕緣層 116之上以及開口 U8之中。其中第四絕緣層120和第二 絕緣層114的材質相同，例如可同爲氧化矽，而其形成的 方法例如可用化學氣相沈積法》 然後例如利用微影蝕刻法，先以第三絕緣層Π6爲去 除終點，去除位於開口 118上方以及其周圍部份之第四絕 緣層12〇，形成冠狀開口 122a來暴露第二絕緣層114的表 面；並以第三絕緣層116爲第二絕緣層H4的罩幕，然後 繼續去除位在開口 118下方部份之第二絕緣層114,形成 節點接觸窗開口 122b，以暴露出汲極104。 在此因爲第四絕緣層120和第二絕緣層114的材質相 同，所以冠狀開口 122a和節點接觸窗開口 122b可以在同 一去除步驟中形成。而又第四絕緣層120和第二絕緣層114 之間夾著一層材質不同的第三絕緣層116，所以可利用第 三絕緣層1丨6,一步形成大小不同的冠狀開口 122a和節點 接觸窗開口 12 2 b。 請參照第1E圖，形成共形之第二導電層124於冠狀 開口 l22a '開口 118和節點接觸窗開口 122b中，以形成 電容器之下電極。第二導電層124例如可爲表面形成有半 球形砂晶粒（hemi-sphere grain ; HSG)之摻雜多晶政層。 本紙張尺度適用中國國家標準（QMS)A4規格（210 X 297公楚〉 (請先閣讀背面之注意事項再填寫本頁) 訂---r . --線- 經濟部智慧財產局員工消費合作社印製 47 Uuv r.doo/〇〇2 ^ _410468_B7_ 五、發明說明（b) 然後形成共形之介電層126於第一導電層124之上， 介電層124例如可爲氧化矽一氮化矽一氧化矽複合層。 接著形成共形之第三導電層128於介電層126以及冠 狀開口 122a周圍之第四絕緣層120之上，以形成電容器 之第二電極。 實施例二 請參照第2A - 2C圖，其繪示依照本發明另一較佳實 施例的一種動態隨機存取記憶體之電容器的製造流程剖面 圖。在實施例二中將描述本發明之另一種變化型應用。 請參照第2A圖，基底200上，形成有閘極2〇2，在 閘極202 —側之基底200中形成有汲極204，閘極202之 另一側基底200中形成有源極206。基底200之上形成有 第一絕緣層208,第一絕緣層208中形成有插塞210、212。 其中插塞210和汲極204電性相接，插塞2U和源極206 電性相接。 接下來，形成第二絕緣層214，且在插塞212之上方， 形成開口 2 16於第二絕緣層214之中。然後在開口 216之 中以及開口 216周圍之第二絕緣層214之上形成位元線 218 ° 然後再依序形成第三絕緣層220、第四絕緣層222於 基底200之上。其中第三絕緣層220例如可爲氧化矽，其 形成的方法例如可爲化學氣相沈積法。而第四絕緣層222 的材質和第二絕緣層220的材質不一樣，例如可爲氮化矽’ 8 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） (請先間讀背面之注意事項再填寫本頁) . -線_ 經濟部智慧財產局員工消費合作杜印製 經濟部智慧財產局員工消費合作社印製 47 I4iw r.doc/002 A7_41Q468__B7______ 五、發明說明（1 ) 其形成的方法例如可爲化學氣相沈積法，而其厚度約2⑽-500 埃。 圖案化第四絕緣層222，形成開口 224以暴露出位於 汲極204上方之第三絕緣層220的表面。形成開口 224的 方法例如可用微影蝕刻法。 請參照第2B圖，形成第五絕緣層226於第四絕緣層 222之上以及開口 224之中。其中第五絕緣層226和第三 絕緣層220的材質相同，例如可同爲氧化矽，而其形成的 方法例如可用化學氣相沈積法。 在第五絕緣層226中蝕刻出冠狀開口 228a ’以暴露出 開口 224周圍之第四絕緣層222以及開口 224底部之第三 絕緣層220，並接著蝕刻開口 224所暴露出之第三絕緣層 220，以形成節點接觸窗開口 228b來暴露出插塞210。 在此所應用之原則和實施例一相同，亦是利用相同材 質的第五絕緣層226和第三絕緣層220夾著材質不同的第 四絕緣層222,以第四絕緣層222爲去除第五絕緣層226 之去除終點，同時又利用第四絕緣層222爲去除第三絕緣 層220之罩幕，以形成上大下小的冠狀開口 228a和節點 接觸窗開口 228b。 請參照第2C圖，形成共形之第一導電層230於冠狀 開口 228a、開口 224和節點接觸窗開口 228b中，以形成 電容器之下電極。第一導電層230例如可爲表面形成有半 球形矽晶粒之摻雜多晶矽層。 然後形成共形之介電層232於第一導電層230之上， (請先閱讀背面之注意事項再填寫本頁) 擧· 訂： --線_ 本紙張尺度適用令國國家標準（CNS)A4規格<210 X 297公釐〉 4 7 I 41 w Γ. do c / 00 2 A7 B7 五、發明說明（2 ) 介電層2 3 2例如可爲氧化砂一氮化砂一氧化砍複合層。 (請先閱讀背面之注意事項再填寫本頁) 接著形成共形之第二導電層234於介電層232以及冠 狀開口 228a周圍之第五絕緣層226之上，以形成電容器 之第二電極。 由上述本發明較佳實施例可知，其中之一特徵爲利用 材質相同的上下兩層絕緣層夾著中間一層材質不同的絕緣 層，如此在去除部份的上層絕緣層時，中間的絕緣層可爲 去除終點，以定義出電容器下電極在上層絕緣層中的位置 大小。並利用中間的絕緣層爲蝕刻下層絕緣層之罩幕，在 下層絕緣層中形成接觸窗開口。所以應用本發明具有下列 優點。 一、 在同一步驟中即可同時決定電容器下電極在絕緣 層中的位置大小以及接觸窗開口的位置大小。 二、 電容器的下電極和接觸窗開口中的節點接點可以 一次沈積完成，二者之間沒有界面接觸阻値之問 .題。 '經濟部智慧財產局員工消費合作社印製 三、 可增加電容器的面積，因爲增加了位在接觸窗開 口中部份之電容器面積。如此可增進電容器電荷 儲存能力來降低再補充的頻率，記憶體的效率也 就跟著提昇了。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 I 0 " 本紙張尺度適用_國國家標準<CNS：)A4規格（210 X 297公釐〉I 47] 4l ', .1' cUW〇iH〇 468 A7 _____B7___ 5. Description of the invention (,). The area of the power-supplying device ’—solid—recultivation _ calendar straight JS_EL also _ Cheng _ · is the space of the container containing the fanli. -I. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments and the accompanying drawings to make a detailed description as follows: Brief description of the drawings: Figures IA-1E are cross-sectional views of a manufacturing process of a dynamic random access memory capacitor according to a preferred embodiment of the present invention; and Figures 2A-2C are a dynamic random access memory according to another preferred embodiment of the present invention Take a sectional view of the manufacturing process of the capacitor of the memory. Description of the drawing symbols: 100, 200: substrate 102, 202: gate 104, 204: drain 106, 206: source. 108, 208: first insulating layer 1 10, 118, 216, 224: opening 112, 218: bit lines 114, 214: second insulation layer, 116, 220: third insulation layer 120, fourth insulation layer 122a, 228a: crown openings 122b, 22Sb: node contact window openings 124, 234: second The size of conductive laminated wood paper is applicable to China National Standard (CNS) A4 specifications < 210 X 297 mm) ------.--- j ------- (Please read the precautions on the back before filling in this Page) Magic · -Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 〇fl24iQ468 B7_ V. Description of the invention (/) 126, 232: Dielectric layer 128: Third conductive layer 2 1 0, 2 1 2: Plug (Please read the precautions on the back before filling this page) 2 2 6: Fifth insulating layer 230: First conductive layer Embodiment 1 Please refer to Figures IA-1E, which shows a preferred embodiment according to the present invention A cross-sectional view of a manufacturing process of a dynamic random access memory capacitor. Referring to FIG. 1A, a gate electrode 102 is formed on the substrate 100, a drain electrode 104 is formed on the substrate 100 on one side of the gate electrode 102, and a source electrode 106 is formed on the substrate 100 on the other side of the gate electrode 102. A first insulating layer 108 is formed on the substrate 100, and then the first insulating layer 108 is patterned to form an opening 110 to expose the source electrode 106. The material of the first insulating layer 108 may be, for example, silicon oxide, and a method for forming the first insulating layer 108 may be, for example, a chemical vapor deposition method. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to FIG. 1B, forming a first conductive layer on the first insulating layer 108 and in the opening 110, and then performing a lithographic etching process to pattern the first conductive layer A first insulating layer [08] is formed on the opening 110 and a part around the opening 110. The material of the bit lines 112 may be, for example, doped polycrystalline silicon, and the formation method may be, for example, a chemical vapor deposition method. Next, a second insulating layer U4 and a third insulating layer 116 are sequentially formed. The material of the second insulating layer Π4 may be, for example, silicon oxide, and a method of forming it may be, for example, a chemical vapor deposition method. The material of the third insulating layer Π6 is different from the material of the second insulating layer 114, for example, it can be silicon nitride, and the method of forming this paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 A7 \ A \ w Γ dot: / (KJ2 410468) 5. Description of the invention (factory) For example, it can also be a chemical vapor deposition method, and its thickness is about 200-500 angstroms. Please refer to Figure 1C to pattern the third insulating layer 116, the opening 11 8 is formed to expose the second insulating layer Π4 above the drain 104. The method for forming the opening 118 can be, for example, a photolithography method. Referring to FIG. D, a fourth insulating layer 120 is formed on the third insulating layer. Above the layer 116 and in the opening U8. The materials of the fourth insulating layer 120 and the second insulating layer 114 are the same, for example, they can be the same as silicon oxide, and the formation method can be, for example, chemical vapor deposition method, and then, for example, using The shadow etching method firstly uses the third insulating layer Π6 as a removal end, removes the fourth insulating layer 120 above the opening 118 and its surroundings, and forms a crown-shaped opening 122a to expose the surface of the second insulating layer 114; Three insulating layers 116 are second The cover of the insulating layer H4, and then continues to remove the second insulating layer 114 located below the opening 118 to form a node contact window opening 122b to expose the drain 104. Here, the fourth insulating layer 120 and the second insulating layer The material of the layer 114 is the same, so the crown opening 122a and the node contact window opening 122b can be formed in the same removal step. A third insulating layer 116 of a different material is sandwiched between the fourth insulating layer 120 and the second insulating layer 114. Therefore, the third insulating layer 1 丨 6 can be used to form a crown opening 122a and a node contact window opening 12 2 b of different sizes in one step. Referring to FIG. 1E, a conformal second conductive layer 124 is formed on the crown opening 1222a. 118 and the node contact window opening 122b to form the lower electrode of the capacitor. The second conductive layer 124 may be, for example, a doped polycrystalline layer with hemi-sphere grain (HSG) formed on the surface. The standard is applicable to China National Standard (QMS) A4 specification (210 X 297). (Please read the precautions on the back before filling out this page.) Order --- r. System 4 7 Uuv r.doo / 〇〇2 ^ _410468_B7_ 5. Description of the invention (b) Then a conformal dielectric layer 126 is formed on the first conductive layer 124. The dielectric layer 124 may be, for example, silicon oxide-silicon nitride- A silicon oxide composite layer. A conformal third conductive layer 128 is then formed on the dielectric layer 126 and the fourth insulating layer 120 around the crown opening 122a to form a second electrode of the capacitor. Embodiment 2 Please refer to FIGS. 2A to 2C, which are cross-sectional views showing a manufacturing process of a dynamic random access memory capacitor according to another preferred embodiment of the present invention. In the second embodiment, another modified application of the present invention will be described. Referring to FIG. 2A, a gate electrode 202 is formed on the substrate 200, a drain electrode 204 is formed on the substrate 200 on one side of the gate electrode 202, and a source electrode 206 is formed on the substrate 200 on the other side of the gate electrode 202. A first insulating layer 208 is formed on the substrate 200, and plugs 210 and 212 are formed in the first insulating layer 208. The plug 210 and the drain 204 are electrically connected, and the plug 2U and the source 206 are electrically connected. Next, a second insulating layer 214 is formed, and an opening 2 16 is formed in the second insulating layer 214 above the plug 212. A bit line 218 ° is then formed in the opening 216 and above the second insulating layer 214 around the opening 216, and then a third insulating layer 220 and a fourth insulating layer 222 are sequentially formed on the substrate 200. The third insulating layer 220 may be, for example, silicon oxide, and a method for forming the third insulating layer 220 may be, for example, a chemical vapor deposition method. The material of the fourth insulating layer 222 is different from the material of the second insulating layer 220. For example, it can be silicon nitride. 8 This paper size applies to the Chinese National Standard (CNS) A4 specification (210x 297 mm) (please read first) Note on the back, please fill in this page again.) -Line _ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperation Du printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 47 I4iw r.doc / 002 A7_41Q468__B7______ 5. Description of the invention (1) Its The formation method may be, for example, a chemical vapor deposition method, and its thickness is about 2 ⑽ to 500 angstroms. The fourth insulating layer 222 is patterned to form an opening 224 to expose the surface of the third insulating layer 220 above the drain 204. A method of forming the opening 224 is, for example, a lithography method. Referring to FIG. 2B, a fifth insulating layer 226 is formed on the fourth insulating layer 222 and in the opening 224. The fifth insulating layer 226 and the third insulating layer 220 are made of the same material, such as silicon oxide, and the method of forming the fifth insulating layer 226 can be, for example, chemical vapor deposition. The crown-shaped opening 228 a ′ is etched in the fifth insulating layer 226 to expose the fourth insulating layer 222 around the opening 224 and the third insulating layer 220 at the bottom of the opening 224, and then the third insulating layer 220 exposed by the opening 224 is etched. To form a node contact window opening 228b to expose the plug 210. The principle applied here is the same as in the first embodiment, and the fifth insulating layer 226 and the third insulating layer 220 of the same material are used to sandwich the fourth insulating layer 222 of different materials, and the fourth insulating layer 222 is used to remove the fifth The end point of the insulation layer 226 is removed, and the fourth insulation layer 222 is used to remove the cover of the third insulation layer 220 to form a crown opening 228a and a node contact window opening 228b. Referring to FIG. 2C, a conformal first conductive layer 230 is formed in the crown-shaped opening 228a, the opening 224, and the node contact window opening 228b to form the lower electrode of the capacitor. The first conductive layer 230 may be, for example, a doped polycrystalline silicon layer having hemispherical silicon grains formed on the surface. Then, a conformal dielectric layer 232 is formed on the first conductive layer 230. (Please read the precautions on the back before filling this page). Order: --line_ This paper applies the national standard (CNS) A4 specifications < 210 X 297 mm> 4 7 I 41 w Γ. Do c / 00 2 A7 B7 V. Description of the invention (2) The dielectric layer 2 3 2 can be, for example, oxide sand-nitride sand-oxide cut compound Floor. (Please read the precautions on the back before filling this page) Then a conformal second conductive layer 234 is formed on the dielectric layer 232 and the fifth insulating layer 226 around the crown opening 228a to form the second electrode of the capacitor. It can be known from the foregoing preferred embodiments of the present invention that one of the features is the use of two insulating layers of the same material that sandwich the middle insulating layer of different materials, so that when a part of the upper insulating layer is removed, the middle insulating layer can be To remove the end point, the position of the lower electrode of the capacitor in the upper insulating layer is defined. The middle insulating layer is used as a mask for etching the lower insulating layer to form a contact window opening in the lower insulating layer. Therefore, the application of the present invention has the following advantages. 1. The position of the lower electrode of the capacitor in the insulating layer and the position of the opening of the contact window can be determined at the same time in the same step. 2. The lower electrode of the capacitor and the node contact in the opening of the contact window can be deposited at one time, and there is no problem of interface contact resistance between the two. 'Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 3. The area of the capacitor can be increased because the area of the capacitor located in the opening of the contact window is increased. In this way, the capacitor's charge storage capacity can be improved to reduce the frequency of replenishment, and the efficiency of the memory is also improved. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. I 0 " This paper size is applicable _ national standard & CNS :) A4 size (210 X 297 mm>