415093 2242twf.doc/002 八了 B7 五、發明説明（I ) 本發明係有關於一種形成動態隨機存取記憶體 (dram)電容器的方法，其電容器平板具有一橫切面爲 類似希臘字ψ的形狀，以提供向外延展的表面積以及電容增 加的能力，同時並應用半圓球砂晶粒（Hemispherical Grain Polysilicon，HSG)來增加表面積。415093 2242twf.doc / 002 Eight B7 V. Description of the invention (I) The present invention relates to a method for forming a dynamic random access memory (dram) capacitor. The capacitor plate has a shape similar to the Greek word ψ in a cross section. In order to provide the extended surface area and the ability to increase the capacitance, at the same time, Hemispherical Grain Polysilicon (HSG) is used to increase the surface area.
Yun之美國專利案第5,389,568號描述一種DRAM電容 器，具有一外圍牆與一中心垂直支柱包含一孔洞的結構， 藉以增加電容器平板的表面積。U.S. Patent No. 5,389,568 to Yun describes a DRAM capacitor having a structure including a peripheral wall and a center vertical pillar including a hole, thereby increasing the surface area of a capacitor plate.
Jeong之美國專利案第5,571,742號描述一種電容器， 使用內連接的堆疊式電容平板以提供電容器表面積的增 加。Jeong U.S. Patent No. 5,571,742 describes a capacitor that uses an interconnected stacked capacitor plate to provide an increase in the surface area of the capacitor.
Koh之美國專利案第5,554,557號描述一種形成電容器 的方法，使用複晶矽邊牆間隙壁或柵欄（fence)形成電容 器的儲存電極。 經濟部中央標準局貝工消费合作社印製 * (請先閔讀背面之注項再填寫本頁) 美國專利申請序號VIS-86-030，名稱爲“A method of fabrication a capacitor storage node having a rugged-fin surface (具有高低不平鰭狀表面之電容器儲存節點的製造 方法）”，描述一種以一非晶矽平板依附在一複晶矽間柱 (stud)上之電容器形成的方法，藉由複晶矽間柱使電容器 平板保持在積體電路晶圓上，再利用一低壓回火步驟使非 晶矽平板表面粗糙化，增加電容器的表面積。 美國專利申請序號VIS-86-033,名稱同爲“具有高低 不平鰭狀表面之電容器儲存節點的製造方法”，描述一種 使用一 HSG層形成於一已定義圖案之非晶矽平板上的電容 3 本紙張尺度適用中國國家標準（CNS > A4规格（2丨0X297公釐) 41509 2242twf. doc/002 A7 B7 經濟部中央標準局負工消費合作社印掣 五、發明説明（2· ) · 器製作方法，於非晶矽平板與一介電層與HSG層內形成介 層窗孔洞，作爲與晶圓接觸區之一接觸窗，再利用一低壓 回火步驟使非晶矽平板表面粗糙化，增加電容器的表面 積。 本發明則提出一種形成動態隨機存取記憶體電容器的 方法，其電容器平板具有一橫切面爲類似希臘字Ψ的形狀， 以提供向外延展的表面積以及電容增加的能力，同時並應 用HSG來增加表面積。 積體電路的應用，特別是對DRAM的應用而言，如何 讓電容器具有足夠的儲存電容是相當重要的。尤其是當積 體電路晶片之尺寸愈來愈小，真正DRAM電路所能利用的 範圍受到限制，必須另尋他途使電容器的空間增加，以製 作具有足夠電容的電容器。 因此，本發明的目的便是提供一種當晶片面積變小 時，具有大表面積電容器儲存電極的形成方法。 根據本發明的目的，提供一種電容器儲存節點，其橫切 面形成類似希臘字ψ的形狀，包括步驟如下：提供一形成有 元件的積體電路基底，其上並形成多數個接觸區域與已平 坦化的一第一介電層；陸續沈積一第二介電層與一第三介 電層；蝕刻部份第三介電層，以定義第三介電層圖案，形 成位於接觸區域上方的多數個電容器孔洞；沈積一第一導 電層於第三介電層上；以一第四介電層塡滿電容器孔洞； 定義第四介電層、第一導電層、第三介電層、第二介電層 與第一介電層，以曝露出接觸區域，形成多數個接觸窗孔 4 ---------1¾.—— 一 . (請先Μ讀背面之注意事項再填寫本頁) 4Τ 線· 本紙張尺度逋用中國國家標準（CNS > A4规格（2丨〇><297公釐） 415093 2242twf.doc/002 A7 B7 五、發明説明（）） 洞；形成一第二導電層以塡滿接觸窗孔洞；蝕刻掉第三介 電層上之部份第一導電層、第二導電層與第四介電層，以. 形成由第一導電層與第二導電層所構成的一第一電容器平 板：蝕刻掉剩餘的第三介電層與剩餘的第四介電層；沈積 一第五介電層以覆蓋在第一電容器平板上；形成一第三導 電層於第五介電層上，以形成一第二電容器平板；以及定 義第五介電層與第三導電層之圖案，完成電容器的製造。 此外，更可在第四介電層形成之前，先形成一 HSG層以增 加電容器的表面積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 圖式之簡單說明： 第1〜9圖與第11〜12圖繪示本發明一較佳實施例的 電容器形成的流程圖； 第10圖繪75圖9之上視圖； 第13〜17圖與第19〜20圖爲延續圖1〜5所繪示本發 明另一較佳實施例的電容器形成的流程圖；以及 第18圖繪示圖17之上視圖。 圖式中標示之簡單說明： 10 基底 12 場氧化絕緣區 14 源極區 18 汲極區 22 閘氧化層 24 複晶砂閘極 26 字元線 28 氧化層 5 本紙張尺度適用中國國家橾準（CNS ) A4说格（210X 297公釐） - (請先閲讀背面之注意事項再填寫本頁) 、τ 經濟部中央標準局員工消費合作社印製 經濟部中央標隼局貝工消费合作社印*. 415093 2242twf.doc/002 八7 B7 五、發明説明（γ) 30 第一介電層 32 第二介電層 34 第三介電層 35 電容器孔洞 36 第一複晶矽層 38 第四介電層 40 接觸窗孔洞 41 插塞 42 第二複晶矽層 44 HSG層 48 實施例 第五介電層 50 第三複晶矽層 請參照第1〜12圖，其繪示本發明一較佳實施例之電 容器形成的流程圖。 第1圖繪示一積體電路基底10的部份剖面圖，包括汲 極區18、一源極區14、一場氧化絕緣區12、一閘氧化層 22以及一複晶矽閘極24。於基底10中之接觸區域，如本 例之源極區14上將形成與一電容器平板的電路連接。上述 元件顯示出部份的DRAM電路，包含形成在場氧化區12 的一複晶矽字元線26。再以未摻雜的氧化層28，例如厚度 約爲〗5〇0〜2500A，沈積於基底10上；沈積一第一介電層 3〇，例如厚度約爲3000〜4500A的硼磷矽玻璃（BPSG)， 或以臭氧和四乙基矽酸鹽（TEOS)爲氣體來源之化學氣相 沈積（LPCVD)法，形成厚度約爲3000〜4500A的氧化矽 層。 請參照第2圖，第一介電層30以化學機械硏磨（CMP) 法或乾蝕刻被平坦化，其上並沈積一第二介電層32，例如 爲氧化的氮化矽層或氮化矽層SixNy，厚度約爲60〜200A。 之後，如第3圖所示，一較厚的第三介電層34，例如 6 — _^---1----1¾.-------^-----威 (請先閲讀背面之注項再填寫本頁) 本纸張ΛΑϋ用中目ϋ家網^CNS > 21()><297公兼> 經濟部中央標準局員工消费合作社印製 415093 2242twf.doc/002 Β7 五、發明説明（i：) 爲厚度約9000〜135〇0人的BPSG層，或以臭氧和TEOS爲 氣體來源之LPCVD法，沈積厚度約9000〜135〇〇A於第二 介電層32上。 請參照第4圖，利用微影技術和乾式非等向性蝕刻定 義第三介電層34圖案，以第二介電層32爲終點蝕刻出一 電容器孔洞35。如圖4所示，電容器孔洞35位於源極區 14正上方，將形成前述的電路接觸。 請參照第5圖’ 一第一導電層36，例如爲厚度約800 〜1000A的複晶矽層，沈積覆蓋在電容器孔洞上。 請參照第6圖，一第四介電層38，例如爲BPSG層， 接著沈積形成，並利用回蝕刻或平坦化使第四介電層38僅 塡滿電容器孔洞。 請參照第7圖，形成一接觸窗孔洞40，利用微影技術 與乾蝕刻，定義第四介電層38、第一導電層36、第二介電 層32、第一介電層30與氧化層28圖案，使源極區〗4曝露 出。 請參照第8圖，沈積一第二導電層42，例如爲一複晶 砂層’塡滿接觸窗孔洞40形成一插塞41，作爲源極區14 與第一導電層从間的電路連接。 接著，請參照第9圖，將位於第三介電層上表面之部 份第一導電層36 '第二導電層42、插塞41與第四介電層 38 ,以電槳回蝕刻或CMP法移除，剩餘之第—導電層36 與插塞41構成之第一電容器平板，便形成如希臘字ψ的形 狀。由晶圓正上方所見的上視圖如第1〇圖所示，包含插塞 7 本紙張尺度適用中國國家榡準（CNS ) Α4現格（21〇χ297公釐） ----：----------β-----,^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 415093 2242twt-d〇c/002 A7 B7 五、發明説明（& ) 41、第一導電層36、第三介電層34與第四導電層38，圖9 便爲圖10中沿9-W線之剖面圖。 之後，請參照第Π圖，剩餘之第三介電層與第四介電 層被完全蝕刻掉，僅保留第一電容器平板46、41。請再參 照第12圖，沈積一第五介電層48，例如爲NO、ΟΝΟ或 Ta205，厚度約爲55〜300Α，覆蓋在第一電容器平板上。 一第三導電層50，例如爲複晶矽層，接著沈積在第五介電 層48上。最後，定義第五介電層48與第三導電層50完成 電容器的製作。 請參照前述之第1〜5圖與13〜20圖，繪示本發明另 一較佳實施例之電容器形成的流程圖。 延續圖5之製程後，請參照第13圖，以沈積座落法 (deposited site method)或種植法（seeding method)，於 第一電層36上形成一 HSG層44。 請參照第Η圖，沈積一第四介電層38，例如爲BPSG 層，再以回蝕刻或平坦化使第四介電層38僅塡滿電容器孔 洞。 請參照第15圖，形成一接觸窗孔洞40，利用微影技術 與乾蝕刻，定義第四介電層38、HSG層44、第一導電層36、 第二介電層32、第一介電層30與氧化層28圖案，使源極 區14曝露出。 請參照第16圖，沈積一第二導電層42，例如爲一複晶 矽層，塡滿接觸窗孔洞40形成一插塞41，作爲源極區14 與HSG層44和第一導電層36間的電路連接。 8 本紙張尺度適用中國國家標準（CNS )八4規格（210Χ297公釐） 「=_ ^1 ^^1 ^^1 - - ^^1 I ^1 -- - -- n^i ^^1 - - - - - 1^1 - - - n^i ^^1 (請先閲讀背面之注意事項再填寫本頁) A7 B7 415093 2 2 42twf. doc/002 五、發明説明（/| ) 接著’請參照第Π圖，將位於第三介電層上表面之部 份HSG層44、第一導電層36、第二導電層42、插塞41與 第四介電層38,以電漿回蝕刻或CMP法移除，剩餘之第一 導電層36與插塞41構成之第一電容器平板，便形成如希 臘字Ψ的形狀。由晶圓正上方所見的上視圖如第18圖所 示，包含插塞41、HSG層44、第一導電層36、第三介電 層34與第四導電層38,圖17便爲圖18中沿17-17,線之剖 面圖。 之後，請參照第19圖，剩餘之第三介電層與第四介電 層被完全蝕刻掉，僅保留第一電容器平板46、41。請再參 照第12圖，沈積—第五介電層48，例如爲NO、ΟΝΟ或 Ta2〇5 ’厚度約爲55〜3〇〇人，覆蓋在第一電容器平板上。 —第三導電層5〇，例如爲複晶矽層，接著沈積在第五介電 層48上。最後，定義第五介電層48與第三導電層50完成 電容器的製作。 雖然本發明是以DRAM電路且特別爲高電容電容器在 DRAM的應用爲實施例，然其並非用以限定本發明，任何 熟習此技藝者，在不脫離本發明之精神和範圍內，當可作 各種之更動與潤飾，而適用於許多不同的電路中，因此本 發明之保護範圍當視後附之申請專利範圍所界定者爲準。 9 I-^---^----—裝-----·--訂-----線 (請先Μ讀背面之注意事項再填寫本頁)Koh U.S. Patent No. 5,554,557 describes a method of forming a capacitor using a polycrystalline silicon sidewall spacer or fence to form the storage electrode of a capacitor. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives * (Please read the notes on the back before filling out this page) US Patent Application Serial No. VIS-86-030, entitled "A method of fabrication a capacitor storage node having a rugged -fin surface (manufacturing method of capacitor storage node with uneven fin surface) ", describes a method for forming a capacitor by attaching an amorphous silicon plate on a stud of a polycrystalline silicon, by using the polycrystalline silicon The pillars keep the capacitor plate on the integrated circuit wafer, and then use a low-pressure tempering step to roughen the surface of the amorphous silicon plate and increase the surface area of the capacitor. US Patent Application No. VIS-86-033, also named "Method for Manufacturing Capacitor Storage Nodes with Uneven Finned Surfaces", describes a capacitor formed using an HSG layer on an amorphous silicon flat plate with a defined pattern 3 This paper size applies to Chinese national standards (CNS > A4 specifications (2 丨 0X297 mm) 41509 2242twf. Doc / 002 A7 B7 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2 ·) A method is to form a dielectric window hole in an amorphous silicon plate and a dielectric layer and an HSG layer as a contact window with a wafer contact area, and then use a low-pressure tempering step to roughen the surface of the amorphous silicon plate and increase The surface area of the capacitor. The present invention proposes a method for forming a dynamic random access memory capacitor. The capacitor plate has a shape similar to a Greek word cross section to provide an outwardly extending surface area and the capacity to increase capacitance. Apply HSG to increase the surface area. For integrated circuit applications, especially for DRAM applications, how to make capacitors have sufficient storage capacitance is quite equivalent. It is necessary. Especially when the size of integrated circuit chips is getting smaller and smaller, the real DRAM circuit can be used in a limited range, and another way must be used to increase the space of the capacitor to make a capacitor with sufficient capacitance. The object of the invention is to provide a method for forming a capacitor storage electrode with a large surface area when the wafer area becomes smaller. According to the purpose of the present invention, a capacitor storage node is provided whose cross-section is formed into a shape similar to the Greek word ψ, including the following steps: Provided is an integrated circuit substrate on which elements are formed, and a plurality of contact areas and a first dielectric layer that has been planarized are formed thereon; a second dielectric layer and a third dielectric layer are successively deposited; and an etched portion The third dielectric layer defines the third dielectric layer pattern and forms a plurality of capacitor holes above the contact area; deposits a first conductive layer on the third dielectric layer; and fills the capacitor with a fourth dielectric layer A hole; defining a fourth dielectric layer, a first conductive layer, a third dielectric layer, a second dielectric layer, and a first dielectric layer to expose a contact area, and A large number of contact window holes 4 --------- 1¾ .---- 1. (Please read the precautions on the back before filling in this page) 4T line · This paper adopts Chinese National Standard (CNS & gt A4 specification (2 丨 〇 < 297 mm) 415093 2242twf.doc / 002 A7 B7 V. Description of the invention ()) Hole; forming a second conductive layer to fill the contact hole of the window; etching away the third dielectric A portion of the first conductive layer, the second conductive layer, and the fourth dielectric layer on the electrical layer to form a first capacitor plate composed of the first conductive layer and the second conductive layer: the remaining third A dielectric layer and the remaining fourth dielectric layer; depositing a fifth dielectric layer to cover the first capacitor plate; forming a third conductive layer on the fifth dielectric layer to form a second capacitor plate; And define the pattern of the fifth dielectric layer and the third conductive layer to complete the manufacturing of the capacitor. In addition, an HSG layer can be formed before the fourth dielectric layer is formed to increase the surface area of the capacitor. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings. Brief description of the drawings: Figures 1 to 9 and Figures 11 to 12 show the flow chart of capacitor formation in a preferred embodiment of the present invention; Figure 10 is a top view of Figure 75; Figures 13 to 17 and 19 to 20 are flowcharts of the capacitor formation according to another preferred embodiment of the present invention shown in FIGS. 1 to 5; and FIG. 18 is a top view of FIG. 17. Brief descriptions indicated in the drawings: 10 substrate 12 field oxidation insulation region 14 source region 18 drain region 22 gate oxide layer 24 polycrystalline sand gate 26 word line 28 oxide layer 5 This paper standard is applicable to Chinese national standards ( CNS) A4 grid (210X 297 mm)-(Please read the precautions on the back before filling out this page), τ Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs *. 415093 2242twf.doc / 002 8 7 B7 V. Description of the invention (γ) 30 First dielectric layer 32 Second dielectric layer 34 Third dielectric layer 35 Capacitor hole 36 First polycrystalline silicon layer 38 Fourth dielectric layer 40 Contact window hole 41 Plug 42 Second polycrystalline silicon layer 44 HSG layer 48 Embodiment Fifth dielectric layer 50 Third polycrystalline silicon layer Please refer to FIGS. 1-12, which shows a preferred embodiment of the present invention Flow chart of capacitor formation. FIG. 1 shows a partial cross-sectional view of an integrated circuit substrate 10, including a drain region 18, a source region 14, a field oxide insulation region 12, a gate oxide layer 22, and a polycrystalline silicon gate 24. A contact region in the substrate 10, such as the source region 14 in this example, will form a circuit connection with a capacitor plate. The above-mentioned element shows a part of a DRAM circuit including a polycrystalline silicon word line 26 formed in the field oxide region 12. Then, an undoped oxide layer 28 is deposited on the substrate 10 with a thickness of, for example, about 500 to 2500 A; a first dielectric layer 30 is deposited, for example, a borophosphosilicate glass with a thickness of about 3000 to 4500 A ( BPSG), or a chemical vapor deposition (LPCVD) method using ozone and tetraethyl silicate (TEOS) as gas sources to form a silicon oxide layer with a thickness of about 3000 to 4500 A. Referring to FIG. 2, the first dielectric layer 30 is planarized by a chemical mechanical honing (CMP) method or dry etching, and a second dielectric layer 32 is deposited thereon, such as an oxidized silicon nitride layer or nitrogen. Silicone layer SixNy, thickness is about 60 ~ 200A. Afterwards, as shown in FIG. 3, a thicker third dielectric layer 34 is, for example, 6 — _ ^ --- 1 ---- 1¾ .------- ^ ----- Wei ( Please read the notes on the back before filling in this page) This paper ΛΑϋUsed in the homepage ^ CNS > 21 () > < 297 Public > Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economy 415093 2242twf .doc / 002 Β7 V. Description of the invention (i :) is a BPSG layer with a thickness of about 9000 to 13500 people, or LPCVD method using ozone and TEOS as gas sources, and a thickness of about 9,000 to 135,000 A is deposited on the second On the dielectric layer 32. Referring to FIG. 4, a pattern of the third dielectric layer 34 is defined by using a lithography technique and dry anisotropic etching, and a capacitor hole 35 is etched with the second dielectric layer 32 as an end point. As shown in Fig. 4, the capacitor hole 35 is located directly above the source region 14 and will form the aforementioned circuit contact. Please refer to FIG. 5 ′. A first conductive layer 36 is, for example, a polycrystalline silicon layer having a thickness of about 800 to 1000 A, which is deposited and covered on the capacitor hole. Referring to FIG. 6, a fourth dielectric layer 38 is, for example, a BPSG layer, and is then deposited and formed, and the fourth dielectric layer 38 is only filled with capacitor holes by using etch-back or planarization. Referring to FIG. 7, a contact window hole 40 is formed, and the fourth dielectric layer 38, the first conductive layer 36, the second dielectric layer 32, the first dielectric layer 30, and the oxide are defined using lithography and dry etching. The layer 28 is patterned so that the source region 4 is exposed. Referring to FIG. 8, a second conductive layer 42 is deposited, for example, a polycrystalline sand layer 'fills the contact hole 40 and forms a plug 41 as a circuit connection between the source region 14 and the first conductive layer. Next, referring to FIG. 9, a portion of the first conductive layer 36 ′, the second conductive layer 42, the plug 41 and the fourth dielectric layer 38 located on the upper surface of the third dielectric layer is etched back or CMP by electric paddle. The first capacitor plate formed by the remaining first conductive layer 36 and the plug 41 is formed by a method such as the Greek word ψ. The top view seen from directly above the wafer is shown in Figure 10, which includes plugs. 7 paper sizes are applicable to China National Standards (CNS) A4 (21〇297297 mm) ----: --- ------- β -----, ^ (Please read the notes on the back before filling this page) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 415093 2242twt-d〇c / 002 A7 B7 5 &Amp; Invention 41, the first conductive layer 36, the third dielectric layer 34 and the fourth conductive layer 38, FIG. 9 is a cross-sectional view taken along line 9-W in FIG. After that, referring to FIG. Π, the remaining third dielectric layer and the fourth dielectric layer are completely etched away, and only the first capacitor plates 46 and 41 remain. Please refer to FIG. 12 again, and deposit a fifth dielectric layer 48, such as NO, ONO or Ta205, with a thickness of about 55 ~ 300A, and cover the first capacitor plate. A third conductive layer 50, such as a polycrystalline silicon layer, is then deposited on the fifth dielectric layer 48. Finally, the fifth dielectric layer 48 and the third conductive layer 50 are defined to complete the fabrication of the capacitor. Please refer to the aforementioned Figures 1 to 5 and 13 to 20 for a flowchart of forming a capacitor according to another preferred embodiment of the present invention. After continuing the process of FIG. 5, please refer to FIG. 13 to form a HSG layer 44 on the first electrical layer 36 by a deposited site method or a seeding method. Referring to the first figure, a fourth dielectric layer 38 is deposited, such as a BPSG layer, and then the fourth dielectric layer 38 is only filled with capacitor holes by etch-back or planarization. Referring to FIG. 15, a contact window hole 40 is formed, and the fourth dielectric layer 38, the HSG layer 44, the first conductive layer 36, the second dielectric layer 32, and the first dielectric are defined using a lithography technique and dry etching. The layer 30 and the oxide layer 28 are patterned to expose the source region 14. Referring to FIG. 16, a second conductive layer 42 is deposited, for example, a polycrystalline silicon layer, and a contact hole 40 is filled to form a plug 41 as the source region 14 and the HSG layer 44 and the first conductive layer 36. Circuit connection. 8 This paper size is in accordance with China National Standard (CNS) 8-4 specification (210 × 297 mm) "= _ ^ 1 ^^ 1 ^^ 1--^^ 1 I ^ 1---n ^ i ^^ 1- ----1 ^ 1---n ^ i ^^ 1 (Please read the notes on the back before filling out this page) A7 B7 415093 2 2 42twf. Doc / 002 5. Description of the invention (/ |) Then 'Please Referring to FIG. Π, a part of the HSG layer 44, the first conductive layer 36, the second conductive layer 42, the plug 41, and the fourth dielectric layer 38 on the upper surface of the third dielectric layer is etched back by plasma or After the CMP method is removed, the first capacitor plate composed of the remaining first conductive layer 36 and the plug 41 is formed into a shape like a Greek letter. The top view seen directly above the wafer is shown in FIG. 18, which includes plugs. The plug 41, the HSG layer 44, the first conductive layer 36, the third dielectric layer 34, and the fourth conductive layer 38. FIG. 17 is a cross-sectional view taken along line 17-17 in FIG. 18. Then, refer to FIG. 19 The remaining third dielectric layer and the fourth dielectric layer are completely etched away, and only the first capacitor plates 46 and 41 remain. Please refer to FIG. 12 again and deposit the fifth dielectric layer 48, for example, NO, ON. Or Ta205 'thickness is about 55 ~ 300 people Covered on the first capacitor plate.-A third conductive layer 50, such as a polycrystalline silicon layer, is then deposited on the fifth dielectric layer 48. Finally, the fifth dielectric layer 48 and the third conductive layer 50 are defined. Production of capacitors. Although the present invention is based on the DRAM circuit and the application of high-capacity capacitors in DRAM as an example, it is not intended to limit the present invention. As it can be modified and retouched, it is applicable to many different circuits, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 9 I-^ --- ^ --- --- install ----- · --order ----- line (please read the precautions on the back before filling in this page)
經濟部中央樣準局貝工消費合作社印II 本紙張尺度適用中國®家標率（CNS ) Α4規格u 10X297公釐）Central Samples Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives Co., Ltd. II This paper size applies to China® House Standard Rate (CNS) Α4 size u 10X297 mm