JP2501647B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device capable of random input / output of arbitrary stored information and a method for manufacturing the same.

[Conventional technology]

In recent years, the demand for semiconductor memory devices has rapidly expanded due to the remarkable spread of information devices such as computers, and there is a tendency for those having a large-scale memory capacity as a function and capable of high-speed operation. Accordingly, various technological developments relating to high integration and high-speed response or high reliability of semiconductor memory devices are being advanced.

By the way, a DRAM (Dynamic Random Access) is used as a semiconductor memory device capable of random input / output of stored information.
Memory), and a normal DRAM is composed of a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input / output with the outside. FIG. 6 shows the configuration of a general DRAM. 1 is a block diagram showing a memory cell array 2 for accumulating a data signal of storage information and an address signal for selecting a memory cell forming a unit storage circuit of this memory cell array 2 from the outside. A row-and-column address buffer 3 for receiving, and a row decoder 4 for designating a memory cell by decoding the address signal.
And column data 5, a sense refresh amplifier 6 that amplifies and reads a signal stored in a specified memory cell, a data-in buffer 7 and a data-out buffer 8 for data input / output, and a clock that generates a clock signal. And a generator 9.

The memory cell array 2 occupying a large area on the semiconductor chip is formed by arranging a plurality of memory cells for accumulating unit storage information in a matrix form, and FIG. 7 constitutes this memory cell array 2. An equivalent circuit for 4 bits of a memory cell is shown.

The memory cell shown in FIG. 7 has one MO per bit.
It shows a so-called 1-transistor 1-capacitor type memory cell that is composed of an S-transistor T and one capacitive element C connected to the S-transistor T. Since this type of memory cell has a simple structure, the memory cell array is integrated. It is easy to improve the performance and is widely used for large capacity DRAM.

Here, WL in FIG. 7 is a word line, and BL is a bit line.

Further, the memory cell of DRAM can be divided into several types depending on the structure of the capacitor for storing information charges, and as an example thereof, there is a so-called stacked type memory cell described in Japanese Patent Publication No. 60-2784. 8th
The figure is a sectional view of this stacked cell.

In FIG. 8, 10 is a p-type semiconductor substrate, 11 is an element isolation region, 12a and 12b are n ⁺ diffusion layers for source and drain, 13 is a gate electrode, 14 is a lower electrode for a capacitor made of a conductive film, and 15 is A capacitor dielectric film, 16 is a capacitor upper electrode made of a conductive film, 17 is an insulating film, and 18 is a conductive film. The lower and upper parts extend to above the gate electrode 13 as a word line and the element isolation region 11. Electrodes 14, 16 and dielectric film 1 between them
Capacitor is composed of 5.

[Problems to be Solved by the Invention]

In the conventional DRAM, when the memory cell size is reduced due to higher integration, the capacitor area is also reduced accordingly, but the stable operation and reliability of the DRAM as a memory device need to be guaranteed. Even with high integration, the amount of charge that can be stored in a 1-bit memory cell must be maintained substantially constant.

Therefore, conventionally, a method such as thinning the dielectric film of the capacitor or thickening the lower electrode of the capacitor has been adopted, but the former causes deterioration of the reliability of the dielectric film, and the latter causes the lower part on the gate electrode 13. There is a problem that the step difference of the electrode 14 becomes large and the etching process of the lower electrode 14 becomes extremely difficult.

The present invention has been made to solve the above problems, and in a semiconductor memory device including a stacked capacitor cell or the like, even if the capacitor area is reduced due to high integration, pattern processing is not performed. An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the semiconductor memory device which can secure a sufficient capacitance of a capacitor without causing difficulty and even with a thick dielectric film that does not impair reliability.

[Means for solving the problem]

A first aspect of a method of manufacturing a semiconductor memory device according to the present invention comprises a step of forming an element isolation region on a first conductivity type semiconductor substrate so as to surround a predetermined region, and a gate insulating film interposed on the predetermined region. Forming a gate electrode by forming a second conductivity type first and second impurity regions on both sides of the gate electrode on the surface of the substrate in the predetermined region, and covering the surface of the gate electrode. A protective film for electrically insulating the substrate, a step of selectively forming an etching stopper from the first impurity region to the protective film, and the second impurity region on the substrate. Forming a first conductive film so as to be in contact with the substrate and extending over the etching stopper; forming an insulating film on the entire upper surface; and flattening the surface of the insulating film; Smell on the first conductive film By forming an opening in the insulating film, forming a second conductive film on the entire upper surface including the inside of the opening, and removing the second conductive film on the upper surface of the insulating film, A step of leaving the second conductive film substantially perpendicular to the substrate on the side surface of the opening, and a lower part of the signal charge storage capacitor having a protruding structure by removing the insulating film and by the first and second conductive films. Forming an electrode, covering an exposed surface of the lower electrode to form a dielectric film of the capacitor, and covering the dielectric film to form an upper electrode of the capacitor. I am trying.

A second aspect of the method for manufacturing a semiconductor memory device according to the present invention comprises a step of forming an element isolation region on a first conductivity type semiconductor substrate so as to surround a predetermined region, and a gate insulating film interposed on the predetermined region. Forming a gate electrode by forming a second conductivity type first and second impurity regions on both sides of the gate electrode on the surface of the substrate in the predetermined region, and covering the surface of the gate electrode. A protective film for electrically insulating the substrate, a step of selectively forming an etching stopper from the first impurity region to the protective film, and the second impurity region on the substrate. Forming a first conductive film so as to contact the insulating film and extend over the etching stopper; forming an insulating film on the entire upper surface; and forming an opening in the insulating film on the first conductive film. A step of forming A step of sequentially stacking a second conductive film and a surface flattening layer having the same etching rate as the entire upper surface including the inside of the opening, and the surface flattening layer and the second conductive film, Etching away until the entire upper surface is exposed, leaving the second conductive film substantially perpendicular to the substrate on the side surface of the opening; and removing the insulating film to remove the first and second insulating films. Forming a lower electrode of a signal charge storage capacitor having a protruding structure with a conductive film; covering an exposed surface of the lower electrode to form a dielectric film of the capacitor; and covering the dielectric film with the dielectric film. And a step of forming an upper electrode of the capacitor.

A semiconductor memory device according to the present invention includes an element isolation region formed on a first conductivity type semiconductor substrate so as to surround a predetermined region, and a gate electrode formed on the predetermined region with a gate insulating film interposed therebetween. A second conductive type impurity region formed on both sides of the gate electrode on the surface of the substrate in the predetermined region, a protective film for covering the surface of the gate electrode and electrically insulating the same, and a protective film on the protective film An etching stopper selectively formed on the substrate, and a lower electrode of a signal charge storage capacitor having a projecting structure and a structure extending on the etching stopper formed on the substrate in contact with the impurity region. A plurality of memory cells each including a dielectric film of the capacitor formed by covering an exposed surface of the lower electrode and an upper electrode of the capacitor formed by covering the dielectric film, It is characterized in that the upper end of each of the protruding structure of the memory cell is parallel to the surface of the semiconductor substrate.

[Action]

In the first aspect of the method for manufacturing a semiconductor memory device according to the present invention, an insulating film is formed on the first conductive film and the semiconductor substrate, the surface of the insulating film is flattened, and then the lower portion of the protruding structure is formed. Since the electrodes are formed, variations in the height of the protruding portion of the lower electrode are suppressed, and when forming a large number of capacitors, such as in a memory cell array, the capacitance of each capacitor can be made uniform, and the protection that covers the gate electrode can be achieved. By forming the etching stopper on the film, it is possible to prevent the protective film for covering the surface of the gate electrode and electrically insulating from being etched, and further, the lower electrode extends on the etching stopper. This prevents a gap from being formed between the etching stopper and the lower electrode, thereby preventing the protective film from being exposed through the gap and ensuring that the protective film is formed. Etching is the fact attained be prevented.

In the second aspect of the method for manufacturing a semiconductor memory device according to the present invention, the second conductive film and the surface flattening layer having the same etching rate as the second conductive film are sequentially stacked, and then the lower electrode having the protruding structure is formed. The variation in height of the protruding portion of the lower electrode can be suppressed, and the capacitance of each capacitor can be made uniform when forming a large number of capacitors such as in a memory cell array, and an etching stopper is formed on the protective film covering the gate electrode. By forming the film, it is possible to prevent the protective film for covering the surface of the gate electrode and electrically insulating from being etched, and by extending the lower electrode on the etching stopper, the etching stopper is formed. By preventing a gap from being formed between the lower electrode and the lower electrode, it is possible to prevent the protective film from being exposed through the gap and to ensure that the protective film is formed. Etching is the fact attained be prevented.

In the semiconductor memory device according to the present invention, since the upper end of each protruding structure of the memory cell is parallel to the surface of the semiconductor substrate, the capacities of a large number of capacitors in the memory cell array become uniform, and further, the surface of the protective film and the etching stopper. By extending the lower electrode on the stepped shape formed by the end portion, the surface area of the lower electrode increases and the capacitance of the capacitor increases.

〔Example〕

FIG. 1 shows one embodiment of the semiconductor memory device of the present invention and the method of manufacturing the same when applied to a DRAM having stacked type memory cells. Each step will be described below.

First, as shown in FIG. 1A, a field oxide film 20 as a thick element isolation region is formed in a predetermined region on the surface of a first conductivity type semiconductor substrate 19 by, for example, the LOCOS method, and then the substrate 19 is formed. Is thermally oxidized to form a gate insulating film 21 made of an oxide film on the surface of the substrate 19 in a predetermined region surrounded by the field oxide film 20 of the substrate 19 as shown in FIG. A conductive film 22 made of, for example, a phosphorus-doped polycrystalline silicon film or the like is formed on the 21 and the field oxide film 20 by the low pressure CVD method or the like, and an oxide film or the like is formed on the conductive film 22 by the low pressure CVD method or the like. Insulating film 2
3 are deposited.

Then, as shown in FIG. 1C, the conductive film 22 is formed by the usual photolithography method and dry etching method.
And a portion other than a predetermined portion of the insulating film 23 is removed, whereby the gate electrode 22a of the access transistor and the word line 2 are removed.
After the formation of 2b, the gate electrode 22a, the word line 22b, and the insulating films 23a, 23b above the gate electrode 22a are formed as shown in FIG.
Using as a mask, the second conductivity type impurity regions 24a and 24b having a relatively low concentration are formed on the surface of the substrate 19 by the ion implantation method.

Thereafter, as shown in FIG. 1 (e), an insulating film 25 made of an oxide film or the like is formed on the substrate 19 and on the insulating films 23a and 23b by the low pressure CVD method or the like, and as shown in FIG. like,
The insulating film 25 is selectively removed by the anisotropic etching method, and the insulating film 2 is formed only on the upper side of the gate electrode 22a and the word line 22b.
After the gate electrodes 22a composed of 3a, 23b and 25 and the insulating films 26a and 26b which are protective films for electrically insulating the surfaces of the word lines 22b are formed, as shown in FIG.
a, the word line 22b and the insulating films 26a, 26b on the upper side thereof are used as masks to form second conductivity type impurity regions 27a, 27b having a relatively high concentration and a large depth on the surface of the substrate 19 by ion implantation. A so-called LDD (Lightly Doped Drain) structure is formed. At this time, the source / drain structure of the access transistor T does not need to be LDD and may have another structure.

Next, as shown in FIG. 1 (h), an insulating film 28, such as a nitride film, which is an etching stopper, is deposited on the substrate 19 by a low pressure CVD method or the like, and then by a photolithography method and an etching method. Impurity amount to be connected to the lower electrode of the capacitor described later Insulating film 2 on the upper side of stomachs 24b and 27b
8 is selectively removed and exposed to the impurity regions 24b and 27b,
As shown in FIG. 7I, after the first conductive film 29 made of, for example, polycrystalline silicon is deposited on the substrate 19 and the insulating film 28 by the low pressure CVD method or the like, the first conductive film 29 is formed by the ion implantation method or the like. Arsenic, for example, is introduced into the first conductive film 29 to reduce the resistance, and the first conductive film 29 other than the portions extending over the impurity regions 24b and 27b and the insulating film 28 is formed by the photolithography method and the etching method. Are selectively removed.

Then, as shown in FIG. 1 (j), by the CVD method or the like,
For example, the insulating film 30 made of an oxide film and the insulating film 28 and the first
Is deposited on the conductive film 29, the resist 30 'having the same etching rate as that of the insulating film 30 is applied to the insulating film 30 for flattening, and the insulating film 30 is flattened by etching back. As shown in the figure (k), the impurity region 24 of the insulating film 30
An opening 31 having a quadrangular cross section is formed above b and 27b.

Then, as shown in FIG. 1 (l), a second conductive film 32 made of, for example, polycrystalline silicon is formed by a low pressure CVD method or the like.
Is deposited on the entire surface, and then the second conductive film 32 on the insulating film 30 is anisotropically etched as shown in FIG.
Are selectively removed, so that only the side of the opening 31
Of the first conductive film 29, 3 and the insulating film 30 is removed by, for example, a wet etching method.
2, the capacitor lower electrode 33 is formed, and, for example, arsenic is introduced into the second conductive film 32 of the lower electrode 33 by an ion implantation method or the like to reduce the resistance.

At this time, by removing the insulating film 30, the substrate is formed on the lower electrode 33.
A rectangular tube-shaped protruding portion 33 ′ that is substantially perpendicular to 19 is formed.

Next, as shown in FIG. 1 (n), after a nitride film is formed on the entire surface by a low pressure CVD method or the like, a heat treatment is performed in an oxygen atmosphere to oxidize a part of the nitride film to form a capacitor dielectric film.
34 is formed, and the capacitor upper electrode 35 made of a conductive film such as polycrystalline silicon is deposited on the entire surface by the low pressure CVD method or the like to form the capacitor C.

Then, as shown in FIG. 1 (o), by the CVD method,
For example, an insulating film 36 for interlayer insulation made of an oxide film or the like is deposited on the entire surface, and the insulating film 36 in a portion connecting a bit line described later and the impurity regions 24a and 27a of the access transistor T is formed by photolithography and etching. Then, the tungsten film 37 is selectively removed by the CVD method to form the opening, and then the tungsten film 37 is selectively formed only in the opening formed in the insulating film 36 by the CVD method so that the opening is almost filled with the tungsten film 37. After that, a conductive film made of, for example, a tungsten silicide film is deposited on the entire surface by a sputtering method, and the conductive film is patterned into a predetermined shape by a photolithography method and an etching method.
This bit line is formed through the tungsten film 37.
38 is connected to impurity regions 24a and 27a of access transistor T.

By the way, FIG. 2 is a diagram showing a planar layout of a finally obtained stacked type memory cell of DRAM. A sectional view taken along line XX ′ in FIG. 2 is shown in FIG. 1 ((o)). Here, the fine cross-hatched portion in Fig. 2 is a rectangular cylindrical protrusion 33 '.

Therefore, since the protruding portion 33 'is formed on the lower electrode 33 of the capacitor C, the inner and outer side surfaces of the protruding portion 33' of the lower electrode 33 can be used as the capacitor C.
By increasing the height of 3 ', the capacitor area can be easily increased, and a sufficient capacitor capacity can be secured even when the memory cell size is reduced.

Further, by flattening the surface of the insulating film 30,
It is possible to suppress the variation in height of the protruding portion 33 'of the lower electrode 33, and it is possible to make the capacitor capacitance uniform when forming a large number of memory cells.

In addition, as shown in FIG. 1 (k), the insulating film is not
Since the plane area of the opening 31 formed in the opening 30 is small, a sufficient margin can be provided when the opening 31 is aligned with the underlying first conductive film 29, and the opening 31 can be easily formed. .

Further, since the protruding portion 33 'is exposed when the lower electrode 33 of the capacitor C is formed, it is possible to easily introduce impurities into the protruding portion 33' by the ion implantation method in order to reduce the resistance. it can.

Further, if the thickness of the protruding portion 33 'is reduced and the inner diameter of the square cylinder is increased, the capacitance of the capacitor can be increased.

In addition, in FIG. 1 (m), the insulating film 28 is the insulating film 26a,
Since it exists on 26b, it is possible to prevent the insulating films 26a and 26b from being etched when the insulating film 30 is removed.
The electrical connection between the first conductive film 29 and the gate electrode 22a or the word line 22b can be prevented, the reliability of the capacitor C can be improved, and the first conductive film 29 can be the insulating film 28.
By extending upwards, a gap is prevented from being formed between the insulating film 28 and the first conductive film 29, so that the insulating films 26a and 26b are prevented from being exposed through the gap and the insulating film is prevented. 26a, 26b
Can be more reliably prevented from being etched.

Further, since the first conductive film 29 is formed on the stepped shape formed by the surfaces of the insulating films 26a and 26b and the insulating film 28, the surface area of the first conductive film 29 can be increased, The capacitance of the capacitor C increases accordingly.

Next, FIG. 3 is a sectional view of another embodiment, which differs from FIG. 1 in that after the second conductive film 32 is deposited on the entire surface as shown in FIG. The second conductive film 32 other than the side wall of the opening 31 is removed by the lithography method and the etching method, and the first conductive film 29 and the remaining second conductive film 32 form a capacitor C having a protrusion 39 '. This is the same as the case of FIG. 1 even if the protrusion 39 ′ is formed by removing the second conductive film 32 by the photolithography method and the etching method as described above. The effect of is obtained.

At this time, a small fin-like portion remains on the upper portion of the projecting portion 39 'in the process, but there is no particular problem in practical use.

Further, FIG. 4 is a sectional view in the middle of the process of still another embodiment, which differs from FIG. 1 in FIGS. 1 (a) to (i).
After the process shown in Fig. 4, as shown in Fig. 4 (a), CV
An insulating film 40 made of, for example, an oxide film is formed on the entire surface by the D method or the like, the insulating film 40 is heat-treated to soften the surface by heat, and as shown in FIG. That is, the surface is flattened and then the steps shown in FIGS. 1 (k) to (o) are performed.

Furthermore, FIG. 5 is a cross-sectional view of another embodiment in the middle of the process, and the difference from FIG. 1 is that of FIG.
After the step shown in (i), as shown in FIG. 5 (a), an insulating film 4 made of, for example, an oxide film is formed by a CVD method or the like.
1 is formed on the entire surface, an opening 42 having a quadrangular cross section is formed above the impurity regions 24b and 27b of the insulating film 41, and the first conductive film 29 is exposed in the opening 42. So that the depressurized CV
A second conductive film 43 made of polycrystalline silicon or the like is deposited in the insulating film 41 and the opening 42 by the D method or the like.
A resist 44 having the same etching rate as that of 43 is applied as a surface flattening layer on 43, and anisotropic or isotropic etching is performed until the entire upper surface of the insulating film 41 is exposed. After removing the conductive film 43, the remaining resist 44 is removed by a resist stripping solution, and as shown in FIG. 6C, a square tube shape is formed only on the sidewall of the opening 42 and the exposed first conductive film 29. The second conductive film 43 is left and the insulating film 41 is removed to form a capacitor lower electrode 45 having a rectangular tubular projecting portion 45 ′ composed of the first and second conductive films 29 and 43.
Thereafter, as shown in FIGS. 3D and 3E, the capacitor dielectric film 46 and the capacitor upper electrode 47 are deposited by the same process as the process shown in FIGS. ′ Is formed, and further, the insulating film 48 for the interlayer insulating film, the tungsten film 49, and the bit line 50 are formed.

In each of the above embodiments, the tungsten films 37 and 49 were formed by the selective CVD method, but the present invention is not limited to this.
Polycrystalline silicon film, metal silicide film, metal film, TiN film,
Alternatively, it goes without saying that a composite film in which these films are alternately stacked may be formed.

Further, although the tungsten silicide film deposited by the sputtering method is formed as the conductive film for the bit lines 38 and 50, other conductive films may be used, such as a polycrystalline silicon film, a metal silicide film, a metal film, a TiN film, Alternatively, it may be a composite membrane in which these membranes are alternately stacked.

Furthermore, in each of the above embodiments, the case where the bit films 38 and 50 are connected to the impurity regions 24a and 27a of the access transistor T via the tungsten films 37 and 49 has been described.
It goes without saying that the bit lines 38, 50 may be directly connected to the impurity regions 24a, 27a.

In each of the above embodiments, the lower electrode 3 of the capacitor C is
The shape of the protruding portions 33 ', 39', 45 'of the 3, 39, 45 is shown as a square tube shape, but the shape is not limited to this shape and may be a cylindrical shape or a cross shape.

Furthermore, in each of the above-described embodiments, the LOCOS method of forming a thick oxide film is used as the method of forming the element isolation region 20, but other isolation methods may be used, and the same applies to the field shield isolation method later. Can be carried out.

〔The invention's effect〕

As described above, according to the method of manufacturing the semiconductor memory device of claim 1, the insulating film is formed on the first conductive film and the semiconductor substrate, the surface of the insulating film is flattened, and then the protruding structure is formed. And the method of manufacturing a semiconductor memory device according to claim 2, the second conductive film and the surface flattening layer having the same etching rate as that of the second conductive film are formed, and then the projecting structure is formed. Since the lower electrode is formed, sufficient capacitance of the capacitor can be ensured even when the area of the element formation region is reduced due to the integration of the semiconductor memory device. It is possible to suppress variations in the height of the protruding portion, and when forming a large number of capacitors such as in a memory cell array, it is possible to make the capacitance of each capacitor uniform, which is advantageous in the manufacture of DRAM and the like. is there.

Further, according to the semiconductor memory device of the third aspect, since the upper ends of the protruding structures of the memory cells are parallel to the surface of the semiconductor substrate, there is an effect that the capacities of a large number of capacitors in the memory cell array become uniform.

[Brief description of drawings]

FIG. 1 is a sectional view of each step of an embodiment of the method of manufacturing a semiconductor memory device of the present invention, FIG. 2 is a plan view of the semiconductor memory device obtained by each step of FIG. 1, and FIG. 4 is a sectional view of a semiconductor memory device obtained by each step of the embodiment, FIG. 4 and FIG. 5 are sectional views of the steps of other different embodiments, and FIG. 6 is a block diagram of a general DRAM. 7 is a connection diagram of a part of FIG. 6, and FIG. 8 is a sectional view of a part of FIG. 7. In the figure, 19 is a semiconductor substrate, 20 is a field insulating film,
21 is a gate insulating film, 22a is a gate electrode, 24a, 24b, 27a, 27b
Is an impurity region, 33, 39, 45 are lower electrodes, 34, 46 are dielectric films, 3
Reference numerals 5 and 47 are upper electrodes, and C and C ′ are capacitors. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

(57) [Claims] 1. A step of forming an element isolation region on a first conductivity type semiconductor substrate so as to surround a predetermined region, a step of forming a gate electrode on the predetermined region via a gate insulating film, and the predetermined region. Forming a second conductivity type first and second impurity regions on both sides of the gate electrode on the substrate surface, and forming a protective film for covering the surface of the gate electrode and electrically insulating the same. And a step of selectively forming an etching stopper from above the first impurity region to above the protective film, and in contact with the second impurity region on the substrate and extending above the etching stopper. Forming a first conductive film, forming an insulating film on the entire upper surface, planarizing the surface of the insulating film, and opening the insulating film on the first conductive film. A step of forming Forming a second conductive film on the entire upper surface including the inside of the opening; and removing the second conductive film on the upper surface of the insulating film so that the side surface of the opening is substantially perpendicular to the substrate. A step of leaving the second conductive film, a step of removing the insulating film and forming a lower electrode of a signal charge storage capacitor having a protruding structure by the first and second conductive films; A method of manufacturing a semiconductor memory device, comprising: a step of covering an exposed surface to form a dielectric film of the capacitor; and a step of covering the dielectric film to form an upper electrode of the capacitor. 2. A step of forming an element isolation region on a first conductivity type semiconductor substrate so as to surround a predetermined region, a step of forming a gate electrode on the predetermined region via a gate insulating film, and the predetermined region. Forming a second conductivity type first and second impurity regions on both sides of the gate electrode on the substrate surface, and forming a protective film for covering the surface of the gate electrode and electrically insulating the same. And a step of selectively forming an etching stopper from above the first impurity region to above the protective film, and in contact with the second impurity region on the substrate and extending above the etching stopper. Forming a first conductive film, forming an insulating film on the entire upper surface, forming an opening in the insulating film on the first conductive film, and The second conductive film on the upper surface And a step of sequentially laminating a surface flattening layer having the same etching rate as this, and removing the surface flattening layer and the second conductive film by etching until the entire upper surface of the insulating film is exposed, A step of leaving the second conductive film substantially perpendicular to the substrate on the side surface of the opening; and a step of removing the insulating film and forming a signal charge storage capacitor having a protruding structure by the first and second conductive films. Forming a lower electrode; covering the exposed surface of the lower electrode to form a dielectric film of the capacitor; and covering the dielectric film to form an upper electrode of the capacitor. A method for manufacturing a semiconductor memory device having a feature. 3. An element isolation region formed on a first conductivity type semiconductor substrate so as to surround a predetermined region, a gate electrode formed on the predetermined region via a gate insulating film, and a predetermined region of the predetermined region. A second conductivity type impurity region formed on both sides of the gate electrode on the surface of the substrate; a protective film for covering the surface of the gate electrode to electrically insulate; and a protective film selectively on the protective film. A lower electrode of a signal charge storage capacitor having a formed etching stopper, a projecting structure formed on the substrate in contact with the impurity region, and a structure extending on the etching stopper; and the lower electrode. A plurality of memory cells each including: a dielectric film of the capacitor formed by covering the exposed surface of the capacitor; and an upper electrode of the capacitor formed by covering the dielectric film. The semiconductor memory device, wherein the upper end of each said projecting structures is parallel to the surface of the semiconductor substrate.