JPH09186302A - Capacitor of semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a good Cmin/Cmax ratio in the lower electrode of a capacitor and also to make it possible to prevent impurities from being out-diffused from the lower electrode of the capacitor by a method wherein a second conductive layer is formed as an amorphous silicon film containing the second concentration impurities higher than the first concentration impurities of a first conductive layer. SOLUTION: An amorphous silicon film containing first concentration impurities is deposited on a semiconductor substrate 10 to form a first conductive layer 14. An amorphous silicon film containing second concentration impurities higher than the first concentration impurities is deposited on the layer 14 to form a second conductive layer 16. Then, a photoresist is applied on the layer 16 and the layers 16 and 14 are etched in order to form a lower electrode pattern constituted of first and second conductive layer patterns 14a and 16a. Then, an HSG silicon layer 22 is formed on the surface of the lower electrode pattern applying a selective hemispherical grained silicon layer (HSG) process and the formation of a lower electrode with the extended surface area is completed. After that, a dielectric film and an upper electrode are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor memory device and a method of manufacturing the same, and more particularly to a selective HS.
The present invention relates to a capacitor for a semiconductor memory device having a cylindrical storage electrode having a G (Hemispherical Grained Silicon layer) formed therein and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor memory device such as a DRAM (Dy
The area occupied by a unit cell composed of one transistor and one cell capacitor has been gradually reduced with the increase in the integration degree of the Namic Random Access Memory. A decrease in cell capacitance due to a decrease in memory cell area is a major factor that hinders improvement in the integration degree of DRAM. The reduction of the cell capacitance not only reduces the read capability of the memory cell and increases the soft error rate, but also makes it difficult to operate the device at low voltage, reduces the refresh characteristic, and increases the power consumption. .
Therefore, in order to increase the integration of the semiconductor memory device, it is necessary to solve the problem due to the reduction of the cell capacitance.

As a method of increasing the cell capacitance, there is a method of forming a dielectric film with a substance having a high dielectric constant or a method of forming a thin dielectric film. However, a dielectric film, which is a material having a high dielectric constant, generally has a large leakage current, which causes a breakdown voltage (breakdown voltage).
There is a problem that voltage) is low. On the other hand, the method of forming a thin dielectric film has a problem that the leakage current is increased and the reliability of the semiconductor device is reduced.

In view of these problems, a method of increasing the surface area of the capacitor electrode and increasing the capacitance has been proposed. As a typical example of this, there is one in which an HSG silicon layer having a hemispherical grain or the like is selectively formed on the surface of the lower electrode. According to this method, the surface area of the lower electrode can be easily increased and the capacitance can be increased.

1 to 3 are cross-sectional views illustrating a conventional method for selectively forming an HSG silicon layer only on a lower electrode portion of a capacitor used in a semiconductor memory device.

In this method, first, as shown in FIG. 1, after forming an insulating film, for example, an oxide film 3 on the semiconductor substrate 1, the contact film is patterned to expose a predetermined region of the semiconductor substrate 1. form h1.

Then, as shown in FIG. 2, amorphous silicon is vapor-deposited on the resultant product to form a contact hole h1.
To form a conductive layer 5 that fills.

Next, as shown in FIG. 3, the conductive layer 5 is patterned to form a lower electrode 7 covering the contact hole h1, and then the HSG silicon layer 9 is formed on the surface of the lower electrode 7.
To form This lower electrode 7 is in an amorphous state. Therefore, it is necessary to increase the concentration of impurities in the lower electrode in order to reduce the resistance of the lower electrode 7.

However, when the concentration of impurities in the lower electrode is increased, a phenomenon occurs in which impurities contained in the lower electrode are out-diffusion into a semiconductor substrate in contact with the lower electrode. . Due to this phenomenon, the concentration of impurities in the semiconductor substrate, that is, the source region or the drain region of the transistor is changed, which causes a problem that the characteristics of the transistor are degraded.

In this way, the source /
The impurity concentration of the drain region is directly influenced by the impurity concentration of the lower electrode. Therefore, the lower the impurity concentration of the lower electrode, the more
The amount of change in the concentration of impurities in the drain region is reduced.

However, if the impurity concentration of the lower electrode is reduced, a general phenomenon in the MOS capacitor structure,
That is, the capacitance changes according to the magnitude of the voltage applied to the electrodes of the capacitor. Particularly, in the capacitor structure in which the HSG film is formed on the surface of the lower electrode, the amount of change in this capacitance is further increased as compared with the general capacitor structure having no HSG film. This is because the depletion layers formed in the hemispherical grains forming the HSG film overlap each other to increase the effective width of the depletion layer. When such a phenomenon occurs, the capacitance changes due to the voltage applied to the electrodes of the capacitor,
Within a certain voltage range, the minimum capacitance (Cm
in) and maximum capacitance (Cmax) will be present.

FIG. 4 is a graph showing changes in Cmin / Cmax due to changes in the doping concentration of impurities, in the case where HSG is formed on the lower electrode of the capacitor and in the case where it is not formed.

The results shown in FIG. 4 are an example of the case where phosphorus (P) is used as an impurity for doping the lower electrode in the actual forming process of the lower electrode. This graph shows that when PH ₃ is used as the source gas of phosphorus and the inflow flow rate of PH ₃ is 5, 7, 15 [sccm], HSG is not formed on the surface of the lower electrode (■), and HSG It is a comparison of Cmin / Cmax in the case of forming (). From this graph, when HSG is formed on the surface of the lower electrode, Cmin increases as the flow rate of PH ₃ decreases.
/ Cmax drops sharply, but H on the surface of the lower electrode
It is understood that when SG is not formed, the phenomenon that Cmin / Cmax sharply decreases does not occur even if the flow rate of PH ₃ is changed.

To form HSGs on the surface of the lower electrode,
As described above, it is necessary to form a lower electrode having a new structure in which Cmin / Cmax does not decrease.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to obtain a good Cmi.
An object of the present invention is to provide a capacitor for a semiconductor memory device and a method for manufacturing the same in which an n / Cmax ratio is obtained and impurities are prevented from diffusing outward from a lower electrode of the capacitor.

[0016]

In order to achieve the above-mentioned object, a capacitor of a semiconductor memory device according to the present invention comprises a first capacitor.
In a capacitor of a semiconductor memory device having a structure in which a conductive layer and a second conductive layer are sequentially stacked, and including a lower electrode on which HSGs are selectively formed, the first conductive layer may have a first concentration of impurities. The second conductive layer is formed of an amorphous silicon film containing an impurity having a second concentration higher than the first concentration.

The impurities are phosphorus (P) or arsenic (As).
It is preferred that

The capacitor of the semiconductor memory device according to the present invention has a structure in which a first conductive layer and a second conductive layer are sequentially stacked, and includes a lower electrode having HSGs selectively formed on its surface. In the capacitor of the memory device, the first conductive layer is a polycrystalline silicon film containing an impurity of a first concentration, and the second conductive layer is an amorphous silicon film containing an impurity of a second concentration higher than the first concentration. Is characterized in that

Preferably, a crystallization blocking film formed between the first conductive layer and the second conductive layer is further included. Further, the crystallization blocking film is preferably an oxide film.

In order to achieve the above object, a method of manufacturing a capacitor of a semiconductor memory device according to the present invention comprises a contact hole for partially etching an insulating layer formed on a semiconductor substrate to partially expose the semiconductor substrate. Forming a first conductive layer and a second conductive layer on the resultant product, and patterning the first conductive layer and the second conductive layer to form a first conductive layer pattern and a second conductive layer. The method is characterized by including a step of forming a lower electrode pattern in which conductive layer patterns are sequentially stacked, and a step of forming an HSG silicon layer on the surface of the lower electrode pattern by a selective HSG forming step.

The first conductive layer is formed of an amorphous silicon film containing a first concentration of impurities, and the second conductive layer is formed of the first conductive layer.
It is preferable to form the amorphous silicon film containing the second concentration of impurities higher than the concentration.

The first conductive layer is formed of a polycrystalline silicon film containing a first concentration of impurities, and the second conductive layer is formed of amorphous silicon containing a second concentration of impurities higher than the first concentration. It is preferably formed.

Also, in the method of manufacturing a capacitor of a semiconductor memory device according to the present invention, a step of partially etching an insulating layer formed on a semiconductor substrate to form a contact hole that partially exposes the semiconductor substrate. And a step of sequentially forming a first conductive layer, a crystallization blocking film, and a second conductive layer on the resultant product, and patterning the second conductive layer, the crystallization blocking film, and the first conductive layer to form a first conductive layer. Forming a lower electrode pattern in which a layer pattern, a crystallization barrier film pattern, and a second conductive layer pattern are sequentially stacked; and wet etching the crystallization barrier film exposed on a sidewall of the lower electrode pattern to a predetermined width. To form an undercut region, and selective H
And a step of forming an HSG silicon layer on the surface of the second conductive layer and the undercut region by an SG forming step.

The first conductive layer is formed of a polycrystalline silicon film containing impurities at a first concentration, the crystallization blocking film is formed of an oxide film, and the second conductive layer is formed at a second concentration higher than the first concentration.
It is preferably formed of an amorphous silicon film containing a high concentration of impurities.

The oxide film is formed by CVD (Chemical Vap
or Deposition) or thermal oxidation.

The step of forming the first conductive layer includes
It is preferable to include a step of stacking an amorphous silicon film containing impurities of a first concentration and a step of crystallizing the amorphous silicon film by heat treatment.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, in a capacitor including an HSG silicon layer, in order to prevent impurities of the capacitor from being diffused outward and to obtain stable Cmin / Cmax, a silicon is used in forming a lower electrode. By forming a silicon layer with a low impurity concentration in the portion that contacts the substrate, the phenomenon of impurities re-diffusing in the subsequent thermal process is suppressed, deterioration of element isolation characteristics and transistor characteristics is prevented, and the silicon layer above the silicon layer is prevented. A silicon layer having a high impurity concentration is formed on the substrate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0029]

First Embodiment FIGS. 5 to 7 relate to a first embodiment of the present invention and explain a method of manufacturing a capacitor of a semiconductor memory device by selectively forming an HSG silicon layer only on a lower electrode. It is sectional drawing for doing.

In this method, first, as shown in FIG. 5, an insulating layer for insulating the lower structure is formed on the semiconductor substrate 10 on which the lower structure such as a transistor is formed. Then, a photoresist pattern (not shown) is formed on the insulating layer by a photo-etching process, and the insulating layer is etched using the photoresist pattern as an etching mask to form an insulating layer pattern 12.
Contact hole h for exposing a part of the semiconductor substrate 10
Form 2

Next, as shown in FIG. 6, after the photoresist pattern is removed, impurities in the lower electrode are removed from the semiconductor substrate 10, more specifically, the source / transistor of the transistor.
In order to reduce the amount of diffusion into an active region such as a drain region, an amorphous silicon film containing impurities of a first concentration is deposited on the resultant product in which the contact hole h2 is formed to form the first conductive layer 14. Form. Then, an amorphous silicon film containing an impurity having a second concentration higher than the first concentration is deposited on the first conductive layer 14 to form the second conductive layer 16. As the impurities, phosphorus (P) or arsenic (As) is suitable.

Then, as shown in FIG. 7, the second conductive layer 1
A photoresist pattern (not shown) for forming a lower electrode of the capacitor is formed after applying a photoresist on the second conductive layer 16 and the first conductive layer 14 using the photoresist pattern as an etching mask. By sequentially etching the first conductive layer pattern 14a and the second conductive layer pattern 1
A lower electrode pattern composed of 6a is formed.

Then, a selective HSG process is applied to the first
The HSG silicon layer 22 is formed on the surface of the lower electrode pattern including the conductive layer pattern 14a and the second conductive layer pattern 16a.
To complete the formation of the lower electrode having the expanded surface area. Then, a dielectric film and an upper electrode are formed, and a general CMOS forming process is continued.

[0034]

Second Embodiment FIGS. 8 to 10 are sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device using a selective HSG process according to a second embodiment of the present invention.

In this method, first, as shown in FIG. 8, an insulating layer for insulating the lower structure is formed on the semiconductor substrate 100 on which the lower structure such as a transistor is formed. Thereafter, a photolithography process using a photoresist pattern (not shown) is performed on the insulating layer to etch the insulating layer to form an insulating layer pattern 112, thereby exposing a part of the semiconductor substrate 100. form h3.

Next, as shown in FIG. 9, after removing the photoresist pattern used in the etching process, a conductive layer for forming a lower electrode is formed on the resultant product in which the contact hole h3 is formed, for example. A first conductive layer 114 made of a polycrystalline silicon film containing a first concentration of impurities and a second conductive layer 116 made of an amorphous silicon film containing a second concentration of impurities higher than the first concentration are sequentially deposited.

Here, after the first conductive layer 114 is formed of the amorphous silicon film containing the impurity of the first concentration instead of forming the polycrystalline silicon film as described above, heat treatment, plasma treatment, electron beam or By crystallization of the amorphous silicon film by irradiation with a laser beam or the like, the subsequent HS
It may be possible to prevent the HSG silicon layer from being formed in the portion of the first conductive layer 114 in the step of forming the G silicon layer.

Then, as shown in FIG. 10, the second conductive layer 116 and the first conductive layer 114 are sequentially etched by a photo-etching process using a photoresist pattern (not shown) to form the first conductive layer pattern 114a. And a lower electrode pattern including the second conductive layer pattern 116a is formed on the second conductive layer 11
6 is formed.

Then, a selective HSG forming step is performed on the lower electrode pattern. At this time, the second conductive layer pattern 116a is used as an underlayer for forming the HSG silicon layer, and the HSG silicon layer 122 is formed only on the surface of the second conductive layer pattern 116a. Complete the formation of. Here, the first
Since the conductive layer pattern 114a is made of the polycrystalline silicon film containing the low concentration impurity as described above, the impurity is prevented from being diffused from the lower electrode to the semiconductor substrate in the subsequent thermal process.

[0040]

[Third Embodiment] FIGS. 11 to 15 are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device using a selective HSG process according to a third embodiment of the present invention.

In this method, first, as shown in FIG. 11, an insulating layer pattern for insulating a lower structure is formed on a semiconductor substrate 200 by the method of the second embodiment described with reference to FIG. 212 is formed.

Then, as a conductive layer for forming a lower electrode on the resultant structure, a first conductive layer 214 made of, for example, a polycrystalline silicon film containing impurities of a first concentration, a crystallization blocking film 215, and a first conductive layer 214 are formed. A second conductive layer 216 made of an amorphous silicon film containing a second concentration higher than the concentration is sequentially deposited.

Here, the first conductive layer 214 is not formed of a polycrystalline silicon film as in the second embodiment, but is formed of an amorphous silicon film containing a first concentration of impurities, and is then subjected to heat treatment and plasma treatment. Alternatively, it may be crystallized by irradiation with an electron beam or a laser beam. In addition, the crystallization blocking film 215
For example, an oxide film formed by CVD (Chemical Vapor Deposition) may be used, or an oxide film formed by thermal oxidation with a thickness of 100 Å or less may be used.

Next, as shown in FIG. 12, a photoresist pattern (not shown) is formed on the second conductive layer 216, and the second conductive layer 21 is formed by a photo-etching process using the photoresist pattern.
6, a crystallization blocking film 215 and a first conductive layer 214 are sequentially etched, and a first conductive layer pattern 214a, a crystallization blocking film pattern (not shown) and a second conductive layer pattern 216a are sequentially stacked to form a lower electrode pattern. To form. After that, the undercut region A is formed under the edge of the second conductive layer pattern 216a by removing the crystallization barrier film pattern exposed on the sidewall of the lower electrode pattern by wet etching by a predetermined width. At the same time, a second crystallization blocking film pattern 215a is formed.

Next, as shown in FIG. 13, a selective HSG forming step is performed on the resultant product. At this time, the second conductive layer pattern 216a is used as an underlayer for forming the HSG silicon layer, and the HSG silicon layer 222 is formed only on the surface of the second conductive layer pattern 216a and the undercut region A. Here, the first conductive layer pattern 214a and the second conductive layer pattern 216a are connected to each other by the HSG silicon layer 222 formed in the undercut region A. Since the first conductive layer pattern 214a is formed of a polycrystalline silicon film containing low concentration impurities as in the second embodiment, impurities are prevented from being diffused from the lower electrode to the semiconductor substrate during the subsequent thermal process. .

Generally, in a conductive layer forming a lower electrode of a semiconductor memory device, a polycrystalline silicon film containing a low concentration impurity is used as a base film, and an amorphous silicon film containing a high concentration impurity is vapor-deposited thereon. In this case, a phenomenon in which the lower polycrystalline silicon film promotes crystallization of the amorphous silicon film deposited on the upper surface may occur. However, according to the third embodiment, since the crystallization blocking film is formed between the first conductive layer made of the polycrystalline silicon film and the second conductive layer made of the amorphous silicon film, the non-conductive layer of the second conductive layer is not formed. Amorphous silicon film is first
It is possible to prevent the conductive layer from being crystallized by polycrystalline silicon.

<Evaluation Example> FIGS. 14 and 15 show that the characteristics of the device are improved by making the concentrations of the impurities in the lower layer and the upper layer constituting the lower electrode low and high, respectively, based on this example. It is a figure which shows the result which confirmed that. FIG. 14 is a graph comparing the Cmin / Cmax ratios of the conventional lower electrode and the lower electrode of the present invention. FIG. 15 is a graph showing a device isolation characteristic due to a difference in impurity concentration between a lower electrode according to the related art and a lower electrode according to the present invention, that is, a difference in breakdown voltage between adjacent active regions. is there.

In the above experiment, the test sample according to the present invention uses phosphorus as an impurity for doping the lower electrode to form a silicon layer in which the lower layer and the upper layer have different impurity concentrations. As P
Formed using H ₃ .

Specifically, first, the first inflow rate of PH ₃ is set to 3.5 [sccm], and the first silicon layer having a low impurity concentration in the lower electrode is set to about the total thickness of the lower electrode. Then, the second inflow rate of PH ₃ is increased to 10 [sccm] to form a second silicon layer having a high impurity concentration in the lower electrode, and the surface of the second silicon layer is formed. Then, an HSG layer, a dielectric film and an upper electrode were sequentially formed. Here, the second silicon layer is formed of an amorphous silicon layer. In the conventional test sample for comparison, the inflow flow rate of PH ₃ was fixed to 10 [sccm] to form the lower electrode of the capacitor with a single layer having a constant impurity concentration, and the surface of the lower electrode was formed. HSG layer,
A dielectric film and an upper electrode were sequentially formed.

As shown in FIGS. 14 and 15, Cmin / Cmax (□) according to the present invention is C according to the prior art.
Although it is about 5% lower than min / Cmax (○), the concentration of impurities in the lower layer and the upper layer constituting the lower electrode according to the present invention becomes low and high at the breakdown voltage in the element isolation region. In the case of the formation (□), the breakdown voltage was improved by about 15% or more as compared with the case of the conventional case (○). Such improvement of the breakdown voltage characteristic improves the reliability of the device.

From the results shown in FIGS. 14 and 15, when the step of forming HSGs on the lower electrode is used to increase the surface area of the capacitor of the semiconductor memory device, the lower and upper layers forming the lower electrode according to the present invention are used. It is confirmed that the deterioration of the characteristics of the device can be prevented by forming the impurity concentration of 1 to be the low concentration and the high concentration of the impurity.

The present invention is not limited to the above embodiments, but various modifications can be made within the scope of the technical idea of the present invention.

[0053]

According to the present invention, good Cmin / Cm
It is possible to obtain an ax ratio and prevent impurities from being diffused outward from the lower electrode of the capacitor.

[0054]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 4 is a graph showing changes in Cmin / Cmax due to changes in the doping concentration of impurities in the case where HSG is formed on the lower electrode of the capacitor and the case where HSG is not formed.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a capacitor of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating the method of manufacturing the capacitor of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating a method of manufacturing a capacitor of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 8 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a second exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a third exemplary embodiment of the present invention.

FIG. 12 is a sectional view illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a third exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the capacitor of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 14 is a graph comparing Cmin / Cmax ratios of a lower electrode according to the related art and a lower electrode according to the present invention.

FIG. 15 is a graph showing breakdown voltage distributions in an element isolation region depending on impurity concentrations in a lower electrode according to a conventional technique and a lower electrode according to the present invention.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shensein Jin, South Korea Gyeonggi-do, Gyeonggi-do, No. 1305, Sanmak Apartment, No. 1305, Fukdeok-gawa, Yongin-si, South Korea No. 453-16 (72) Inventor ▲ Kure ▼ Kansui 123-103 Ike-dong, Badal-gu, Suwon-si, Gyeonggi-do, Republic of Korea

Claims (12)

[Claims] 1. A first conductive layer and a second conductive layer are sequentially stacked, and HSG (Hemispherical Grained Si) is selectively formed on the surface.
In a capacitor of a semiconductor memory device including a lower electrode having a conductive layer, the first conductive layer is made of an amorphous silicon film containing impurities of a first concentration, and the second conductive layer is made of an amorphous silicon film having a concentration of less than the first concentration. A capacitor of a semiconductor memory device comprising an amorphous silicon film containing a high second concentration of impurities. 2. The capacitor of claim 1, wherein the impurity is phosphorus or arsenic. 3. A capacitor of a semiconductor memory device, comprising: a lower electrode having a first conductive layer and a second conductive layer stacked in order and having HSGs selectively formed on a surface thereof, wherein the first conductive layer has a first concentration. A capacitor of a semiconductor memory device, comprising a polycrystalline silicon film containing impurities, and the second conductive layer being an amorphous silicon film containing impurities having a second concentration higher than the first concentration. 4. The capacitor of claim 3, further comprising a crystallization blocking film formed between the first conductive layer and the second conductive layer. 5. The capacitor of claim 4, wherein the crystallization blocking layer is an oxide layer. 6. A step of partially etching an insulating layer formed on a semiconductor substrate to form a contact hole that partially exposes the semiconductor substrate, and a first conductive layer and a second layer on the resultant product. A step of sequentially forming a conductive layer; a step of patterning the first conductive layer and the second conductive layer to form a lower electrode pattern in which a first conductive layer pattern and a second conductive layer pattern are sequentially stacked; A step of forming an HSG silicon layer on the surface of the lower electrode pattern by an HSG forming step, and a method of manufacturing a capacitor of a semiconductor memory device. 7. The first conductive layer is formed of an amorphous silicon film containing impurities of a first concentration, and the second conductive layer is amorphous silicon containing impurities of a second concentration higher than the first concentration. The method for manufacturing a capacitor of a semiconductor memory device according to claim 6, wherein the method is used to form a film. 8. The first conductive layer is formed of a polycrystalline silicon film containing impurities of a first concentration, and the second conductive layer is an amorphous silicon film containing impurities of a second concentration higher than the first concentration. 7. The method for manufacturing a capacitor of a semiconductor memory device according to claim 6, wherein the capacitor is formed by. 9. A step of partially etching an insulating layer formed on a semiconductor substrate to form a contact hole that partially exposes the semiconductor substrate, and a first conductive layer and crystallization on the resultant product. A step of sequentially forming a barrier film and a second conductive layer, and patterning the second conductive layer, the crystallization barrier film, and the first conductive layer to form a first conductive layer pattern, a crystallization barrier film pattern, and a second conductive layer. A step of forming a lower electrode pattern in which patterns are sequentially stacked; a step of wet-etching the crystallization blocking film exposed on the sidewall of the lower electrode pattern by a predetermined width to form an undercut region; And a step of forming an HSG silicon layer on the surface of the second conductive layer and the undercut region by an HSG forming step. 10. The first conductive layer is formed of a polycrystalline silicon film containing impurities of a first concentration, the crystallization blocking film is formed of an oxide film, and the second conductive layer is higher than the first concentration. 10. The method of manufacturing a capacitor of a semiconductor memory device according to claim 9, wherein the amorphous silicon film includes impurities of a second concentration. 11. The method for manufacturing a capacitor of a semiconductor memory device according to claim 10, wherein the oxide film is formed by CVD or thermal oxidation. 12. The step of forming the first conductive layer includes a step of stacking an amorphous silicon film containing a first concentration of impurities, and a step of crystallizing the amorphous silicon film by heat treatment. 10. The method of manufacturing a capacitor of a semiconductor memory device according to claim 9, further comprising: