JP2875227B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a stacked capacitor device constituting a DRAM.
The present invention relates to a method for manufacturing a cell.

[0002] A DRAM has a structure in which a memory cell comprising one transistor and one capacitor cell is integrated. With the recent demand for higher integration of DRAM,
There is a need for smaller sized capacitor cells.

[0003] As a means for increasing the capacitance of a capacitor in a smaller space, a capacitor
Various methods have been considered for increasing the surface area of the cell. As a structure using this method, a stacked capacitor cell in which a capacitor cell is provided above a semiconductor substrate is currently used.

However, in order to cope with higher miniaturization in the future, it is necessary to devise a method of obtaining a sufficient capacitor capacity in a smaller area.

[0005]

[Prior art]

 (Conventional Example 1) FIG. 13 is a diagram showing Conventional Example 1.

This figure shows an example of a planar capacitor cell. In FIG. 13, reference numeral 301 denotes a Si substrate,
302 is a field oxide film, 303 is a source region, 30
4 is a drain region, 305 is a gate electrode, 306 is a poly-Si layer, 307 is a CVD / SiO ₂ film, and 308 is an Al wiring.

The Si substrate 301 has a field oxide film 30
2, each memory cell is partitioned. A MOS transistor having a memory cell capacity includes a source region 303 and a drain region 304 formed on the surface of a Si substrate 301.
And a gate electrode 305. As a material of the gate electrode 305, polySi, a metal, a metal silicide, or the like is used.

[0008] A capacitor cell for a memory cell has a poly-Si layer 306 and an Si substrate 301 as capacitor electrodes, and charges are stored in an inversion layer formed on the surface of the Si substrate 301.

[0009] With the increase in capacity of DRAM, miniaturization of elements constituting the DRAM has been advanced. As a result, the area of the capacitor cell has been reduced, and the capacitance of the capacitor has also been reduced.

The capacitance of the capacitor is determined by the S / S of the sense amplifier.
From the two viewpoints of the N ratio and the soft error resistance, it is difficult to reduce the value to a certain value or less, so that it has become difficult to cope with the planar capacitor cell.

Therefore, a stacked capacitor cell having a structure in which both electrodes of a capacitor are made of polysilicon and the whole is buried in an interlayer insulating film on a semiconductor substrate has been used. (Conventional Example 2) FIG. 14 is a diagram showing Conventional Example 2.

This figure shows an example of a stacked capacitor cell. In FIG. 14, reference numeral 401 denotes a Si substrate, 402 denotes a field oxide film, 403 denotes a source region,
404 is a drain region, 405 is a gate electrode, 406 is a CVD SiO ₂ film, 407 is a poly-Si layer constituting a storage node, 408 is a SiO ₂ film or _two layers of a Si ₃ N ₄ film and a SiO ₂ film or A capacitor insulating film having a three-layer structure, 409 is poly-Si constituting a cell plate
The layer 410 is a CVD-SiO constituting an interlayer insulating film.
_{The second} film 411 is an Al wiring.

The Si substrate 401 has a field oxide film 40
2, each memory cell is partitioned. The MOS transistor for a memory cell includes a source region 403, a drain region 404, and a gate electrode 405 formed on the surface of a Si substrate 401. As a material of the gate electrode 405, poly-Si, metal, or metal silicide is used.

A capacitor cell for a memory cell is composed of a poly-Si layer 407 constituting a storage node, SiO
_A CVD / SiO ₂ film which is an interlayer insulating film comprising a capacitor insulating film 408 having a two-layer or three-layer structure of a Si ₃ N ₄ film and a SiO ₂ film and a poly-Si layer 409 constituting a cell plate. Formed in 410.

[0015]

Even in the stacked capacitor cell shown as the conventional example 2, as the capacity of the DRAM increases and the element becomes finer, the capacity of the capacitor becomes insufficient.

Therefore, the conventional DRAM capacitor cell has a problem that the capacitance of the capacitor is not sufficient. An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device including a DRAM having a capacitor cell capable of obtaining a large capacitor capacity in a small area.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (1) a step of forming a field insulating film defining an element region on a semiconductor substrate; Forming a gate electrode on the surface of the semiconductor substrate in the element region via a gate insulating film;
Forming a source or drain region on the substrate surface on both sides of the gate electrode; and on the gate electrode, on the field insulating film, and on the source or drain region between the gate electrode and the field insulating film. Forming an insulating layer having a bottom surface of the opening, and a side surface extending substantially perpendicular to a main surface of the substrate surface from the gate electrode and the field insulating film as a side wall of the opening; Forming a conductive layer on the side wall and the insulating layer electrically connected to the source or drain region on the bottom of the opening, and selectively removing at least the conductive layer on the insulating layer; Forming a storage node made of the conductive layer, forming a capacitor insulating film on the surface of the storage node, and forming a counter electrode on the surface of the capacitor insulating film. Configured. (2) a step of forming a field insulating film defining an element region on the semiconductor substrate; a step of forming a gate electrode on the surface of the semiconductor substrate in the element region via a gate insulating film; and both sides of the gate electrode Forming a source or drain region on the surface of the substrate; and forming a bottom surface of an opening on the gate electrode, on the field insulating film, and on the source or drain region between the gate electrode and the field insulating film. Forming an insulating layer having a side surface extending substantially perpendicular to the main surface of the substrate surface as a side wall of the opening from the gate electrode and the field insulating film; Forming a conductive layer electrically connected to a source or drain region and forming the conductive layer on the side wall and the insulating layer; and at least selectively removing the conductive layer on the insulating layer to form the conductive layer. Or Forming the storage node, and removing the insulating layer of the storage node that contacts the storage node extending substantially perpendicular to the main surface of the substrate surface; and It is configured to include a step of forming a capacitor insulating film on the surface and a step of forming a counter electrode on the surface of the capacitor insulating film. (3) In the above item (1) or (2), after the gate electrode is formed, a step of forming a stopper film extending on the gate electrode, the field insulating film, and the source or drain region. Forming the insulating layer on the stopper film, etching the insulating layer using the stopper layer as a stopper, and forming the insulating layer on the gate electrode, the field insulating film, and the gate electrode and the field insulating film. Forming the opening having a side surface extending substantially perpendicularly to the main surface of the substrate surface from above the gate electrode and the field insulating film. It is configured as follows. (4) In the above items (1) to (3), after forming the conductive layer, filling the opening with a coating film, and then selectively removing the conductive layer on the insulating layer. Forming a storage node made of the conductive layer.

A stacked capacitor cell formed by the method of manufacturing a semiconductor integrated circuit device according to the present invention has a storage node which is in contact with a semiconductor substrate and accumulates electric charge, a capacitor insulating film, and a cell plate forming a counter electrode. Consisting of a laminate, the storage node has a box-like shape having an upright wall at its end face, and a capacitor is formed by providing a cell plate facing the entire bottom face and at least the inner face of the wall. It has been like that.

The cell plate may be provided to face only the inner surface of the storage node wall, or may be provided to face the inner and outer surfaces of the storage node wall. In the latter case, the capacitance of the capacitor can be further increased.

As described above, according to the stacked capacitor cell of the present invention, the storage node is formed in a box shape by providing the upright wall portion at the end face of the storage node, and the inner surface or the inner surface and the outer surface of the wall portion are formed by the capacitor. , The surface area of the capacitor is increased, and a larger capacitor capacity can be obtained in the same area as the conventional stacked capacitor cell.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

 (First Embodiment) FIG. 1 is a diagram showing a first embodiment.

In FIG. 1, reference numeral 101 denotes an Si substrate;
Is a field oxide film, 103 is a source region, 104 is a drain region, 105 is a gate electrode, 109 is a poly-Si layer constituting a storage node, 111 is an SiO ₂ film or a film of Si ₃ N ₄ and SiO ₂ films. A capacitor insulating film having a three-layer or three-layer structure; 112, a poly-Si layer forming a cell plate;
The SiO ₂ film 114 is an Al wiring.

The Si substrate 101 has a field oxide film 10
2, each memory cell is partitioned. The MOS transistor for a memory cell includes a source region 103, a drain region 104, and a gate electrode 105 formed on the surface of a Si substrate 101. As a material of the gate electrode 105, polySi, a metal, a metal silicide, or the like is used.

A capacitor cell for a memory cell includes a poly-Si layer 109 and a SiO layer constituting a storage node.
A CVD / SiO film comprising a capacitor insulating film 111 having a two-layer or three-layer structure of a _two- film or Si ₃ N ₄ film and a SiO ₂ film and a poly-Si layer 112 constituting a cell plate, and constituting an interlayer insulating film It is formed in the _two films 113.

The poly-Si layer 109 constituting the storage node has an upright wall at its end face, and the poly-Si layer 109 constituting the cell plate is opposed thereto.
Since the layer 112 is provided, the surface area of the capacitor can be increased, and a larger capacitor capacity can be obtained in the same area as the conventional stacked capacitor cell.

Next, a method of manufacturing the stacked capacitor cell of this embodiment will be described. 3 to 8 are views showing the respective manufacturing steps leading to FIG. A method of manufacturing the stacked capacitor cell according to the present embodiment will be described with reference to FIGS. Step 1: See FIG. 3 A field oxide film 102 as an element isolation region is formed on the surface of a Si substrate 101 by a LOCOS method, and a source region 103 and a drain region 104 are formed by diffusion or ion implantation.

Next, after forming a gate oxide film, poly-Si, high melting point metal, silicide of high melting point metal, polycide of high melting point metal and the like are deposited on the gate oxide film and patterned to form a gate electrode 105. I do.

Then, after depositing a SiO ₂ film on the entire surface by the CVD method, the gate electrode 10 is anisotropically etched.
Forming an interlayer insulating film around 5 and other wiring
- covered with a SiO ₂ film 106. Step 2: See FIG. 4 After a resist is applied evenly over the entire surface of the Si substrate 101, only the resist 107 at a portion where a storage node is to be formed is left using a mask.

The height of the storage node wall is determined by the thickness of the resist 107. Step 3: See FIG. 5 Spin-on-glass (SOG) 108 by a coating method over the entire surface
And flatten the entire surface.

Next, the resist 10 is etched back.
After the resist 107 is exposed by etching the spin-on-glass (SOG) on the resist 7, the resist 107 is removed with persulfuric acid. Step 4: See FIG. 6 In order to make contact between the storage node and the drain region 104, the surface of the Si substrate 101 above the drain region 104 is exposed, and then the poly-Si layer 109 serving as the storage node is removed. It is deposited by the phase growth method.

Thereafter, SOG or resist 11 is applied to the entire surface.
0 is applied. Step 5: See FIG. 7 After the SOG or the resist 110 (FIG. 6) is etched back to expose the poly-Si layer on the SOG 108, the poly-Si layer in this portion is selectively etched and removed. Step 6: See FIG. 8 When the outer and inner surfaces of the storage node poly-Si layer 109 are exposed, a capacitor insulating film 111 is formed on the surface of the poly-Si layer 109. Capacitor insulating film 1
Reference numeral 11 denotes a thermal SiO ₂ film or a Si ₃ N ₄ film and a SiO ₂ film.
A two-layer film or a three-layer film with a film is used.

After forming the capacitor insulating film 111, a poly-Si layer 112 for a cell plate is deposited, and the cell plate is patterned. Then, SOG108
(FIG. 7) is removed. When the SOG 108 is wet-etched, if the concentration of phosphorus in the SOG 108 is increased in advance, the CVD / SiO ₂ film 10 serving as an interlayer insulating film is formed.
6 can be increased. Therefore,
Even if the SOG 108 is removed by etching, the CVD / SiO ₂ film 106 as an interlayer insulating film can be left.
Further, Si is formed in or on the CVD / SiO ₂ film 106.
_If there is a substance having a high selectivity with respect to the SiO ₂ film, such as a 3N ₄ film, the etching becomes easy. Step 7: See FIG. 1 SiO ₂ film 113 constituting an interlayer insulating film by the CVD method
Is deposited, a contact is made between the source region 103 and the Al wiring 114.

As described above, the stacked capacitor cell of this embodiment is completed. (Embodiment 2) FIG. 2 is a view showing Embodiment 2.

In FIG. 2, reference numeral 201 denotes an Si substrate;
Is a field oxide film, 203 is a source region, 204 is a drain region, 205 is a gate electrode, 210 is a poly-Si layer constituting a storage node, 211 is a SiO ₂ film or a film of Si ₃ N ₄ and SiO ₂ films. A capacitor insulating film having a three-layer or three-layer structure; 212, a poly-Si layer forming a cell plate; 213, a CVD layer forming an interlayer insulating film;
The SiO ₂ film 214 is an Al wiring.

The Si substrate 201 has the field oxide film 20
2, each memory cell is partitioned. The MOS transistor for a memory cell includes a source region 203, a drain region 204, and a gate electrode 205 formed on the surface of a Si substrate 201. As a material of the gate electrode 205, polySi, metal, metal silicide, or the like is used.

A capacitor cell for a memory cell includes a poly-Si layer 210 and a SiO layer constituting a storage node.
It is composed of _two film or Si ₃ N ₄ capacitors was a two-layer or three-layer structure of a film insulation film 211 and the poly-Si layer 212 constituting the cell plate, forming the interlayer insulating film C
It is formed in the VD · SiO ₂ film 213.

The poly-Si layer 210 forming the storage node has an upright wall at its end face, and the poly-Si layer 212 forming the cell plate is opposed to the inner and outer surfaces of the wall. Since it is provided, the surface area of the capacitor can be increased, and a larger capacitor capacity can be obtained in the same area as the conventional stacked capacitor cell. Since the capacitor area is larger than that of the stacked capacitor cell of the first embodiment, the stacked capacitor cell of the present embodiment is larger.
The cell can have a larger capacitance than the stacked capacitor cell of the first embodiment.

Next, a method of manufacturing the stacked capacitor cell of this embodiment will be described. 9 to 12 are views showing the respective manufacturing steps leading to FIG. A method of manufacturing the stacked capacitor cell according to the present embodiment will be described with reference to FIGS. Step 1: See FIG. 9 A field oxide film 202 as an element isolation region is formed on the surface of a Si substrate 201 by LOCOS, and a source region 203 and a drain region 204 are formed by diffusion or ion implantation.

Next, after forming a gate oxide film, poly-Si, high melting point metal, silicide of high melting point metal, polycide of high melting point metal and the like are deposited on the gate oxide film and patterned to form a gate electrode 205. I do.

Then, after depositing a SiO ₂ film on the entire surface by the CVD method, the gate electrode 20 is anisotropically etched.
Forming an interlayer insulating film around 5 and other wiring
Cover with SiO ₂ film 206. Step 2: See FIG. 10 A thin Si ₃ N ₄ film 207 is deposited on the entire surface.

Next, after spin-on-glass (SOG) 208 is applied flat on the entire surface of the Si substrate 201, a resist 209 is applied on the entire surface, and a portion of the resist forming a storage node is removed.

The height of the storage node wall is SO
It is determined by the thickness of G208. Step 3: See FIG. 11 Using the resist 209 (FIG. 10) as a mask, the SOG 208 where the storage node is to be formed is removed by etching.

Next, in order to make contact between the storage node and the drain region 204, the drain region 2
After exposing the surface of the Si substrate 201 on the top of
A poly-Si layer 210 serving as a storage node is deposited by a vapor deposition method.

Thereafter, the SOG 208 is removed by etching. Step 4: See FIG. 12 When the outer surface and the inner surface of the wall standing upright on the end surface of the poly-Si layer 210 for the storage node are exposed, the poly-S
A capacitor insulating film 211 is formed on the surface of the i-layer 210. The capacitor insulating film 211 is formed on the bottom surface, the inner surface and the outer surface of the wall of the poly-Si layer 210 for the storage node. As the capacitor insulating film 211, thermal SiO ₂
A film or a two-layer film or a three-layer film of a Si ₃ N ₄ film and a SiO ₂ film is used. Step 5: See FIG. 2 After forming the capacitor insulating film 211, a poly-Si layer 212 for a cell plate is deposited, and the cell plate is patterned.

Next, after depositing a CVD / SiO ₂ film 213 constituting an interlayer insulating film by the CVD method, a contact is made between the source region 203 and the Al wiring 214. Thus, the stacked capacitor cell of the present embodiment is completed.

[0046]

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the inner surface or the inner surface and the outer surface of the wall standing upright on the end surface of the storage node can be used as the capacitor capacitance. A larger capacitor capacity can be obtained in the same area as the capacitor cell.

Therefore, each element constituting the semiconductor integrated circuit device can be miniaturized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram of Embodiment 2 of the present invention.

FIG. 3 is an explanatory view of step 1 of Example 1.

FIG. 4 is an explanatory view of a step 2 in the first embodiment.

FIG. 5 is an explanatory view of step 3 of the first embodiment.

FIG. 6 is an explanatory view of a step 4 in the first embodiment.

FIG. 7 is an explanatory diagram of step 5 of the first embodiment.

FIG. 8 is an explanatory diagram of step 6 of the first embodiment.

FIG. 9 is an explanatory diagram of Step 1 of Example 2.

FIG. 10 is an explanatory diagram of step 2 of the second embodiment.

FIG. 11 is an explanatory diagram of step 3 of the second embodiment.

FIG. 12 is an explanatory diagram of step 4 of the second embodiment.

FIG. 13 is an explanatory diagram of Conventional Example 1.

FIG. 14 is an explanatory diagram of Conventional Example 2.

[Explanation of symbols]

101: Si substrate 102: Field oxide film 103: Source region 104: Drain region 105: Gate electrode 109: Poly-Si layer constituting a storage node 111: _{2 of} SiO ₂ film, Si ₃ N ₄ film and SiO ₂ film
Capacitor insulating film having a layer or three-layer structure 112: Poly-Si layer forming a cell plate 113: CVD SiO ₂ film forming an interlayer insulating film 114: Al wiring 201: Si substrate 202: Field oxide film 203: Source Region 204: Drain region 205: Gate electrode 209: Poly-Si layer constituting storage node 211: _{2 of} SiO ₂ film or Si ₃ N ₄ film and SiO ₂ film
Capacitor insulating film 212 having a three-layer or three-layer structure 212: Poly Si layer forming a cell plate 213: CVD SiO ₂ film forming an interlayer insulating film 214: Al wiring

────────────────────────────────────────────────── (5) References JP-A-62-48062 (JP, A) JP-A-62-128168 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (4)

(57) [Claims] A step of forming a field insulating film defining an element region on a semiconductor substrate; a step of forming a gate electrode on a surface of the semiconductor substrate in the element region via a gate insulating film; Forming a source or drain region on the substrate surface on both sides; and forming an opening on the gate electrode, on the field insulating film, and on the source or drain region between the gate electrode and the field insulating film. Forming a bottom surface and an insulating layer having a side surface extending substantially perpendicular to a main surface of the substrate surface from above the gate electrode and the field insulating film as a side wall of the opening; Forming a conductive layer on the side wall and the insulating layer, and electrically removing the conductive layer on the insulating layer to form a conductive layer. A step of forming a storage node comprising a layer, a step of forming a capacitor insulating film on the surface of the storage node, and a step of forming a counter electrode on the surface of the capacitor insulating film Device manufacturing method. 2. A step of forming a field insulating film defining an element region on a semiconductor substrate; a step of forming a gate electrode on a surface of the semiconductor substrate in the element region via a gate insulating film; Forming a source or drain region on the substrate surface on both sides; and forming an opening on the gate electrode, on the field insulating film, and on the source or drain region between the gate electrode and the field insulating film. Forming a bottom surface and an insulating layer having a side surface extending substantially perpendicular to a main surface of the substrate surface from above the gate electrode and the field insulating film as a side wall of the opening; Forming a conductive layer on the side wall and the insulating layer, and electrically removing the conductive layer on the insulating layer to form a conductive layer. Forming a storage node consisting of a layer; removing the insulating layer of the storage node contacting the storage node extending substantially perpendicular to a main surface of the substrate surface; A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a capacitor insulating film on a surface of a node; and a step of forming a counter electrode on the surface of the capacitor insulating film. A step of forming a stopper film extending on the gate electrode, the field insulating film and the source or drain region after forming the gate electrode; and forming the insulating layer on the stopper film. Forming the insulating layer with the stopper layer as a stopper, and etching the insulating layer, on the gate electrode, on the field insulating film, and on the source or drain region between the gate electrode and the field insulating film. Forming the opening from the gate electrode and the field insulating film, the opening having a side surface extending substantially perpendicular to the main surface of the substrate surface. 3. The method for manufacturing a semiconductor integrated circuit device according to item 2. 4. After forming the conductive layer, a step of filling the opening with a coating film, and then selectively removing the conductive layer on the insulating layer,
Forming a storage node comprising the conductive layer. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: