KR100246467B1 - Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask - Google Patents

Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask Download PDF

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KR100246467B1
KR100246467B1 KR1019950055948A KR19950055948A KR100246467B1 KR 100246467 B1 KR100246467 B1 KR 100246467B1 KR 1019950055948 A KR1019950055948 A KR 1019950055948A KR 19950055948 A KR19950055948 A KR 19950055948A KR 100246467 B1 KR100246467 B1 KR 100246467B1
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film
semiconductor substrate
pattern
conductive film
capacitor
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KR1019950055948A
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Korean (ko)
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KR970054044A (en
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박정호
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 반도체 소자의 캐패시터 제조방법에 있어서, 반도체 기판(1) 상에 층간 절연막(3)을 증착하는 단계; 상기 층간절연막(3)에 콘택홀을 형성하여 상기 반도체 기판(1)의 일부영역을 노출시키는 단계; 노출된 상기 반도체 기판(1)과 콘택을 이루는 다결정 실리콘막(5)을 증착하는 단계; 상기 다결정 실리콘막(5) 상에 감광막(30)을 도포하는 단계; 상기 감광막(30)에 입사되는 빛의 양이 각 부위별로 다르게 입사되도록 노광시켜 형성하는 단계; 및 선택식각비가 동일한 건식식각 가스로 상기 감광막(30)과 상기 다결정 실리콘막(5)을 차례로 식각하여 상기 다결정 실리콘막(5)의 표면적을 증가시키는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method for manufacturing a capacitor of a semiconductor device, the method comprising: depositing an interlayer insulating film (3) on a semiconductor substrate (1); Forming a contact hole in the interlayer insulating film (3) to expose a portion of the semiconductor substrate (1); Depositing a polycrystalline silicon film (5) in contact with the exposed semiconductor substrate (1); Applying a photosensitive film (30) on the polycrystalline silicon film (5); Exposing to form different amounts of light incident on the photosensitive film 30 for each part; And increasing the surface area of the polycrystalline silicon film 5 by sequentially etching the photoresist film 30 and the polycrystalline silicon film 5 with a dry etching gas having the same selective etching ratio.

Description

위상반전마스크의 사이드 로브를 이용하는 반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device Using Side Lobe of Phase Inversion Mask

제1도 내지 제3도는 본 발명에 따른 반도체 캐패시터의 제조 공정 단면도.1 to 3 are cross-sectional views of the manufacturing process of the semiconductor capacitor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 3 : 층간절연막1 silicon substrate 3 interlayer insulating film

5, 9 : 다결정 실리콘막 7 : 유전막5, 9: polycrystalline silicon film 7: dielectric film

11, 11′ : 정상 홈 패턴 13, 13′ : 기생 홈 패턴11, 11 ′: normal groove pattern 13, 13 ′: parasitic groove pattern

20, 30 : 감광막 패턴20, 30: photosensitive film pattern

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 위상 반전 마스크를 이용한 노광 공정시 발생하는 사이드 로브를 이용하여 초고집적 반도체 소자의 캐패시터의 유효면적을 극대화 할 수 있는 방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of maximizing the effective area of a capacitor of an ultra-high density semiconductor device by using a side lobe generated during an exposure process using a phase inversion mask.

일반적으로, 반도체 소자가 초고집적 소자로 발전되어 감에 따라 현재 제조되고 있는 캐패시터로는 유효면적을 확보하기가 어려울 뿐만 아니라 많은 공정 스텝에 따라 공정시간이 많이 소요되는 단점을 가지고 있다.In general, as a semiconductor device is developed into an ultra-high integrated device, it is not only difficult to secure an effective area with a capacitor that is currently manufactured, but also has a disadvantage that a process time is required according to many process steps.

따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 위상반전 마스크를 이용할 경우에 생기는 사이드 로브 효과(Side-Lobe Effect)를 이용하여 캐패시터의 충분한 면적을 확보하여 고집적 메모리 소자의 제조를 가능하도록 하는 반도체 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention devised to solve the above problems is to secure a sufficient area of the capacitor by using the side-lobe effect generated when using a phase inversion mask (semiconductor) to enable the manufacture of highly integrated memory devices It is an object of the present invention to provide a capacitor manufacturing method.

상기 목적을 달성하기 위하여 본 발명은, 반도체 기판 상에 층간절연막을 증착하는 단계; 상기 층간절연막 내에 콘택홀을 형성하여 상기 반도체 기판의 일부영역을 노출시키는 단계; 노출된 상기 반도체 기판과 콘택을 이루는 전하 저장 전극용 전도막을 증착하는 단계; 상기 전하 저장 전극용 전도막 상에 감광막을 도포하는 단계; 노광시 사이드로브 효과를 일으키는 위상반전마스크를 사용하여 노광영역별로 다른 광량으로 상기 감광막을 노광한 다음, 상기 감광막을 현상하여 깊이가 일정하지 않은 다수의 홈을 갖는 감광막 패턴을 형성하는 단계; 및 상기 감광막 패턴과 상기 전도막의 식각선택비가 동일한 조건으로 상기 감광막 패턴 및 상기 전도막을 식각함으로써 깊이가 일정하지 않은 다수의 홈을 갖는 전하저장 전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법을 제공한다.The present invention to achieve the above object, the step of depositing an interlayer insulating film on a semiconductor substrate; Forming a contact hole in the interlayer insulating film to expose a portion of the semiconductor substrate; Depositing a conductive film for a charge storage electrode making contact with the exposed semiconductor substrate; Coating a photosensitive film on the conductive film for the charge storage electrode; Exposing the photoresist film with a different amount of light for each exposure region using a phase inversion mask that causes a side lobe effect during exposure, and then developing the photoresist film to form a photoresist pattern having a plurality of grooves having a constant depth; And forming a charge storage electrode having a plurality of grooves not having a constant depth by etching the photosensitive film pattern and the conductive film under the same etching selectivity of the photosensitive film pattern and the conductive film. to provide.

이하, 첨부된 도면 제1도 내지 제3도를 통하여 본 발명에 따른 캐패시터 제조방법을 상세히 살펴보면 다음과 같다.Hereinafter, the capacitor manufacturing method according to the present invention will be described in detail with reference to FIGS. 1 to 3 as follows.

먼저, 제1도에 도시된 바와 같이 반도체 기판(1) 위에 층간절연막(3)을 증착한 후 상기 층간절연막(3) 상에 콘택홀 형성 영역을 정의하는 제1 감광막 패턴(20)을 형성한다.First, as shown in FIG. 1, an interlayer insulating layer 3 is deposited on the semiconductor substrate 1, and then a first photoresist layer pattern 20 defining a contact hole forming region is formed on the interlayer insulating layer 3. .

이어서, 제2도와 같이 상기 제1 감광막 패턴(20)을 식각마스크로 이용하여 층간절연막(3)를 건식식각해서 반도체 기판(1)을 노출시키는 콘택홀을 형성한 다음, 상기 제1 감광막 패턴(20)을 제거하고 저장전극을 이룰 도핑된 제1 다결정 실리콘막(5)을 증착한 다음, 제2 감광막 패턴(30)을 형성한다.Subsequently, as shown in FIG. 2, the first photoresist layer pattern 20 is used as an etching mask to dry-etch the interlayer insulating layer 3 to form a contact hole exposing the semiconductor substrate 1, and then the first photoresist layer pattern ( 20) is removed and the doped first polycrystalline silicon film 5 is formed to form the storage electrode, and then the second photoresist film pattern 30 is formed.

상기 제2 감광막 패턴(30)은 위상반전 마스크를 사용하여 사이드-로브 효과(Side-Lobe Effect)에 의해 형성된다. 즉, 위상반전 마스크 상에 정의된 형상에 따라 노광되어 상대적으로 깊은 정상 홈 패턴(11)과 위상 반전 마스크 상에 정의되지 않았으나 사이드-로브 효과에 의해 기생적으로 노광되어 상대적으로 얕은 홈 패턴(13)이 형성되는데, 상기 정상 홈 패턴(11)은 노광시 빛을 20% 차단함으로써 형성되고, 상기 기생 홈 패턴(13)은 그 이상의 빛을 차단함으로써 형성된다.The second photoresist layer pattern 30 is formed by a side-lobe effect using a phase inversion mask. That is, according to the shape defined on the phase inversion mask, the relatively deep normal groove pattern 11 and the phase pattern that are not defined on the phase inversion mask but are parasitically exposed by the side-lobe effect are relatively shallow groove patterns 13. ), The normal groove pattern 11 is formed by blocking 20% of light during exposure, and the parasitic groove pattern 13 is formed by blocking more light.

끝으로, 제3도에 도시된 바와 같이 제2 상기 감광막 패턴(30)과 상기 제1 다결정 실리콘막(5)의 선택식각비가 1:1이 되도록 Cl2및 N2가스를 25:8의 비율로 혼합하여 상기 제1 다결정 실리콘막(5)이 전기적으로 단락되지 않도록 상기 제2 감광막 패턴(30)과 제1 다결정 실리콘막(5)을 차례로 건식식각한다. 이와 같은 건식식각 과정에서 제2 감광막 패턴이 제거되면서 제2 감광막 패턴(30)에 형성된 정상홈 패턴(11)과 기생 홈 패턴(13)이 제1 다결정 실리콘막(5) 내에 전사되어 제1 다결정 실리콘막(5) 내에 깊이가 일정하지 않은 다수의 홈 패턴(11′, 13′)이 형성된다.Finally, as shown in FIG. 3, the ratio of Cl 2 and N 2 gases is 25: 8 so that the selective etching ratio of the second photoresist pattern 30 and the first polycrystalline silicon layer 5 is 1: 1. The second photosensitive film pattern 30 and the first polycrystalline silicon film 5 are sequentially dry-etched so as to prevent the first polycrystalline silicon film 5 from being electrically shorted by mixing. As the second photoresist layer pattern is removed in the dry etching process, the normal groove pattern 11 and the parasitic groove pattern 13 formed on the second photoresist layer pattern 30 are transferred into the first polycrystalline silicon layer 5 to be transferred to the first polycrystalline layer. In the silicon film 5, a plurality of groove patterns 11 'and 13' having a constant depth are formed.

이어서, 다수의 홈 패턴(11′, 13′)을 갖는 제1 다결정 실리콘막(5) 상에 유전막(7)을 증착한 후 제2 다결정 실리콘(9)을 증착하여 캐패시터의 플레이트 전극을 형성한다.Subsequently, after the dielectric film 7 is deposited on the first polycrystalline silicon film 5 having the plurality of groove patterns 11 ′ and 13 ′, the second polycrystalline silicon 9 is deposited to form a plate electrode of the capacitor. .

상기와 같이 이루어지는 본 발명은 위상반전 마스크를 이용하 노광 공정시 발생하는 사이드 로브 효과를 이용하여 감광막에 입사되는 빛의 양을 조절함으로써 감광막 패턴에 형성되는 홈 패턴의 깊이를 조절하고, 상기 감광막 패턴과 다결정 실리콘막과의 선택비가 1:1인 가스로 건식식각함으로써 간단한 마스크 공정으로 전하 저장 전극의 표면적을 증대시켜 고집적 소자의 캐패시터를 확보할 수 있는 효과가 있다. 또한, 제2 감광막 패턴과 제1 다결정 실리콘막을 모두 식각함으로써, 감광막 패턴 제거를 위한 별도의 공정 생략할 수 있어 제조 공정의 단순화를 꾀할 수 있다.According to the present invention, the depth of the groove pattern formed in the photosensitive film pattern is adjusted by controlling the amount of light incident on the photosensitive film by using the side lobe effect generated during the exposure process using the phase inversion mask. By dry etching with a gas having a selectivity of 1: 1 with the polycrystalline silicon film, the surface area of the charge storage electrode can be increased by a simple masking process, thereby securing a capacitor of a highly integrated device. In addition, by etching both the second photosensitive film pattern and the first polycrystalline silicon film, a separate process for removing the photosensitive film pattern may be omitted, thereby simplifying the manufacturing process.

Claims (3)

반도체 소자의 캐패시터 제조방법에 있어서, 반도체 기판 상에 층간절연막을 증착하는 단계; 상기 층간절연막 내에 콘택홀을 형성하여 상기 반도체 기판의 일부영역을 노출시키는 단계; 노출된 상기 반도체 기판과 콘택을 이루는 전하 저장 전극용 전도막을 증착하는 단계; 상기 전하 저장 전극용 전도막 상에 감광막을 도포하는 단계; 노광시 사이드로브 효과를 일으키는 위상반전마스크를 사용하여 노광영역 별로 다른 광량으로 상기 감광막을 노광한 다음, 상기 감광막을 현상하여 깊이가 일정하지 않은 다수의 홈을 갖는 감광막 패턴을 형성하는 단계; 및 상기 감광막 패턴과 상기 전도막의 식각선택비가 동일한 조건으로 상기 감광막 패턴 및 상기 전도막을 식각함으로써 깊이가 일정하지 않은 다수의 홈을 갖는 전하저장 전극을 형성하는 단계를 포함하는 반도체 소자의 캐패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, comprising: depositing an interlayer insulating film on a semiconductor substrate; Forming a contact hole in the interlayer insulating film to expose a portion of the semiconductor substrate; Depositing a conductive film for a charge storage electrode making contact with the exposed semiconductor substrate; Coating a photosensitive film on the conductive film for the charge storage electrode; Exposing the photoresist film with a different amount of light for each exposure area using a phase inversion mask that causes a side lobe effect during exposure, and then developing the photoresist film to form a photoresist pattern having a plurality of grooves having a constant depth; And forming a charge storage electrode having a plurality of grooves not having a constant depth by etching the photosensitive film pattern and the conductive film under the same etching selectivity of the photosensitive film pattern and the conductive film. 제1항에 있어서, 상기 전도막을 폴리실리콘막으로 형성하고, 상기 감광막과 상기 전도막을 Cl2및 N2의 혼합 가스로 식각하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 1, wherein the conductive film is formed of a polysilicon film, and the photosensitive film and the conductive film are etched with a mixed gas of Cl 2 and N 2 . 제2항에 있어서, 상기 Cl2및 N2의 혼합 비율은 25 : 8인 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The method of claim 2, wherein the mixing ratio of Cl 2 and N 2 is 25: 8.
KR1019950055948A 1995-12-23 1995-12-23 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask KR100246467B1 (en)

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JPH03222417A (en) * 1990-01-29 1991-10-01 Nec Corp Manufacture of semiconductor device
JPH0677430A (en) * 1992-08-28 1994-03-18 Hitachi Ltd Semiconductor device and manufacture thereof

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