JPH03222417A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03222417A
JPH03222417A JP1977790A JP1977790A JPH03222417A JP H03222417 A JPH03222417 A JP H03222417A JP 1977790 A JP1977790 A JP 1977790A JP 1977790 A JP1977790 A JP 1977790A JP H03222417 A JPH03222417 A JP H03222417A
Authority
JP
Japan
Prior art keywords
etching
gas
undercut
ion source
ecr ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1977790A
Other languages
Japanese (ja)
Inventor
Hidekazu Nakano
仲野 英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1977790A priority Critical patent/JPH03222417A/en
Publication of JPH03222417A publication Critical patent/JPH03222417A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent undercut induced by scattered active species by discharging mixed etching ga to which inactive dilution gas is added in an ECR ion source. CONSTITUTION:As impurities, phosphorous is added to an oxidizing silicon film 1 which forms an offset region. When a polysilicon film 2 is deposited thereon, mask patterns are formed on the silicon film by a photo resist film 3. Cl2 is used as an etching gas while N2 gas is used as a dilution gas. Under the pressure of 0.05Torr, the plasma generated in an ECR ion source is converged by a magnetic field and introduced into an etching chamber where etching is carried out. Then, a favorable etching shape, which is virtually free of undercut, is available. It is, therefore, possible to inhibit undercut induced by scattered active species.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にECRイオ
ン源を用いた場合のドライエツチング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a dry etching method using an ECR ion source.

〔従来の技術〕[Conventional technology]

従来ECRイオン源を用いたドライエツチング方法は高
真空条件で高密度な活性種が得られるために、直進性の
良い活性種による異方性加工に優れ、広汎に用いられる
ようになってきている。
Conventional dry etching methods using ECR ion sources can obtain high-density active species under high-vacuum conditions, so they are excellent at anisotropic processing using active species that move in a straight line, and are becoming widely used. .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが上述のエツチング方法ではその活性種の直進性
故に第2図に示すように段差領域の近傍で散乱され、ア
ンダーカットを生じるという欠点がある。
However, the above-mentioned etching method has the disadvantage that, due to the linear nature of the active species, they are scattered in the vicinity of the step region as shown in FIG. 2, resulting in undercuts.

この欠点を補う方法としては (1)エツチングガスに側壁保護膜を形成するための添
加ガスを加える方法。
Methods to compensate for this drawback include (1) a method of adding an additive gas to the etching gas for forming a sidewall protective film;

(2)エツチング時に基板を極低湯道冷却しエツチング
種の散乱を抑制する方法。
(2) A method of suppressing scattering of etching species by extremely low runner cooling of the substrate during etching.

等が考案されているが(1)ではエツチングの再現性が
著しく低下するという欠点があり、(2)ではエツチン
グ装置の構成が複雑になり、運用が困難になるという欠
点がある。
etc. have been devised, but (1) has the disadvantage that the reproducibility of etching is significantly reduced, and (2) has the disadvantage that the configuration of the etching apparatus becomes complicated and operation becomes difficult.

〔課題を解決するための手段〕[Means to solve the problem]

本発明はECRイオン源を用いたドライエツチング工程
を含む半導体装置の製造方法において、エチングガスに
、不活性な希釈ガスを加えた混合ガスを前記ECRイオ
ン源内で放電させるというものである。
The present invention is a method of manufacturing a semiconductor device including a dry etching process using an ECR ion source, in which a mixed gas containing an etching gas and an inert diluent gas is discharged within the ECR ion source.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)、(b)は本発明の一実施例を説明するた
めのエツチング工程前後の半導体チップの断面図である
FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip before and after an etching process for explaining one embodiment of the present invention.

段差領域を形成する酸化シリコン膜1上に不純物として
燐が添加されたポリシリコン膜2が堆積された上にフォ
トレジスト膜3によりマスクパターンが形成されている
(第1図(a))。
A polysilicon film 2 doped with phosphorus as an impurity is deposited on a silicon oxide film 1 forming a step region, and a mask pattern is formed with a photoresist film 3 (FIG. 1(a)).

エツチングガスとしてC12,希釈ガスとしてN2を用
い0.05Torrの圧力下でECRイオン源内で発生
したプラズマを磁場により収束させエツチング室へ導入
しエツチングを行うことによりほぼアンダーカットのな
い良好なエツチング形状を得る(第1図(b))。
Using C12 as the etching gas and N2 as the diluent gas, the plasma generated in the ECR ion source under a pressure of 0.05 Torr is focused by a magnetic field and introduced into the etching chamber for etching, resulting in a good etched shape with almost no undercuts. (Fig. 1(b)).

N2添加率とポリシリコンのエツチングレート及びアン
ダーカット量との関係は第3図に示す。
The relationship between the N2 addition rate, polysilicon etching rate, and undercut amount is shown in FIG.

ただし、N2分圧比0%を指数1゜0としである。However, the index is 1°0 when the N2 partial pressure ratio is 0%.

尚N2分圧比が50%以上ではエッチレートの低下が著
しく実用的ではなく、アンダーカット量も不明である。
Note that when the N2 partial pressure ratio is 50% or more, the etch rate decreases significantly and is not practical, and the amount of undercut is also unknown.

また実用に際してはN2の添加によりエッチレートが低
下するため多段階の条件設定により最初はC!12単独
でエツチングを行い、ポリシリコン膜を半ば迄エツチン
グした11 N 2にて希釈してエツチングを行うこと
が処理効率の面から効果的である。
In addition, in practical use, the etch rate decreases due to the addition of N2, so by setting conditions in multiple stages, the initial C! From the viewpoint of processing efficiency, it is effective to perform etching with 12 alone and dilute with 11 N2, which has etched the polysilicon film halfway.

実施例ではエツチングガスとしてcJ22.希釈ガスと
してN2を揚げて説明したが、その他エツチングガスと
してはNF3.CF4.HF。
In the example, cJ22. Although N2 was used as the diluting gas in the explanation, other etching gases include NF3. CF4. HF.

HCJ、HBr又はSF6.及びその混合系、希釈ガス
としてはHe、Ar又はNe及びその混合系を用いても
同様な効果が得られる。
HCJ, HBr or SF6. Similar effects can be obtained by using He, Ar, Ne, or a mixture thereof as the diluent gas.

また被エツチング物としてポリシリコンを揚げたが前述
のガス種の選択によりW、Mo、Ti。
In addition, although polysilicon was fried as the object to be etched, W, Mo, and Ti were used depending on the selection of the gas type mentioned above.

Ta、及びそのシリサイドについても同様である。The same applies to Ta and its silicide.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はエツチングガスに希釈ガス
を加えることにより、活性種の散乱によるアンダーカッ
トを抑制できる効果がある。
As explained above, the present invention has the effect of suppressing undercuts due to scattering of active species by adding a diluent gas to the etching gas.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)は本発明の一実施例を説明する為
のエツチング工程前後の断面図、第2図は従来例による
エツチング後の断面図、第3図は本発明の一実施例にお
けるエツチングレート及びアンダーカット量のN2分圧
依存性を示す特性図である。 1・・・酸化シリコン膜、2・・・ポリシリコン膜、3
・・・フォトレジスト膜、4・・・エツチング種、5・
・・希釈ガス。
FIGS. 1(a) and (b) are sectional views before and after the etching process for explaining one embodiment of the present invention, FIG. 2 is a sectional view after etching according to a conventional example, and FIG. 3 is a sectional view of one embodiment of the present invention. FIG. 3 is a characteristic diagram showing the dependence of etching rate and undercut amount on N2 partial pressure in Examples. 1... Silicon oxide film, 2... Polysilicon film, 3
... Photoresist film, 4... Etching species, 5.
...Dilution gas.

Claims (1)

【特許請求の範囲】 1、ECRイオン源を用いたドライエッチング工程を含
む半導体装置の製造方法において、エチングガスに、不
活性な希釈ガスを加えた混合ガスを前記ECRイオン源
内で放電させることを特徴とする半導体装置の製造方法
。 2、エッチングガスはSF_6、NF_3、CF_4、
HF、HCl、HBr又はCl_2であり、希釈ガスは
N_2、He、Ar又はNeである請求項1記載の半導
体装置の製造方法。
[Claims] 1. A method for manufacturing a semiconductor device including a dry etching step using an ECR ion source, characterized in that a mixed gas in which an inert diluent gas is added to an etching gas is discharged within the ECR ion source. A method for manufacturing a semiconductor device. 2. Etching gas is SF_6, NF_3, CF_4,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the diluent gas is HF, HCl, HBr, or Cl_2, and the diluent gas is N_2, He, Ar, or Ne.
JP1977790A 1990-01-29 1990-01-29 Manufacture of semiconductor device Pending JPH03222417A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977790A JPH03222417A (en) 1990-01-29 1990-01-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977790A JPH03222417A (en) 1990-01-29 1990-01-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03222417A true JPH03222417A (en) 1991-10-01

Family

ID=12008760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977790A Pending JPH03222417A (en) 1990-01-29 1990-01-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03222417A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03241830A (en) * 1990-02-20 1991-10-29 Mitsubishi Electric Corp Plasma etching process
JPH05121370A (en) * 1991-10-25 1993-05-18 Nec Corp Dry-etching method
KR100243911B1 (en) * 1996-12-16 2000-02-01 김영환 Polysilicon etching method
KR100246467B1 (en) * 1995-12-23 2000-03-15 김영환 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask
JP2002538620A (en) * 1999-03-04 2002-11-12 サーフィス テクノロジー システムズ ピーエルシー Gas delivery system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03241830A (en) * 1990-02-20 1991-10-29 Mitsubishi Electric Corp Plasma etching process
JPH05121370A (en) * 1991-10-25 1993-05-18 Nec Corp Dry-etching method
KR100246467B1 (en) * 1995-12-23 2000-03-15 김영환 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask
KR100243911B1 (en) * 1996-12-16 2000-02-01 김영환 Polysilicon etching method
JP2002538620A (en) * 1999-03-04 2002-11-12 サーフィス テクノロジー システムズ ピーエルシー Gas delivery system

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