KR100243911B1 - Polysilicon etching method - Google Patents
Polysilicon etching method Download PDFInfo
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- KR100243911B1 KR100243911B1 KR1019960066165A KR19960066165A KR100243911B1 KR 100243911 B1 KR100243911 B1 KR 100243911B1 KR 1019960066165 A KR1019960066165 A KR 1019960066165A KR 19960066165 A KR19960066165 A KR 19960066165A KR 100243911 B1 KR100243911 B1 KR 100243911B1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 36
- 238000005530 etching Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims description 7
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000007789 gas Substances 0.000 description 11
- 230000003628 erosive effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910008045 Si-Si Inorganic materials 0.000 description 2
- 229910003691 SiBr Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910006411 Si—Si Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 102000010410 Nogo Proteins Human genes 0.000 description 1
- 108010077641 Nogo Proteins Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
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Abstract
본 발명은 다결정실리콘의 식각방법에 관한 것으로서 반도체기판에 산화막을 형성하는 공정과, 상기 산화막 상에 불순물이 도핑된 다결정실리콘층을 형성하고 상기 다결정실리콘층 상의 소정 부분에 감광막을 형성하는 공정과, 상기 감광막을 마스크로 사용하고 식각 가스인 Cl2/O2에 N2를 첨가하여 상기 다결정실리콘층을 건식 식각하여 패터닝하는 공정을 구비한다. 따라서, 별도의 장치가 필요하지 않으므로 원가를 절감하면서 노칭 현상의 발생을 방지할 수 있다.The present invention relates to a method of etching polycrystalline silicon, comprising the steps of forming an oxide film on a semiconductor substrate, forming a polycrystalline silicon layer doped with impurities on the oxide film, and forming a photoresist film on a predetermined portion on the polycrystalline silicon layer; Using the photosensitive film as a mask and adding N 2 to Cl 2 / O 2 , which is an etching gas, to dry-etch and pattern the polysilicon layer. Therefore, since a separate device is not required, the occurrence of the notching phenomenon can be prevented while reducing the cost.
Description
제1a도 내지 c도는 본 발명의 실시예에 따른 다결정실리콘의 식각방법을 도시한 공정도.1a to c is a process chart showing an etching method of polysilicon according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 필드산화막11: semiconductor substrate 13: field oxide film
15 : 게이트산화막 17 : 다결정실리콘층15 gate oxide film 17 polysilicon layer
17a : 게이트 19 : 감광막17a: gate 19: photosensitive film
본 발명은 다결정실리콘의 식각방법에 관한 것으로서, 특히 불순물이 도핑된 다결정실리콘을 노칭(notching) 현상을 방지하면서 건식식각할 수 있는 다결정실리콘의 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method of polysilicon, and more particularly, to an etching method of polycrystalline silicon that can dry-etch polycrystalline silicon doped with impurities while preventing notching.
반도체장치의 제조 공정에 있어서 다결정실리콘은 불순물이 도핑되어 게이트 또는 배선 등에 사용된다. 이러한 불순물이 도핑된 다결정실리콘을 산하막과 같은 절연성물질이나 감광막을 마스크로 사용하고 고밀도 플라즈마로 건식 식각하여 게이트를 형성할 때 다결정실리콘층과 게이트산화막의 식각 선택비를 고려하여 과도 식각해야 한다. 이러한 경우, 식각될 웨이퍼의 외곽 부분에 전장이 집중되어 다결정실리콘층의 게이트산화막과 계면을 이루는 부분이 식각되는 노칭 현상이 발생된다. 노칭 현상은 다결정실리콘이 다수 개의 라인(line)을 이룰 때 최외곽에 있는 라인에 심하게 나타난다.In the manufacturing process of a semiconductor device, polysilicon is doped with impurities and used for a gate or a wiring. When the impurity doped polysilicon is formed by using an insulating material such as a sub-layer or a photoresist as a mask and dry etching with a high density plasma to form a gate, it must be excessively etched in consideration of the etching selectivity of the polysilicon layer and the gate oxide film. In this case, the electric field is concentrated on the outer portion of the wafer to be etched, and a notching phenomenon occurs in which a portion forming an interface with the gate oxide film of the polysilicon layer is etched. Notching phenomenon is severe in the outermost line when the polysilicon forms a number of lines.
이러한 노칭 현상을 해결하기 위한 종래 방법은 TM(Time Modulated) 플라즈마 방법을 사용하였다. 상기 TM 플라즈마 방법은 수㎲∼수십㎲씩 플라즈마를 온(on)/오프(off)함으로써 전하(charge)의 축적을 중화시키므로써 음영효과 (shading effect)에 따른 전하의 축적에 기인하는 노칭 현상의 발생을 억제하였다.As a conventional method for solving such a notching phenomenon, a TM (Time Modulated) plasma method is used. The TM plasma method neutralizes the accumulation of charges by turning the plasma on and off by several tens to several tens of degrees, thereby eliminating the notching phenomenon due to the accumulation of charges due to the shading effect. Occurrence was suppressed.
노칭 현상을 해결하기 다른 방법으로 식각 가스인 Cl2/O2에 HBr을 첨가하여 사용하였다. 상기한 방법은 HBr의 분자 특성상 플라즈마 내에서 이온화할 수 있는 충돌 반경이 크고, 또한, Cl2플라즈마에 비해 상대적으로 낮은 부유 전압(floating voltage : Vf)을 갖는 특성을 갖는다. 그리고, 식각 생성물인 SiBr2또는 SiBr4의 중기압이 상대적으로 낮아서 Cl2보다 나은 측면 보호막을 형성할 수 있다. 그러므로, 다결정실리콘을 건식 식각할 때 노칭 현상을 억제할 수 있다.To solve the notching phenomenon, HBr was added to the etching gas, Cl 2 / O 2 . The above method has a characteristic that the collision radius that can be ionized in the plasma is large due to the molecular nature of HBr, and has a relatively low floating voltage (Vf) compared to the Cl 2 plasma. In addition, since the medium pressure of SiBr 2 or SiBr 4 , which is an etching product, is relatively low, a side protective film that is better than Cl 2 may be formed. Therefore, notching phenomenon can be suppressed when dry etching polycrystalline silicon.
그러나, 상술한 종래의 Tm 플라즈마 방법은 별도의 TM 플라즈마 발진기가 필요하므로 원가가 상승되는 문제점이 있었다. 또한, 식각 가스인 Cl2/O2에 HBr을 첨가하는 방법은 노칭 현상을 완전히 방지할 수 없는 문제점이 있었다.However, the above-described conventional Tm plasma method requires a separate TM plasma oscillator, resulting in a cost increase. In addition, the method of adding HBr to the etching gas Cl 2 / O 2 has a problem that can not completely prevent the notching phenomenon.
따라서, 본 발명의 목적은 게이트 형성시 게이트산화막과 식각 선택비에 의해 과도식각하므로써 다수 개의 라인(line) 중 최외곽에 있는 라인에 발생되는 노칭 현상을 별도의 장치 없이 방지하여 원가를 절감할 수 있는 다결정실리콘의 식각방법을 제공함에 있다.Accordingly, an object of the present invention is to reduce the cost by preventing the notching phenomenon generated in the outermost line of the plurality of lines by the excessive etching by the gate oxide film and the etching selectivity when forming the gate without a separate device. The present invention provides an etching method of polysilicon.
상기 목적을 달성하기 위한 본 발명에 따른 다결정실리콘의 식각방법은 반도체 기판에 산화막을 형성하는 공정과, 상기 산화막 상에 불순물이 도핑된 다결정실리콘층을 형성하고 상기 다결정실리콘층 상의 소정 부분에 감광막을 형성하는 공정과, 상기 감광막을 마스크로 사용하고 식각 가스인 Cl2/O2에 N2를 첨가하여 상기 다결정실리콘층을 건식 식각하여 패터닝하는 공정을 구비한다.In order to achieve the above object, an etching method of polycrystalline silicon according to the present invention includes forming an oxide film on a semiconductor substrate, forming a polycrystalline silicon layer doped with impurities on the oxide film, and forming a photoresist film on a predetermined portion on the polycrystalline silicon layer. And forming a pattern by dry etching the polycrystalline silicon layer by adding N 2 to Cl 2 / O 2 , which is an etching gas, using the photosensitive film as a mask.
이하, 첨부한 도면을 참조하여 본 발명의 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1a도 내지 c도는 본 발명의 실시예에 따른 다결정실리콘의 식각 방법을 도시한 공정도이다.1a to c is a process chart showing the etching method of the polysilicon according to the embodiment of the present invention.
제1a도를 참조하면, 반도체기판(11)상의 소정 부분에 LOCOS(Local Oxidation of Silicon)등의 방법에 의해 필드산화막(13)을 형성한다. 그리고, 반도체기판(11)상의 필드산화막(13)이 형성되지 않은 부분에 열산화 방법에 의해 게이트산화막(15)을 형성한다.Referring to FIG. 1A, a field oxide film 13 is formed in a predetermined portion on the semiconductor substrate 11 by a method such as LOCOS (Local Oxidation of Silicon). Then, the gate oxide film 15 is formed in the portion where the field oxide film 13 on the semiconductor substrate 11 is not formed by the thermal oxidation method.
제1b도를 참조하면, 필드산화막(13) 및 게이트산화막(15)상에 불순물, 예를 들면, 인(P)등의 불순물이 도핑된 다결정실리콘층(17)을 화학기상증착(Chemical Vapor Deposition) 방법으로 증착하여 형성한다. 그리고, 다결정실리콘층(17) 상에 감광막(19)을 도포한다. 감광막(19)을 게이트 패턴이 형성된 노고아 마스크를 사용하여 노광하고, 이 노광된 부분을 다결정실리콘층(19)이 노출되도록 현상한다.Referring to FIG. 1B, the chemical vapor deposition of the polycrystalline silicon layer 17 doped with impurities such as phosphorus (P) on the field oxide film 13 and the gate oxide film 15 is performed. By vapor deposition). Then, the photosensitive film 19 is coated on the polysilicon layer 17. The photosensitive film 19 is exposed using a Nogo mask on which a gate pattern is formed, and the exposed portion is developed such that the polysilicon layer 19 is exposed.
제1c도를 참조하면, 감광막(19)을 마스크로 사용하여 다결정실리콘층(19)을 건식 식각하여 게이트(17a)를 형성한다. 상기에서, 게이트(17a)을 형성할 때 다결정실리콘층(17)을 게이트산화막(15)도 제거되도록 과도 식각한다. 그리고, 감광막(19)을 제거한다. 상기에서, 다결정실리콘층(17)을 건식 식각할 때 PMT(Plasma Materials Technology)사의 헬리콘 모드 플라즈마(Helicon mode plasma) 식각장비인 P8000을 사용하였다. 상기 식각 공정 조건은 소스 전력(source power)가 1500∼2500W 정도이고, 바이어스 전력(bias power)가 10∼100W 정도이며, 압력이 2∼5mT 정도이다. 그리고, 식각 가스로 20∼50 SCCM 정도의 Cl2, 2∼6 SCCM 정도의 O2, 2∼10 SCCM 정도의 N2를 사용하였다.Referring to FIG. 1C, the gate 17a is formed by dry etching the polysilicon layer 19 using the photosensitive film 19 as a mask. In the above, when the gate 17a is formed, the polysilicon layer 17 is excessively etched so that the gate oxide film 15 is also removed. Then, the photosensitive film 19 is removed. In the above, when dry etching the polysilicon layer 17, P8000 which is a helicon mode plasma (PM) (Helicon mode plasma) etching equipment of PMT (Plasma Materials Technology) was used. The etching process conditions have a source power of about 1500 to 2500 W, a bias power of about 10 to 100 W, and a pressure of about 2 to 5 mT. As the etching gas, Cl 2 of about 20 to 50 SCCM, O 2 of about 2 to 6 SCCM, and N 2 of about 2 to 10 SCCM were used.
상기에서 다결정실리콘층(17)과 게이트산화막(15)의 식각 선택비를 조절하기 위한 첨가 기체인 O2가스는 플라즈마 내에서 실리콘의 미결합수(danging bond)와 결합하여 Si-O 결합을 형성한다. 이러한 결합은 O2의 높은 전기음성도(electronegativity)에 의하여 편극화(polarization)를 이루게 한다. 그러므로, Si-Si의 백 본드(back bond)의 결합을 약하게 하여 주 식각 가스인 Cl2가 흡착되어 SiXOYClZ형태로 식각되게 한다. 상기에서, 식각 선택비가 높은 게이트산화막(15)상에서는 게이트(17a)의 측면에 흡착되어 있는 O2원자와 Si원자 간의 결합이 형성되고 운동도(mobility)가 큰 Cl2원자가 표면 확산될 수도 있어 노칭 현상이 발생될수도 있다.In the above, O 2 gas, which is an additive gas for controlling the etching selectivity of the polysilicon layer 17 and the gate oxide layer 15, is combined with the danging bond of silicon in the plasma to form a Si—O bond. . This bond causes polarization by the high electronegativity of O 2 . Therefore, the back bond of Si-Si is weakened so that Cl 2 , the main etching gas, is adsorbed and etched in the form of Si X O Y Cl Z. In the above, on the gate oxide film 15 having a high etching selectivity, a bond between O 2 atoms and Si atoms adsorbed on the side surface of the gate 17a is formed, and Cl 2 atoms having a high mobility may be surface-diffused. Phenomenon may occur.
그러나, N2가스는 O2가스에 비해 전기음성도가 작아서 Si-N 결합 후의 Si-Si 백본드 힘을 약하게 하는 정도가 작고 O2에 비해 게이트(17a)의 측면에 감광막(19)의 침식(erosion)에 따른 보호막의 형성을 빠르게 하므로 노칭 현상을 방지한다.However, the N 2 gas has a lower electronegativity than the O 2 gas, so that the degree of weakening of the Si-Si backbond force after Si-N bonding is small and the erosion of the photosensitive film 19 on the side of the gate 17a compared to O 2 ( The formation of a protective film due to erosion is accelerated to prevent notching.
상기에서, 식각 장비를 헬리콘 모드 플라즈마(Helicon mode plsma) 뿐만 아니라 ECR(Electron Cyclotron Resonance)를 포함하는 확산형(diffusion type)을 사용할 수 있는 데, 이 확산형 장비는 특성상 소스 전력이 클 수록 이온의 밀도가 증가하는 대신 에너지는 감소한다. 따라서, 소스 전력을 감소시켜 이온의 밀도를 감소시키고 씨스(sheath)에 형성된 전계를 그대로 따르는 에너지가 높은 이온을 형성하게 하여 수직으로 입사하는 정도에 벗어나는 이온의 수를 감소시킬 수 있다. 이에 의해, 식각 선택비가 낮아질 수 있으나 첨가 기체인 N2양을 증가하고 바이어스 전력을 감소시킴으로써 해결할 수 있다.In the above, the etching equipment may be used as a diffusion type including an ECR (Electron Cyclotron Resonance) as well as a helicon mode plasma (Helicon mode plsma), which is characterized in that as the source power is larger, Instead of increasing the density, the energy decreases. Therefore, the source power can be reduced to reduce the density of the ions, and the energy following the electric field formed in the sheath can form high ions, thereby reducing the number of ions that deviate from the degree of vertical incidence. Thereby, the etching selectivity can be lowered but can be solved by increasing the amount of N 2 which is the additive gas and reducing the bias power.
상술한 바와 같이 본 발명에 따른 다결정실리콘의 식각방법은 식각 가스인 Cl2및 O2에 N2를 첨가하므로써 건식 식각시 다결정실리콘의 식각된 측면에 감광막의 침식에 따른 보호막의 형성을 빠르게 한다.As described above, the etching method of the polysilicon according to the present invention accelerates the formation of the protective film due to the erosion of the photoresist on the etched side of the polysilicon during dry etching by adding N 2 to the etching gases Cl 2 and O 2 .
따라서, 본 발명은 별도의 장치가 필요하지 않으므로 원가를 절감하면서 노칭현상의 발생을 방지할 수 있는 잇점이 있다.Therefore, the present invention does not require a separate device has the advantage of preventing the occurrence of notching phenomenon while reducing the cost.
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| JPH03222417A (en) * | 1990-01-29 | 1991-10-01 | Nec Corp | Manufacture of semiconductor device |
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| KR100461506B1 (en) * | 2002-03-09 | 2004-12-14 | 한국전자통신연구원 | Method of etching thin film and method for manufacturing a transistor and a capacitor in a semiconductor device using the same |
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