KR100461506B1 - Method of etching thin film and method for manufacturing a transistor and a capacitor in a semiconductor device using the same - Google Patents
Method of etching thin film and method for manufacturing a transistor and a capacitor in a semiconductor device using the same Download PDFInfo
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- KR100461506B1 KR100461506B1 KR10-2002-0012670A KR20020012670A KR100461506B1 KR 100461506 B1 KR100461506 B1 KR 100461506B1 KR 20020012670 A KR20020012670 A KR 20020012670A KR 100461506 B1 KR100461506 B1 KR 100461506B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 128
- 238000000034 method Methods 0.000 title claims abstract description 81
- 238000005530 etching Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 239000003990 capacitor Substances 0.000 title abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 12
- 238000002156 mixing Methods 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- 238000004528 spin coating Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 125000002524 organometallic group Chemical group 0.000 claims description 2
- 238000000197 pyrolysis Methods 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 20
- 239000007789 gas Substances 0.000 description 19
- 229910052786 argon Inorganic materials 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
Abstract
본 발명은 박막 식각 방법 및 이를 이용한 반도체 소자의 트랜지스터 및 캐패시터 제조 방법에 관한 것으로, 헬리콘형 플라즈마(Helicon Plasma) 방법을 이용한 한번의 식각 공정으로 금속 박막과 강유전체 박막을 모두 패터닝함으로써, 하부층의 손상을 방지하고 식각 찌거기(Residue)가 발생되는 것을 방지하면서 공정 단계를 단순화하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 박막 식각 방법 및 이를 이용한 반도체 소자의 트랜지스터 및 캐패시터 제조 방법이 개시된다.The present invention relates to a thin film etching method and a method of manufacturing a transistor and a capacitor of a semiconductor device using the same, and to damage the underlying layer by patterning both the metal thin film and the ferroelectric thin film in one etching process using the Helicon Plasma method Disclosed are a thin film etching method and a method of manufacturing a transistor and a capacitor of a semiconductor device using the same, which can improve the reliability of the process and the electrical characteristics of the device by preventing the process and simplifying the process steps while preventing etching residues.
Description
본 발명은 박막 식각 방법 및 이를 이용한 반도체 소자의 트랜지스터 및 캐패시터 제조 방법에 관한 것으로, 특히 금속 박막과 강유전체 박막의 패터닝 공정을 단순화하면서 소자의 전기적 특성을 향상시킬 수 있는 박막 식각 방법 및 이를 이용한 반도체 소자의 트랜지스터 및 캐패시터 제조 방법에 관한 것이다.The present invention relates to a thin film etching method and a method of manufacturing a transistor and a capacitor of a semiconductor device using the same, and in particular, a thin film etching method and a semiconductor device using the same to simplify the patterning process of metal thin film and ferroelectric thin film and improve the electrical characteristics of the device A method of manufacturing a transistor and a capacitor.
강유전체(SrxBi1-xTa2O9; SBT)를 이용한 메모리소자로는 트랜지스터형 강유전체 메모리 및 디램형(DRAM)형 강유전체 메모리소자가 있다. 이론적으로, 트랜지스터형 강유전체 메모리소자는 소자의 셀 크기를 줄일 수 있으며, 일반적인 디램 메모리소자보다 동작전압을 낮출 수 있다. 반면, 디램형 강유전체 메모리소자는 디램 메모리소자와는 달리 불휘발성 메모리소자로 활용할 수 있다. 이러한 메모리소자들을 제조하기 위해서는 강유전체 게이트의 형성 공정 및 강유전체 캐패시터의 형성공정의 재현성이 확보되어야 한다.Memory devices using ferroelectrics (Sr x Bi 1-x Ta 2 O 9 ; SBT) include transistor type ferroelectric memory and DRAM type (DRAM) ferroelectric memory devices. In theory, the transistor type ferroelectric memory device can reduce the cell size of the device, and can lower the operating voltage than the general DRAM memory device. On the other hand, a DRAM ferroelectric memory device may be used as a nonvolatile memory device unlike a DRAM memory device. In order to manufacture such memory devices, reproducibility of the process of forming the ferroelectric gate and the process of forming the ferroelectric capacitor should be ensured.
일반적으로, 트랜지스터는 게이트 산화막과 게이트 전극을 필수 구성 요소로하며, 트랜지스터형 강유전체 메모리소자에서는 SBT 박막이 게이트 산화막의 역할을 하고, Pt 박막이 게이트 전극의 역할을 한다.In general, a transistor includes a gate oxide film and a gate electrode as essential components. In a transistor type ferroelectric memory device, an SBT thin film serves as a gate oxide film and a Pt thin film serves as a gate electrode.
강유전체 박막을 형성하기 위한 소자 제조 공정 중 가장 핵심적인 공정의 하나가 식각공정 기술이다. SBT 강유전체 박막 및 Pt 박막은 기존의 실리콘산화물(SiO2)이나 알루미늄(Al) 박막과는 달리 식각 속도가 느리며, 식각을 위한 식각장치 및 식각 가스에 대한 연구가 부족한 상태이다. Pt 박막은 높은 내식성으로 인하여 식각의 어려움에도 불구하고 강유전체 특성을 향상시키는 장점이 있기 때문에, 트랜지스터형 강유전체 메모리 소자 및 DRAM형 강유전체 소자의 캐패시터의 전극재료로 활용되고 있다.Etching technology is one of the most important processes of the device manufacturing process for forming a ferroelectric thin film. Unlike conventional silicon oxide (SiO 2 ) or aluminum (Al) thin films, SBT ferroelectric thin films and Pt thin films have a slow etching speed and lack of research on etching apparatus and etching gas for etching. Pt thin films are used as electrode materials for capacitors of transistor type ferroelectric memory devices and DRAM type ferroelectric devices because they have the advantage of improving ferroelectric properties despite etching difficulties due to high corrosion resistance.
따라서, 캐패시터 및 게이트소자로서 강유전체 박막을 안정적으로 활용하기 위해서는 강유전체 박막의 식각 특성 및 상부전극의 식각특성을 확보해야 하며, 이를 위하여 Pt 박막 및 SBT 박막 식각시 기술적으로 크게 세 가지의 문제점을 해결해야만 한다.Therefore, in order to stably use the ferroelectric thin film as a capacitor and a gate device, it is necessary to secure the etching characteristics of the ferroelectric thin film and the etching characteristics of the upper electrode. For this purpose, three problems must be largely solved when etching Pt thin film and SBT thin film. do.
첫째는, 식각시 식각 기울기(Etch profile)가 디자인룰(Design Rule)에 맞추어 어느 정도 유지되어야한다. 둘째는, 식각시 식각벽(Fence)이 생기지 않는 공정조건을 찾아야 한다. 셋째는, 식각시 식각찌꺼기(Residue)가 남지 않아야 한다.First, the etching profile must be maintained to some extent in accordance with the design rule during etching. Second, find the process conditions that do not form the fence during etching. Third, no residue should remain during etching.
상기의 조건을 만족할 때 형태적으로 식각이 올바로 이루어졌다고 할 수 있다. 그러나, 게이트의 식각이 어려운 것은 식각으로 인해 식각이 끝나는 지점(Endpoint)을 검출하기가 어렵고, 여러 가지의 공정이 실시될 경우 게이트 바로 아래의 캐리어 채널(Carrier channel)에 손상이 발생되기 쉽다.When the above conditions are satisfied, it can be said that the etching is properly performed. However, since the gate is difficult to etch, it is difficult to detect the end point of the etching due to etching, and when various processes are performed, damage to a carrier channel directly under the gate is likely to occur.
이러한 가운데, Pt 박막을 먼저 식각한 후 SBT 박막을 식각하는 2단계의 식각방법이 일반적인 방법으로 사용되고 있으나, 이는 포토레지스트 마스크 및 금속 마스크를 번갈아 사용하는 이중 공정을 거쳐야 한다. 이로 인하여, 결과적으로 공정 단계가 복잡화되고, 이에 따른 공정상의 오염문제 및 공정의 어려움 등으로 강유전체 박막이 손상을 입을 수 있으며, 공정의 단가도 올라가는 부담이 생기게 된다.Among these, a two-step etching method of etching the Pt thin film first and then etching the SBT thin film is used as a general method, but it must pass through a dual process using alternating photoresist masks and metal masks. As a result, the process steps are complicated, resulting in damage to the ferroelectric thin film due to process contamination problems and process difficulties, resulting in a burden of increasing the cost of the process.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 헬리콘형 플라즈마(Helicon Plasma) 방법을 이용한 식각 공정으로 금속 박막과 강유전체 박막을 한번에 패터닝함으로써, 공정 단계를 단순화하면서 하부층의 손상을 방지하고 식각 찌거기(Residue)가 발생되는 것을 방지하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 박막 식각 방법 및 이를 이용한 반도체 소자의 트랜지스터 및 캐패시터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to pattern the metal thin film and the ferroelectric thin film in one step by using an helicon plasma (Helicon Plasma) method to solve the above problems, to prevent damage to the underlying layer and simplify the etching step (Residue) It is an object of the present invention to provide a thin-film etching method and a method of manufacturing a transistor and a capacitor of a semiconductor device using the same, which can prevent the occurrence of a) and improve process reliability and device electrical characteristics.
도 1은 금속 박막 및 강유전체 박막을 식각하기 위한 헬리콘 플라즈마 식각 장치의 구성도이다.1 is a configuration diagram of a helicon plasma etching apparatus for etching a metal thin film and a ferroelectric thin film.
도 2a 및 도 2b는 본 발명에 따른 박막 식각 방법을 설명하기 위한 소자의 단면도이다.2A and 2B are cross-sectional views of devices for explaining a thin film etching method according to the present invention.
도 3은 Ar과 CF4의 혼합비에 따른 백금 박막과 강유전체 박막의 식각률을 나타내는 특성 그래프이다.3 is a characteristic graph showing the etching rate of the platinum thin film and the ferroelectric thin film according to the mixing ratio of Ar and CF 4 .
도 4는 본 발명의 백금 박막 및 강유전체 박막의 식각 방법에 따라 패터닝된 백금 박막 및 강유전체 박막의 단면 셈 사진이다.4 is a cross-sectional photo of a platinum thin film and a ferroelectric thin film patterned according to the etching method of the platinum thin film and the ferroelectric thin film of the present invention.
도 5a 내지 도 5c는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 단면도이다.5A to 5C are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
101 : 터보 펌프 102: VAT 밸브101: turbo pump 102: VAT valve
103 :RF 바이어스 파워 104: 캐소드(Cathode)103: RF bias power 104: cathode
105 : 영구 자석 106 : RF 소스 파워105: permanent magnet 106: RF source power
201, 501 : 반도체 기판 202, 504 : SBT 박막201 and 501: semiconductor substrates 202 and 504: SBT thin film
203, 505 : 금속 박막 204 : 금속 마스크203, 505: metal thin film 204: metal mask
502 : 소자 분리막 506 : 소오스/드레인502: device isolation layer 506: source / drain
507 : 층간 절연막 508 : 금속 배선507: interlayer insulating film 508: metal wiring
본 발명에 따른 박막 식각 방법은 하부 구조가 형성된 반도체 기판이 제공되는 단계와, SBT 박막, 금속 박막 및 금속 마스크를 순차적으로 형성하는 단계, 및 금속 마스크를 이용한 헬리콘형 플라즈마 식각 방법으로 금속 박막 및 SBT 박막을 한번에 패터닝하는 단계로 이루어지는 것을 특징으로 한다.According to the present invention, the thin film etching method includes the steps of providing a semiconductor substrate having a lower structure, sequentially forming an SBT thin film, a metal thin film, and a metal mask, and using a helicon-type plasma etching method using a metal mask. It is characterized by consisting of the step of patterning the thin film at a time.
본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 반도체 기판 상에 절연층을 형성하는 단계와, 절연층 상부에 SBT 박막, 금속 박막 및 금속 마스크를 순차적으로 형성하는 단계와, 금속 마스크를 이용한 헬리콘형 플라즈마 식각 방법으로 금속 박막 및 SBT 박막을 한번에 패터닝하여 게이트를 형성하는 단계, 및 게이트 양측의 반도체 기판에 소오스/드레인을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A transistor manufacturing method of a semiconductor device according to the present invention comprises the steps of forming an insulating layer on a semiconductor substrate, sequentially forming an SBT thin film, a metal thin film and a metal mask on the insulating layer, and a helicon plasma using a metal mask And forming a gate by patterning the metal thin film and the SBT thin film at once by an etching method, and forming a source / drain on the semiconductor substrates at both sides of the gate.
본 발명에 따른 반도체 소자의 캐패시터 제조 방법은 콘택 플러그를 포함한 하부 구조가 형성된 반도체 기판이 제공되는 단계와, 콘택 플러그를 포함한 하부 구조 상에 금속 박막을 형성하는 단계와, 금속 박막 상부에 SBT 박막을 형성하는 단계와, SBT 박막 상부에 금속 마스크를 형성하는 단계와, 금속 마스크를 이용한 헬리콘형 플라즈마 식각 방법으로 SBT 박막 및 금속 박막을 한번에 패터닝하는 단계, 및 금속 마스크를 제거한 후 소정의 패턴으로 상부 전극용 금속 박막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: providing a semiconductor substrate having a lower structure including a contact plug; forming a metal thin film on the lower structure including the contact plug; Forming a metal mask on the SBT thin film; forming a metal mask on the SBT thin film; patterning the SBT thin film and the metal thin film at once by a helicon plasma etching method using the metal mask; Characterized in that it comprises the step of forming a metal thin film for.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 보다 더 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1은 금속 박막 및 강유전체 박막을 식각하기 위한 헬리콘 플라즈마 식각 장치의 구성도이다.1 is a configuration diagram of a helicon plasma etching apparatus for etching a metal thin film and a ferroelectric thin film.
도 1을 참조하면, 헬리콘 플라즈마 식각 장치는 기본적으로 진공을 만드는 터보펌프(101), 챔버와 펌프를 분리하는 VAT 밸브(102), RF 바이어스 파워(103), 캐소드(104), 영구자석(105), 및 RF 소스 파워(106)로 구성된다.Referring to FIG. 1, the helicon plasma etching apparatus basically includes a turbopump 101 for creating a vacuum, a VAT valve 102 for separating a chamber and a pump, an RF bias power 103, a cathode 104, a permanent magnet ( 105, and RF source power 106.
상기의 헬리콘 플라즈마 식각 장치는 플라즈마를 만들기 위한 이온이나 중성자 등을 헬리콘 방식의 형태로 충돌을 높여 플라즈마 밀도를 높이고자 만든 장치이다. 여기에 식각용 가스로 클로린(Cl2), 알곤(Ar), 카본플로라이드(CF4) 및 산소(O2) 등의 가스를 혼합하여 사용할 수 있다.The helicon plasma etching apparatus is a device made to increase plasma density by increasing collisions of ions or neutrons for making plasma in the form of helicon. As the etching gas, gases such as chlorine (Cl 2 ), argon (Ar), carbon fluoride (CF 4 ) and oxygen (O 2 ) may be mixed and used.
한편, 챔버는 부식성이 강한 가스를 사용하기 때문에 챔버 내부의 부식을 막기 위하여 Al를 산화처리(Anodizing)하였다. 또한, 고밀도 플라즈마 형성을 위해 챔버 주위의 안테나 박스와 함께 설치하였다.On the other hand, since the chamber uses a highly corrosive gas, Al was oxidized to prevent corrosion in the chamber. It was also installed with an antenna box around the chamber for high density plasma formation.
이하, 헬로콘형 플라즈마 방법을 이용한 박막의 식각 방법에 대한 실시예를 설명하기로 한다.Hereinafter, an embodiment of an etching method of a thin film using a hellocon plasma method will be described.
도 2a 및 도 2b는 본 발명에 박막 식각 방법을 설명하기 위한 소자의 단면도이다.2A and 2B are cross-sectional views of devices for explaining a thin film etching method according to the present invention.
도 2a를 참조하면, 소자 분리막, 층간 절연막 또는 플러그 등과 같은 하부 구조(도시되지 않음)가 형성된 반도체 기판(201) 상부에 SBT 박막(202), 금속 박막(203) 및 금속층을 순차적으로 형성한 후, 금속층을 패터닝하여 금속 마스크(204)를 형성한다.Referring to FIG. 2A, an SBT thin film 202, a metal thin film 203, and a metal layer are sequentially formed on a semiconductor substrate 201 on which a lower structure (not shown), such as an isolation layer, an interlayer insulating film, or a plug, is formed. The metal layer is patterned to form a metal mask 204.
상기에서, SBT 박막(202)은 졸-겔(Sol-Gel)용액을 이용한 스핀 코팅(Spin-Coating)방법으로 형성하거나, 유기 금속 열분해방법(Metal Organic Decomposition; MOD)으로 형성한다. 스핀 코팅으로 SBT 박막(202)을 형성할 경우에는, 반도체 기판(201)을 1000 내지 5000rpm으로 회전시키면서 마이크로 피펫으로 졸-겔 용액을 회전하는 반도체 기판(201)의 표면을 코팅한 후 섭씨 200 내지 600의 온도에서 2 내지 10분 동안 반도체 기판(201)의 표면을 건조시킨 다음 섭씨 500 내지 800의 온도에서 산소 분위기로 10 내지 50분간 열처리를 실시하여 SBT 박막(202)을 형성한다. 이때, SBT 박막(202)은 1000 내지 5000Å의 두께로 형성한다.In the above, the SBT thin film 202 is formed by a spin-coating method using a sol-gel solution, or is formed by a metal organic decomposition method (MOD). When forming the SBT thin film 202 by spin coating, after coating the surface of the semiconductor substrate 201 rotating the sol-gel solution with a micro pipette while rotating the semiconductor substrate 201 at 1000 to 5000rpm, and then 200 to Celsius The surface of the semiconductor substrate 201 is dried for 2 to 10 minutes at a temperature of 600 and then heat treated for 10 to 50 minutes in an oxygen atmosphere at a temperature of 500 to 800 degrees Celsius to form the SBT thin film 202. At this time, the SBT thin film 202 is formed to a thickness of 1000 to 5000Å.
SBT 박막(202) 상부의 금속 박막(203)은 백금 박막으로 형성할 수 있으며, 스퍼터링 방법을 통해 500 내지 3000Å의 두께로 형성한다.The metal thin film 203 on the top of the SBT thin film 202 may be formed of a platinum thin film, and is formed to a thickness of 500 to 3000 kPa through a sputtering method.
금속 마스크(204)는 스퍼터링 방법을 통해 1000 내지 8000Å의 두께로 금속층을 형성하고 금속층상부에 포토레지스트 패턴(도시되지 않음)을 약1.2㎛의 두께로 형성한 후, 포토레지스트 패턴을 식각 마스크로 이용한 식각 공정으로 금속층을 패터닝하여 형성한다. 이때, 금속층은 티타늄으로 형성할 수 있다. 이후, 포토레지스트 패턴을 제거한다.The metal mask 204 is formed by sputtering to form a metal layer with a thickness of 1000 to 8000 Å and a photoresist pattern (not shown) is formed on the metal layer to a thickness of about 1.2 μm, and then the photoresist pattern is used as an etching mask. It is formed by patterning a metal layer by an etching process. In this case, the metal layer may be formed of titanium. Thereafter, the photoresist pattern is removed.
도 2b를 참조하면, 금속 마스크를 이용하면서 헬리콘형 플라즈마 방법을 이용한 한번의 식각 공정으로 금속 박막(203)과 강유전체 박막(202)을 모두 패터닝한다. 이후, 금속 마스크(204)를 제거한다.Referring to FIG. 2B, both the metal thin film 203 and the ferroelectric thin film 202 are patterned in one etching process using a helicon plasma method while using a metal mask. The metal mask 204 is then removed.
헬리콘형 플라즈마 방법은 도 1에 도시된 헬리콘 플라즈마 식각 장치에서 실시하며, 공정압력을 1mTorr 내지 10mTorr로 유지하고 500 내지 1200W의 소오스 파워와 300 내지 900V의 백 바이어스(Back bias) 전압을 인가한 상태에서 실시한다.이때, 식각 가스는 Ar과 CF4가 첨가된 혼합 가스를 사용하는데, Ar 가스, Cl2가스 및 O2가스가 혼합된 가스를 식각 가스로 사용할 경우 혼합비를 x:y:z (x=50 내지 70, y=30 내지 40, z=5 내지 15)로 하고, Ar 가스, Cl2가스 및 CF4가스가 혼합된 가스를 식각 가스로 사용할 경우 혼합비를 50:x:y (x=10 내지 20, y=30 내지 40)으로 한다.The helicon plasma method is performed in the helicon plasma etching apparatus shown in FIG. 1, and maintains a process pressure at 1 mTorr to 10 mTorr and applies a source power of 500 to 1200 W and a back bias voltage of 300 to 900 V. In this case, the etching gas uses a mixed gas of Ar and CF 4 added, and when the mixed gas of Ar gas, Cl 2 gas and O 2 gas is used as the etching gas, the mixing ratio is x: y: z ( x = 50 to 70, y = 30 to 40, z = 5 to 15), and when the mixed gas of Ar gas, Cl 2 gas and CF 4 gas is used as an etching gas, the mixing ratio is 50: x: y (x = 10 to 20 and y = 30 to 40).
한편, 헬리콘형 플라즈마 식각 방법을 이용한 식각 공정 시 박막의 식각률은 식각 가스에 첨가된 Ar과 CF4의 혼합비에 따라 좌우된다.Meanwhile, the etching rate of the thin film in the etching process using the helicon plasma etching method depends on the mixing ratio of Ar and CF 4 added to the etching gas.
도 3은 Ar과 CF4의 혼합비에 따른 백금 박막과 강유전체 박막의 식각률을 나타내는 특성 그래프이다.3 is a characteristic graph showing the etching rate of the platinum thin film and the ferroelectric thin film according to the mixing ratio of Ar and CF 4 .
도 3을 참조하면, SBT 박막은 CF4/(Ar+CF4)의 혼합비가 증가함에 따라 식각률이 점차 감소하는 경향을 나타내다 CF4/(Ar+CF4)의 혼합비가 0.5정도 되었을 때 식각률이 36nm/min 정도의 값을 가지며 감소경향이 줄다가 CF4/(Ar+CF4)의 혼합비가 0.6이상이 될 때 다시 감소률이 증가한다. 반면, CF4의 농도가 증가하면서 SBT박막에 대한 Pt의 식각 선택비는 증가한다. 이는 SBT 박막의 식각 속도의 감소가 Pt의 식각 속도의 감소보다 크기 때문이다. 따라서, 식각률에 따라 Ar과 CF4를 적절하게 혼합한 혼합 가스를 식각 가스로 사용한다.Referring to FIG. 3, the SBT thin film shows a tendency that the etching rate gradually decreases as the mixing ratio of CF 4 / (Ar + CF 4 ) increases. When the mixing ratio of CF 4 / (Ar + CF 4 ) is about 0.5, the etching rate It has a value of about 36nm / min and decreases the decreasing tendency, and then decreases again when the mixing ratio of CF 4 / (Ar + CF 4 ) is 0.6 or more. On the other hand, as the concentration of CF 4 increases, the etching selectivity of Pt to the SBT thin film increases. This is because the decrease in the etching rate of the SBT thin film is larger than the decrease in the etching rate of Pt. Therefore, a mixed gas in which Ar and CF 4 are appropriately mixed according to the etching rate is used as the etching gas.
도 4는 상기의 방법에 따라 패터닝된 백금 박막 및 강유전체 박막의 단면 셈사진으로써, 하부층의 손상을 방지하고 식각 찌거기가 발생되는 것을 방지하면서 백금 박막과 강유전체 박막이 한번의 식각 공정으로 패터닝된 상태를 보여주고 있다.4 is a cross-sectional view of the platinum thin film and the ferroelectric thin film patterned according to the above method, and the platinum thin film and the ferroelectric thin film patterned in one etching process while preventing damage to the underlying layer and preventing etching residues. Is showing.
상기에서 서술한 금속 박막 및 강유전체 박막의 식각 방법은 금속 박막을 게이트 전극으로 사용하고 강유전체 박막을 게이트 산화막으로 사용하는 전계효과 트랜지스터의 제조 공정에 적용될 수 있으며, 금속 박막을 상부 전극으로 사용하고 강유전체 박막을 유전체막으로 사용하는 캐패시터의 제조 공정에도 적용될 수 있다.The etching method of the metal thin film and the ferroelectric thin film described above can be applied to the manufacturing process of the field effect transistor using the metal thin film as the gate electrode and the ferroelectric thin film as the gate oxide film, the metal thin film as the upper electrode and the ferroelectric thin film It can also be applied to the manufacturing process of a capacitor using a as a dielectric film.
이하, 본 발명의 박막 식각 방법이 적용된 반도체 소자의 트랜지스터 제조 방법을 설명하면 다음과 같다.Hereinafter, a transistor manufacturing method of a semiconductor device to which the thin film etching method of the present invention is applied will be described.
도 5a 내지 도 5c는 본 발명의 박막 식각 방법을 이용한 MFIS(Metal-Ferroelectric-Insulator-Silicon) 구조의 전계효과 트랜지스터를 설명하기 위한 단면도이다.5A to 5C are cross-sectional views illustrating field effect transistors having a metal-ferroelectric-insulator-silicon (MFIS) structure using the thin film etching method of the present invention.
도 5a를 참조하면, 소자 분리막(502)이 형성된 반도체 기판(501) 상에 절연층(503), SBT 박막(504) 및 금속 박막(505)을 순차적으로 형성한 다음 도 2b에서 설명한 헬리콘형 플라즈마 방법을 이용하여 금속 박막(505) 및 SBT 박막(504)을 패터닝한 후 순차적으로 절연층(503)을 패터닝한다. 이로써, 절연층(503), SBT 박막(504) 및 금속 박막(505)이 순차적으로 적층된 구조의 게이트가 형성된다.Referring to FIG. 5A, the insulating layer 503, the SBT thin film 504, and the metal thin film 505 are sequentially formed on the semiconductor substrate 501 on which the device isolation film 502 is formed, and then the helicon plasma described with reference to FIG. 2B. After the metal thin film 505 and the SBT thin film 504 are patterned using the method, the insulating layer 503 is sequentially patterned. As a result, a gate having a structure in which the insulating layer 503, the SBT thin film 504, and the metal thin film 505 are sequentially stacked is formed.
상기에서, 절연층(503)은 실리콘과의 접합이 우수하고 고온공정에서 실리콘과 강유전체 박막의 반응을 방지할 수 있도록 실리콘 산화물(SiO2)이나 실리콘 질화물(Si3N4)로 형성하며, 이들의 적층 구조로 형성할 수도 있다. 절연층(503)으로 실리콘 산화물(SiO2)을 적용할 경우에는 열 산화(Thermal oxidation) 공정으로, 실리콘 질화물(Si3N4)을 적용할 경우에는 LPCVD(Low Pressure Chemical Vapor Deposition)법으로 제조한다. 또한, CeO2, Ta2O3, Al2O3, ZrO2또는 SrTa2O6같은 일련의 유전체 절연막(Dielectric insulator layer)으로 절연층(503)을 형성할 수도 있다. 절연층(503)은 10 내지 20nm의 두께로 형성되는 것이 바람직하다.In the above, the insulating layer 503 is formed of silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ) to have excellent bonding with silicon and to prevent the reaction between silicon and the ferroelectric thin film in a high temperature process. It can also be formed in a laminated structure. When silicon oxide (SiO 2 ) is applied to the insulating layer 503, thermal oxidation is performed, and when silicon nitride (Si 3 N 4 ) is applied, the low pressure chemical vapor deposition (LPCVD) method is used. do. In addition, the insulating layer 503 may be formed of a series of dielectric insulator layers such as CeO 2 , Ta 2 O 3 , Al 2 O 3 , ZrO 2, or SrTa 2 O 6 . The insulating layer 503 is preferably formed to a thickness of 10 to 20nm.
SBT 박막(504)을 유기금속 열분해방법이나 스핀 코팅 방법으로 형성한다.The SBT thin film 504 is formed by organometallic pyrolysis or spin coating.
게이트의 전극 역할을 하는 금속 박막(505)은 백금(Pt)을 이용하여 금속전극으로 형성할 수 있으며, 이 경우 스퍼터링을 통해 형성한다. 한편, 금속 박막(505)은 IrO2와 같은 산화물 금속전극으로 형성할 수도 있다.The metal thin film 505 serving as an electrode of the gate may be formed of a metal electrode using platinum (Pt), and in this case, is formed through sputtering. The metal thin film 505 may be formed of an oxide metal electrode such as IrO 2 .
한편, 반도체 기판(501)에는 채널 스탑 이온주입이 실시되는데, 채널 스탑 이온주입 공정이나 소자 분리막 형성 공정과 같은 세부 공정은 통상적으로 실시되는 공정이므로 서술을 생략하기로 한다.Meanwhile, the channel stop ion implantation is performed on the semiconductor substrate 501. Detailed processes such as the channel stop ion implantation process and the device isolation film forming process are commonly performed, and thus description thereof will be omitted.
도 5b를 참조하면, 게이트 양측의 반도체 기판(501)에 소오스/드레인(506)을 형성한다.Referring to FIG. 5B, a source / drain 506 is formed on the semiconductor substrate 501 on both sides of the gate.
소오스/드레인(506)은 저농도 이온 주입을 먼저 실시하고 게이트의 측벽에 게이트 스페이서(도시되지 않음)를 형성한 후 고농도 이온주입을 실시하여LDD(Lightly Doped Drain) 구조로 형성할 수도 있다.The source / drain 506 may be formed in a lightly doped drain (LDD) structure by first performing low concentration ion implantation, forming a gate spacer (not shown) on the sidewall of the gate, and then performing high concentration ion implantation.
이로써, MFIS(Metal-Ferroelectric-Insulator-Silicon) 구조의 전계효과 트랜지스터가 제조된다.As a result, a field effect transistor having a metal-ferroelectric-insulator-silicon (MFIS) structure is manufactured.
도 5c를 참조하면, 전체 상부에 층간 절연막(507)을 형성하고 금속 박막(505) 및 소오스/드레인(506)이 노출되도록 층간 절연막(507)에 홀을 형성한 후, 홀에 전도성 물질을 매립하여 금속 배선(508)을 형성한다. 이때, 층간 절연막(507)은 실리콘 산화막이나 실리콘 질화막을 화학기상 증착법으로 증착하여 형성한다.Referring to FIG. 5C, an interlayer insulating film 507 is formed over the entire surface, and holes are formed in the interlayer insulating film 507 so that the metal thin film 505 and the source / drain 506 are exposed, and then a conductive material is filled in the holes. The metal wiring 508 is formed. At this time, the interlayer insulating film 507 is formed by depositing a silicon oxide film or a silicon nitride film by chemical vapor deposition.
한편, 트랜지스터뿐만 아니라, 캐패시터를 제조하는 과정에서도 본 발명에 따른 박막 식각 방법을 이용할 수 있다.Meanwhile, the thin film etching method according to the present invention may be used not only in the transistor but also in the process of manufacturing the capacitor.
즉, 콘택 플러그를 포함한 하부 구조가 형성된 반도체 기판 상에 하부 전극용 금속 박막 및 SBT 박막을 순차적으로 형성한 후 상기에서 서술한 헬리콘형 플라즈마 방법을 이용한 식각 공정으로 SBT 박막 및 금속 박막을 한번에 패터닝한 다음 상부에 상부 전극용 금속 박막을 형성함으로써, 본 발명에 따른 금속 박막 및 강유전체 박막의 식각 방법을 이용하여 캐패시터를 제조할 수 있다.That is, the metal thin film and the SBT thin film for the lower electrode are sequentially formed on the semiconductor substrate on which the lower structure including the contact plug is formed, and then the SBT thin film and the metal thin film are patterned at one time by an etching process using the helicon plasma method described above. Next, by forming a metal thin film for the upper electrode on the upper portion, it is possible to manufacture a capacitor using the etching method of the metal thin film and the ferroelectric thin film according to the present invention.
상기와 같이, 본 발명에 따른 박막 식각 방법은 MFIS 구조의 전계효과 트랜지스터 및 캐패시터의 제조 방법에 적용이 가능할 뿐만 아니라, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 밝힌다.As described above, the thin film etching method according to the present invention is not only applicable to the method of manufacturing the field effect transistor and the capacitor of the MFIS structure, but the above-described embodiment is for the purpose of description and not of limitation.
상술한 바와 같이, 본 발명은 금속 박막과 강유전체 박막인 SBT 박막을 한번의 식각 공정으로 동시에 패터닝하면서 안정된 구조를 얻을 수 있고, 공정을 단순화하여 단일 공정이 가능하며 특성향상 및 공정단가 절감효과를 거둘 수 있다.As described above, the present invention can obtain a stable structure while simultaneously patterning the metal thin film and the ferroelectric thin film SBT thin film at the same time in one etching process, a single process is possible by simplifying the process, and the characteristics and the cost reduction of the process Can be.
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