KR100349693B1 - Method for forming ferroelectric capacitor - Google Patents
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- KR100349693B1 KR100349693B1 KR1019990063755A KR19990063755A KR100349693B1 KR 100349693 B1 KR100349693 B1 KR 100349693B1 KR 1019990063755 A KR1019990063755 A KR 1019990063755A KR 19990063755 A KR19990063755 A KR 19990063755A KR 100349693 B1 KR100349693 B1 KR 100349693B1
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- H—ELECTRICITY
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Abstract
강유전 박막의 누설전류특성을 향상시키도록 한 강유전체 캐패시터의 제조 방법에 관한 것으로, 이를 위한 본 발명은 소정공정이 실시된 반도체기판 상부에 제1층간절연막을 형성하는 제 1 단계, 상기 층간절연막 상부에 하부전극, 강유전박막, 상부전극으로 이루어진 강유전캐패시터를 형성하는 제 2 단계, 상기 상부전극 상부에 제2층간절연막을 형성하고 플라즈마를 이용한 상기 층간절연막의 선택적 식각으로 상기 상부전극을 노출시키는 콘택홀을 형성하는 제 3 단계, 상기 플라즈마로 인한 상기 강유전박막의 열화를 회복시키도록 상기 노출된 상부전극과 강유전박막의 계면에 650℃∼850℃의 고온에서 1차 열처리하는 제 4 단계, 상기 강유전박막과 상부전극의 계면에 존재하는 결함을 제거하도록 상기 열처리 온도를 400℃∼500℃로 감소시키면서 2차 열처리하는 제 5 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a ferroelectric capacitor to improve leakage current characteristics of a ferroelectric thin film. The present invention provides a first step of forming a first interlayer insulating film on a semiconductor substrate subjected to a predetermined process, and on the interlayer insulating film. Forming a ferroelectric capacitor including a lower electrode, a ferroelectric thin film, and an upper electrode; forming a second interlayer insulating film on the upper electrode and exposing the upper electrode by selective etching of the interlayer insulating film using plasma; The third step of forming, the fourth step of the first heat treatment at the high temperature of 650 ℃ to 850 ℃ at the interface between the exposed upper electrode and the ferroelectric thin film to recover the degradation of the ferroelectric thin film due to the plasma, the ferroelectric thin film and While reducing the heat treatment temperature to 400 ℃ to 500 ℃ to remove the defects present in the interface of the upper electrode 2 It comprises a fifth step of heat treatment.
Description
본 발명은 비휘발성 메모리 소자의 제조 방법에 관한 것으로, 특히 SBT, SBTN 강유전체 캐패시터의 강유전특성(Ferroelectric property) 및 누설전류특성 (Leakage current)을 향상시키도록 한 강유전체 캐패시터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a ferroelectric capacitor designed to improve ferroelectric properties and leakage current of SBT and SBTN ferroelectric capacitors.
일반적으로 강유전체 메모리(Ferroelectric RAM;이하 'FeRAM')의 축전물질로서 강유전체 박막을 이용하는데, 이러한 강유전체 박막은 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다.Generally, a ferroelectric thin film is used as a storage material of a ferroelectric RAM ('FeRAM'). The ferroelectric thin film has a dielectric constant of several hundreds to thousands at room temperature and has two stable remnant polarization states. By thinning it, applications to nonvolatile memory devices have been realized.
강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 "1"과 "0"을 저장하는 히스테리시스 (Hysterisis) 특성을 이용한다.Non-volatile memory devices using ferroelectric thin films store the digital signals "1" and "0" by controlling the direction of polarization in the direction of the applied electric field and inputting a signal, and the residual polarization remaining when the electric field is removed. It takes advantage of the hysterisis characteristic.
그리고 강유전체 메모리(FeRAM)에서 캐패시터의 강유전체 물질로서 PZT, SrxBi2+yTa2O9(이하 SBT), SrxBi2+y(TaiNbj)2O9(이하 'SBTN') 등의 페로브스카이트 (perovskite) 구조를 갖는 강유전체를 사용하는 경우, 통상적으로 Pt, Ir, Ru, Pt 합금 등의 금속으로 상하부전극을 형성한다. 특히, SBT,SBTN와 같은 강유전체 박막을 적용하기 위한 연구가 활발히 진행되고 있다.In the ferroelectric memory (FeRAM), as the ferroelectric material of the capacitor, PZT, Sr x Bi 2 + y Ta 2 O 9 (hereinafter SBT), Sr x Bi 2 + y (Ta i Nb j ) 2 O 9 (hereinafter 'SBTN') In the case of using a ferroelectric having a perovskite structure, such as, the upper and lower electrodes are usually formed of a metal such as Pt, Ir, Ru, or Pt alloy. In particular, research is being actively conducted to apply ferroelectric thin films such as SBT and SBTN.
이러한 상하부전극의 패터닝작업과 식각공정을 통해 메탈-강유전막-메탈 (Metal Ferroelectric Metal; MFM)구조의 캐패시터 형성하고, 상기 캐패시터의상부전극을 포함한 전면에 층간절연막으로서 BPSG(Boro Phospho Silicate Glass)막을 증착하고 평탄화 및 BPSG막 식각을 통해 금속배선과의 콘택홀을 형성한다.Through the patterning and etching process of the upper and lower electrodes, a capacitor having a metal ferroelectric metal (MFM) structure is formed, and a BPSG (Boro Phospho Silicate Glass) film is formed on the entire surface including the upper electrode of the capacitor as an interlayer insulating film. Depositing and forming contact holes with the metallization through planarization and BPSG film etching.
이 때 상기 SBT,SBTN 강유전체 캐패시터는 콘택홀 형성 과정에서 플라즈마에 의한 물리적, 전기적 열화가 발생된다. 이와 같은 플라즈마로 인한 열화는 후속으로 700℃ 이상의 산소열처리가 수반될 경우 모두 제거되지만, SBT,SBTN의 페로브스카이트(Perovskite) 구조를 이루는 비스무스(Bi)는 상하부전극으로 확산되어 캐패시터의 내부에 결함(Defect)을 형성시킨다. 또한 상부전극인 백금(Pt)전극과 국부적으로 반응이 일어나 캐패시터 계면에 BiPt 계열의 물질을 형성시켜 일함수(Work function)를 크게 낮추어 SBT, SBTN 강유전막의 누설전류를 증가시키고 브레이크다운전압(Breakdown voltage)을 낮아지게 한다.At this time, the SBT, SBTN ferroelectric capacitors are physically and electrically deteriorated by plasma during the formation of contact holes. Such deterioration due to the plasma is all removed when subsequent oxygen heat treatment of 700 ℃ or more, but bismuth (Bi) forming the perovskite structure of SBT, SBTN is diffused to the upper and lower electrodes to the inside of the capacitor Defect is formed. In addition, it reacts locally with the upper electrode, platinum (Pt), to form BiPt-based materials at the capacitor interface, greatly reducing the work function, increasing the leakage current of SBT and SBTN ferroelectric films, and breaking down voltage. Lower).
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 2 단계 열처리를 이용하여 SBT, SBTN 강유전체막의 누설전류 특성을 향상시키는데 적합한 강유전체 캐패시터의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a ferroelectric capacitor suitable for improving leakage current characteristics of SBT and SBTN ferroelectric films using two-step heat treatment.
도 1 내지 도 6 은 본 발명의 실시예에 따른 강유전체 캐패시터의 제조 방법을 나타낸 도면.1 to 6 illustrate a method of manufacturing a ferroelectric capacitor according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체 기판 11 : 소자격리층10 semiconductor substrate 11 device isolation layer
12 : 불순물접합층 13 : 제1층간절연막12 impurity bonding layer 13 first interlayer insulating film
14a : 티타늄확산방지막 15a : 하부전극14a: titanium diffusion barrier 15a: lower electrode
16a : 강유전막 17 : 상부전극16a: ferroelectric film 17: upper electrode
18 : 제2층간절연막 19 : 콘택홀18: second interlayer insulating film 19: contact hole
20 : 금속배선20: metal wiring
상기의 목적을 달성하기 위한 본 발명의 강유전체 캐패시터의 제조 방법은 소정공정이 실시된 반도체기판 상부에 제1층간절연막을 형성하는 제 1 단계, 상기 제1층간절연막 상부에 하부전극, 강유전박막, 상부전극으로 이루어진 강유전캐패시터를 형성하는 제 2 단계, 상기 상부전극을 포함한 전면에 제2층간절연막을 형성하는 제 3 단계, 상기 제2층간절연막을 플라즈마를 이용하여 선택적으로 식각하여 상기 상부전극의 소정 표면을 노출시키는 금속배선용 콘택홀을 형성하는 제 4 단계, 상기 플라즈마로 인한 상기 강유전박막의 열화를 회복시키도록 상기 노출된 상부전극과 강유전박막의 계면에 650℃∼850℃의 고온에서 1차 열처리하는 제 5 단계, 및 상기 강유전박막과 상부전극의 계면에 존재하는 결함을 제거하도록 상기 열처리 온도를 400℃∼500℃로 감소시키면서 2차 열처리하는 제 6 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing the ferroelectric capacitor of the present invention for achieving the above object is a first step of forming a first interlayer insulating film on a semiconductor substrate subjected to a predetermined process, a lower electrode, a ferroelectric thin film, an upper portion on the first interlayer insulating film A second step of forming a ferroelectric capacitor made of an electrode, a third step of forming a second interlayer insulating film on the front surface including the upper electrode, and selectively etching the second interlayer insulating film using a plasma to form a predetermined surface of the upper electrode A fourth step of forming a contact hole for metal wiring exposing the first and second heat treatments, at a high temperature of 650 ° C. to 850 ° C. at an interface between the exposed upper electrode and the ferroelectric thin film so as to recover deterioration of the ferroelectric thin film due to the plasma. In the fifth step, the heat treatment temperature is 400 ° C. to 500 ° C. to remove defects existing at the interface between the ferroelectric thin film and the upper electrode. While reducing the yirueojim characterized by a sixth step of heat-treating the second.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1 에 도시된 바와 같이, 소자격리층(11)과 불순물접합층(12)이 형성된 반도체기판(10) 상부에 제1층간절연막(13)을 형성하고 평탄화한다. 이어 상기 제1층간절연막(13) 상에 하부전극접착층(Bottom electrode adhesion layer)으로 티타늄 (Ti)을 증착하고 후속 강유전체막의 열처리 공정에서 티타늄의 확산을 억제하기 위해 상기 티타늄을 산화시키어 티타늄산화막(TiOx)(14)을 형성한다.As shown in FIG. 1, the first interlayer insulating film 13 is formed and planarized on the semiconductor substrate 10 on which the device isolation layer 11 and the impurity junction layer 12 are formed. Subsequently, titanium (Ti) is deposited on the first interlayer insulating layer 13 as a bottom electrode adhesion layer, and the titanium is oxidized to suppress diffusion of titanium in a subsequent heat treatment of the ferroelectric film. x ) 14.
도 2에 도시된 바와 같이, 상기 티타늄산화막(14) 상부에 강유전체 캐패시터의 하부전극물질인 백금(Pt)막(15)을 증착하고, 상기 백금막(15) 상부에 SBT(SBTN) 강유전체 박막(16)을 형성한다.As shown in FIG. 2, a platinum (Pt) film 15, which is a lower electrode material of a ferroelectric capacitor, is deposited on the titanium oxide film 14, and an SBT (SBTN) ferroelectric thin film () is formed on the platinum film 15. 16).
여기서 상기 SBT(SBTN) 강유전체 박막(16)은 스핀온(Spin-on)방법, 스퍼터링법 (Sputtering)등의 물리적증착법(Physical Vapor Deposition; 이하 'PVD' ), 유기금속화학기상증착법(Metal Organic CVD; MOCVD), 플라즈마 유기금속화학기상증착법 (Plasma-Ehanced MOCVD) 또는 LSMCD(Liquid Source Mist Chemical Deposition)중 어느 하나를 이용하여 형성된다. 특히 PVD를 이용할 경우 강유전체막의 조성을 유지하기 위해 상온에서 증착하고 급속열처리와 후속 열처리로 결정립 성장을 이룬다. 또한 플라즈마 유기금속화학기상증착을 이용할 경우, 5mTorr∼50Torr의 증착압력과 400∼700℃ 온도에서 이루어진다.Wherein the SBT (SBTN) ferroelectric thin film 16 is a physical vapor deposition (PVD), such as spin-on (Spin-on), sputtering (Sputtering), metal organic chemical vapor deposition (Metal Organic CVD) MOCVD), Plasma-Ehanced MOCVD, or Liquid Source Mist Chemical Deposition (LSMCD). In particular, when PVD is used, grain growth is achieved by depositing at room temperature to maintain the composition of the ferroelectric film and by rapid heat treatment and subsequent heat treatment. In addition, in the case of using the plasma organometallic chemical vapor deposition, the deposition pressure is 5mTorr to 50Torr and 400 to 700 ° C.
그리고 상기 스핀온 방법으로 SBT(SBTN) 강유전체막을 형성할 때 액상소오스 (Liquid source)를 사용하며 Sr,Bi,Ta,Nb등 출발 금속 분말을 용해시킬 때, 혼합용액으로 옥테인(Octane)을 사용한다. 이어 상기 옥테인으로 형성된 액상소오스에 함유된 Sr,Bi,Ta,Nb 금속물질의 안정제로 n-부틸아세테이트(n-butyl acetate)를 사용한다.When the SBT (SBTN) ferroelectric layer is formed by the spin-on method, a liquid source is used, and when dissolving starting metal powders such as Sr, Bi, Ta, and Nb, octane is used as a mixed solution. do. Subsequently, n-butyl acetate (n-butyl acetate) is used as a stabilizer of the Sr, Bi, Ta, and Nb metal materials contained in the liquid source formed of the octane.
이처럼 형성된 SBT, SBTN 강유전체막의 액상소오스의 비스무스(Bi)의 조성비는 2.05∼2.5%이고, 스트론튬(Sr)의 조성비는 0.7∼1.0%이다.The composition ratio of bismuth (Bi) of the liquid source of the SBT and SBTN ferroelectric films thus formed is 2.05 to 2.5%, and the composition ratio of strontium (Sr) is 0.7 to 1.0%.
상기의 방법들을 이용하여 특히 SBTN 강유전체막을 형성할 때 Nb 의 도핑농도는 20∼30% 원자농도(Atomic concentration) 한계를 갖는다.The doping concentration of Nb has a 20 to 30% atomic concentration limit, particularly when forming the SBTN ferroelectric film using the above methods.
다음으로, 강유전체 물질막의 핵 형성을 위하여 30 torr∼150 torr 의 저압, 670 ℃∼800 ℃ 온도 범위의 O2와 N2의 혼합가스, O2또는 N2O 가스 분위기에서 급속열처리(RTA)를 실시한다. 이때, 급속열처리의 승온속도(ramp-up rate)는 80℃/초 ∼300℃/초가 되도록 한다.Next, in order to nucleate the ferroelectric material film, rapid thermal treatment (RTA) is carried out in a low pressure of 30 torr to 150 torr, a mixed gas of O 2 and N 2 in a temperature range of 670 ° C. to 800 ° C., and an O 2 or N 2 O gas atmosphere. Conduct. At this time, the ramp-up rate of the rapid heat treatment is 80 ° C./sec to 300 ° C./sec.
이어서, 결정립 성장을 위한 후속 로(furnace) 열처리를 700 ℃ 내지 850 ℃온도 범위에서 O2와 N2의 혼합가스, O2또는 N2O 가스 분위기에서 실시하여 도3에 도시한 바와 같이 SBT(SBTN) 강유전체 박막(16)을 형성한다.Subsequently, a subsequent furnace heat treatment for grain growth is carried out in a mixed gas of O 2 and N 2 , O 2 or N 2 O gas atmosphere at a temperature range of 700 ° C. to 850 ° C., as shown in FIG. 3. SBTN) ferroelectric thin film 16 is formed.
도 3에 도시된 바와 같이, 상기 SBT(SBTN)강유전체 박막(16), 백금막(15) 그리고 티타늄산화막(14)을 선택적으로 패터닝 및 식각하여 강유전체 캐패시터의 강유전막(16a), 하부전극(15a) 및 티타늄확산방지막(14a)을 형성한다. 이어 물리적기상증착(PVD) 또는 화학적기상증착(CVD) 방식을 이용하여 강유전막(16a) 상에 상부전극물질을 증착하고 패터닝 및 식각하여 강유전체 캐패시터의 상부전극(17)을 형성한다. 이처럼 상부전극(17), 강유전막(16a), 하부전극(15a) 및 티타늄확산방지막 (14a)으로 이루어지는 MFM(Metal Ferroelectric Metal) 구조의 강유전체 캐패시터를 형성한다.As shown in FIG. 3, the SBT (SBTN) ferroelectric thin film 16, the platinum film 15, and the titanium oxide film 14 are selectively patterned and etched to selectively ferroelectric film 16a and lower electrode 15a of the ferroelectric capacitor. ) And a titanium diffusion barrier 14a. Subsequently, the upper electrode material is deposited, patterned and etched on the ferroelectric film 16a by using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form the upper electrode 17 of the ferroelectric capacitor. As such, a ferroelectric capacitor having a metal ferroelectric metal (MFM) structure including an upper electrode 17, a ferroelectric film 16a, a lower electrode 15a, and a titanium diffusion barrier 14a is formed.
도 4 에 도시된 바와 같이, 상기 상부전극(17)을 포함한 전면에 제2층간절연막(18)으로서 BPSG막을 형성한 다음, 제2층간절연막(18)을 선택적으로 식각하여 캐패시터의 상부전극(17)을 노출시키고 제2층간절연막(18) 및 제1층간절연막(13)을 선택적으로 식각하여 불순물접합층(12)을 노출시키는 콘택홀(19)을 형성한다.As shown in FIG. 4, a BPSG film is formed as the second interlayer insulating film 18 on the entire surface including the upper electrode 17, and then the second interlayer insulating film 18 is selectively etched to form the upper electrode 17 of the capacitor. ) And the second interlayer insulating film 18 and the first interlayer insulating film 13 are selectively etched to form a contact hole 19 exposing the impurity bonding layer 12.
이 때 상기 제2층간절연막(18)을 식각할 때 플라즈마를 이용하며, 이러한 플라즈마 식각으로 인해 상기 강유전막(16a)은 전기적, 물리적 손실이 발생하여 전기적으로 열화된다.At this time, a plasma is used to etch the second interlayer dielectric layer 18. The plasma etch causes the ferroelectric layer 16a to be electrically deteriorated due to electrical and physical loss.
이러한 강유전막(16a)의 전기적 열화를 회복하기 위한 회복열처리공정을 2단계로 실시한다. 도 5에 도시된 바와 같이, 상기 노출된 상부전극(17)과 강유전막(16a)의 계면에 650∼850℃의 온도와 산소분위기에서 O2,N2O 또는 O2+O3혼합가스를 이용한 1차 열처리를 실시하고, 이어 400∼500℃의 저온 환원분위기에서 N2,Ar 또는 N2+O2혼합가스를 이용한 2차 열처리를 실시하는데, 상기 N2와 O2의 혼합가스에서 상기 O2의 조성비는 최고 10%이하를 유지한다. 이처럼 상기 1차 열처리에서는 강유전막(16a)을 산화시키고, 2차 열처리에서는 가스비를 조절하며 진행한다.A recovery heat treatment process for recovering the electrical deterioration of the ferroelectric film 16a is performed in two steps. As shown in FIG. 5, O 2 , N 2 O or O 2 + O 3 mixed gas is mixed at an interface between the exposed upper electrode 17 and the ferroelectric film 16a at an temperature of 650 to 850 ° C. and an oxygen atmosphere. The first heat treatment is performed, followed by a second heat treatment using N 2 , Ar or N 2 + O 2 mixed gas in a low temperature reducing atmosphere at 400 to 500 ° C., wherein the mixed gas of N 2 and O 2 is used. The composition ratio of O 2 is kept up to 10%. As described above, the ferroelectric film 16a is oxidized in the first heat treatment, and the gas ratio is controlled in the second heat treatment.
이 때 상기 1차 열처리는 플라즈마로 인한 강유전막(16a)의 손실을 완전히 제거하는 공정으로 고온(650∼850℃)의 산소분위기에서 열처리를 수반하여 전기적으로 열화된 강유전막(16a)을 회복시킨다. 그리고 상기 2차 열처리는 1차 열처리 후, 점차적으로 온도를 감소시켜 저온(400∼500℃)의 환원분위기에서 수반되어 SBT 강유전막(16a)과 상부전극(17)의 계면에 존재하는 비스무스(Bi) 확산에 의한 결함을 감소시킨다.At this time, the primary heat treatment is a process of completely eliminating the loss of the ferroelectric film 16a due to the plasma to recover the electrically deteriorated ferroelectric film 16a with heat treatment in an oxygen atmosphere at a high temperature (650 to 850 ° C.). . The secondary heat treatment gradually decreases the temperature after the first heat treatment, and is accompanied by a reducing atmosphere at a low temperature (400 to 500 ° C.) to be present at the interface between the SBT ferroelectric film 16a and the upper electrode 17. Reduce defects caused by diffusion.
또한 BiPt계열의 물질이 상부전극(17) 및 하부전극(15a)의 결정립 성장에 의해 전극 표면으로 확산되거나 결정립계에 존재하지만, 인접한 결정립계와의 성장 및 소멸에 의해 감소되므로 강유전막(16a)과 상부전극(17)의 일함수(Work function)가 증가되어 누설전류 특성을 향상시킨다.In addition, the BiPt-based material diffuses to the surface of the electrode due to grain growth of the upper electrode 17 and the lower electrode 15a or exists at the grain boundary, but is reduced by growth and annihilation with adjacent grain boundaries. The work function of the electrode 17 is increased to improve leakage current characteristics.
도 6에 도시된 바와 같이, 상기와 같이 1,2 차 열처리한 후, 콘택홀(19)을 포함한 전면에 금속물질을 증착하고 패터닝 및 식각하여 상기 불순물접합층(12)과 강유전체 캐패시터의 상부전극(17)을 전기적으로 연결하는 금속배선(20)을 형성한다.As shown in FIG. 6, after the first and second heat treatments as described above, a metal material is deposited on the entire surface including the contact hole 19, patterned, and etched to form an upper electrode of the impurity bonding layer 12 and the ferroelectric capacitor. Metal wiring 20 for electrically connecting 17 is formed.
이와 같이 본 발명에서는 안정하고 치밀한 SBT(SBTN) 강유전박막을 형성하기 위해 강유전박막 형성 후, 핵 생성을 위한 급속열처리(RTA) 공정과 결정립 성장을 위한 노열처리 공정을 진행하고, 특히 콘택식각 공정에서 발생되는 강유전박막의 플라즈마 손실을 회복시키기 위해 1,2 차 열처리 공정을 실시하므로써 전기적 특성이 우수한 강유전체 캐패시터를 형성한다.Thus, in the present invention, after the formation of the ferroelectric thin film to form a stable and dense SBT (SBTN) ferroelectric thin film, the rapid thermal treatment (RTA) process for nucleation and the heat treatment process for grain growth, in particular in the contact etching process In order to recover the plasma loss of the ferroelectric thin film generated, the first and second heat treatment processes are performed to form ferroelectric capacitors having excellent electrical characteristics.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 SBT(SBTN) 강유전체 캐패시터의 제조 방법은 고온 산소분위기에서 1차 열처리하고, 저온 환원분위기에서 2 차 열처리하므로써 강유전체막의 누설전류특성을 향상시킬 수 있는 효과가 있다.The method of manufacturing the SBT (SBTN) ferroelectric capacitor of the present invention as described above has the effect of improving the leakage current characteristics of the ferroelectric film by primary heat treatment in a high temperature oxygen atmosphere, secondary heat treatment in a low temperature reducing atmosphere.
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| KR19980037961A (en) * | 1996-11-22 | 1998-08-05 | 김광호 | Capacitor Manufacturing Method for Semiconductor Devices |
| JPH10261767A (en) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH1120095A (en) * | 1997-07-07 | 1999-01-26 | Bridgestone Corp | Electronic device sealing film |
| JPH11220095A (en) * | 1998-01-30 | 1999-08-10 | Sony Corp | Manufacture of dielectric capacitor |
| KR19990075997A (en) * | 1998-03-26 | 1999-10-15 | 윤종용 | Method of manufacturing capacitor of semiconductor device having high dielectric constant dielectric film |
| KR19990076228A (en) * | 1998-03-30 | 1999-10-15 | 윤종용 | Semiconductor device and its manufacturing method |
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| JPH10261767A (en) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH1120095A (en) * | 1997-07-07 | 1999-01-26 | Bridgestone Corp | Electronic device sealing film |
| JPH11220095A (en) * | 1998-01-30 | 1999-08-10 | Sony Corp | Manufacture of dielectric capacitor |
| KR19990075997A (en) * | 1998-03-26 | 1999-10-15 | 윤종용 | Method of manufacturing capacitor of semiconductor device having high dielectric constant dielectric film |
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