KR100333662B1 - Method for forming ferroelectric capacitor - Google Patents
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- KR100333662B1 KR100333662B1 KR1019990024997A KR19990024997A KR100333662B1 KR 100333662 B1 KR100333662 B1 KR 100333662B1 KR 1019990024997 A KR1019990024997 A KR 1019990024997A KR 19990024997 A KR19990024997 A KR 19990024997A KR 100333662 B1 KR100333662 B1 KR 100333662B1
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000003990 capacitor Substances 0.000 title claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 241001122315 Polites Species 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000007704 transition Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 50
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 230000006911 nucleation Effects 0.000 description 6
- 238000010899 nucleation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000010287 polarization Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- DKPFZGUDAPQIHT-UHFFFAOYSA-N butyl acetate Chemical compound CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- TVMXDCGIABBOFY-UHFFFAOYSA-N octane Chemical compound CCCCCCCC TVMXDCGIABBOFY-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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Abstract
본 발명은 강유전체 막 구조를 치밀화시킬 수 있으며 강유전 특성을 보다 향상시킬 수 있는 강유전체 캐패시터 제조 방법에 관한 것으로, 페롭스카이트 핵 형성 공정인 급속열처리를 종래의 상압 방식에서 상압보다 낮은 저압방식으로 전환하는데 특징이 있다. SBT, SBTN 핵의 플루라이트에서 페롭스카이트로의 전이는 저압 상태, 700 ℃ RTA 열공정으로 충분히 이루어진다. 또한, SBT, SBTN막은 급속열처리 과정 중 산화반응에 의해 체적 증가가 제한되므로 극히 평탄하고 치밀한 표면 상태를 갖게된다.The present invention relates to a method of manufacturing a ferroelectric capacitor capable of densifying a ferroelectric film structure and further improving ferroelectric properties. There is a characteristic. The transition from the polite to the perovskite of the SBT and SBTN nuclei is fully accomplished in a low pressure, 700 ° C RTA thermal process. In addition, SBT and SBTN film has an extremely flat and dense surface state because the volume increase is limited by the oxidation reaction during the rapid heat treatment process.
Description
본 발명은 반도체 메모리 소자 제조 방법에 관한 것으로, 특히 강유전체 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a ferroelectric capacitor.
반도체 메모리 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(ferroelectric random access memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.
비휘발성 메모리 소자의 축전물질로는 SrxBi2+yTa2O9(이하 SBT), SrxBi2+y(TaiNbj)2O9(이하 SBTN) 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다.As the storage material of the nonvolatile memory device, Sr x Bi 2 + y Ta 2 O 9 (hereinafter SBT) and Sr x Bi 2 + y (Ta i Nb j ) 2 O 9 (hereinafter SBTN) thin films are mainly used. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices.
강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용한다.Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .
비휘발성 메모리 소자의 캐패시터 유전막으로 SrxBi2+yTa2O9, SrxBi2+y(TaiNbj)2O9등과 같은 페롭스카이트(perovskite) 구조의 강유전체막을 형성하기 위해서는 막 형성 후, 핵 생성을 위한 급속열처리(rapid thermal anneal) 공정과 결정립 성장을 위한 노(furnace) 열처리 공정이 수반되어야 한다.To form a ferroelectric film having a perovskite structure such as Sr x Bi 2 + y Ta 2 O 9 , Sr x Bi 2 + y (Ta i Nb j ) 2 O 9, and the like as a capacitor dielectric film of a nonvolatile memory device After formation, a rapid thermal anneal process for nucleation and a furnace heat treatment process for grain growth must be involved.
핵 생성은 급속열처리 방식으로 725 ℃에서 30 초 동안 상압 산소 분위기에서 실시되며, 결정립 성장을 위한 노 열처리는 750 ℃ 이하의 온도에서 1 시간동안 산소 분위기에서 실시된다. 이와 같이 두 단계의 열처리를 실시하는 것은 초기 유전막의 페롭스카이트 핵 형성에 물리적, 전기적 특성이 의존하기 때문이다. 즉, 낮은 온도에서 핵 생성을 위한 급속열처리를 실시하면 막에 페롭스카이트와 플루라이트(flurite)의 두 구조가 혼재하여 강유전체 성질인 분극 특성이 우수하지 않으며, 높은 온도에서 급속열처리 공정이 진행되면 결정립 성장이 동시에 이루어져 박막이 거칠어지고 다공성(porosity)도 커져 전류 특성이 나쁘다.Nucleation is carried out in an atmospheric oxygen atmosphere for 30 seconds at 725 ℃ by a rapid heat treatment method, the furnace heat treatment for grain growth is carried out in an oxygen atmosphere for 1 hour at a temperature of 750 ℃ or less. This two-step heat treatment is because the physical and electrical properties depend on the perovskite nucleation of the initial dielectric film. In other words, when the rapid heat treatment for nucleation is performed at low temperature, the two structures of perovskite and flurite are mixed in the membrane, so the polarization characteristic of ferroelectric properties is not excellent, and when the rapid heat treatment process is performed at high temperature Grain growth occurs simultaneously, resulting in a rough film and a large porosity, resulting in poor current characteristics.
따라서, 핵 생성을 위한 급속열처리 조건을 보다 안정화시킬 수 있는 강유전체막 형성 방법이 필요한 실정이다.Accordingly, there is a need for a method of forming a ferroelectric film capable of further stabilizing rapid heat treatment conditions for nucleation.
상기와 같은 문제점 및 필요성을 해결하기 위하여 안출된 본 발명은 강유전체 막 구조를 보다 치밀화시킬 수 있으며 강유전 특성을 보다 향상시킬 수 있는 강유전체 캐패시터 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems and necessity is to provide a ferroelectric capacitor manufacturing method that can further densify the ferroelectric film structure and further improve the ferroelectric properties.
도1 내지 도6은 본 발명의 일실시예에 따른 FeRAM 제조 공정 단면도.1 to 6 are cross-sectional views of a FeRAM manufacturing process according to an embodiment of the present invention.
*도면의 주요 부분에 대한 도면부호의 설명** Description of reference numerals for the main parts of the drawings *
15A: 하부전극 16A: 강유전체막 패턴15A: Lower electrode 16A: Ferroelectric film pattern
17: 상부전극17: upper electrode
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 캐패시터의 하부전극을 이룰 제1 전도막을 형성하는 제1 단계; 상기 제1 전도막 상에 강유전체 물질막을 형성하는 제2 단계; 상기 강유전체 물질막의 핵 형성을 위하여, 상압 보다 낮은 압력에서 급속열처리 공정을 실시하는 제3 단계; 상기 강유전체 물질막의 결정립 성장을 위한 열처리를 실시하여 강유전체막을 형성하는 제4 단계; 상기 강유전체막 상에 캐패시터의 상부전극을 이룰 제2 전도막을 형성하는 제5 단계; 및 상기 제2 전도막, 상기 강유전체막, 상기 제1 전도막을 패터닝하여, 상부전극,강유전체막 패턴 및 하부전극을 형성하는 제6 단계를 포함하는 강유전체 캐패시터 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a first conductive film to form a lower electrode of the capacitor on the semiconductor substrate; Forming a ferroelectric material film on the first conductive film; A third step of performing a rapid heat treatment process at a pressure lower than normal pressure to nucleate the ferroelectric material film; A fourth step of forming a ferroelectric film by performing heat treatment for grain growth of the ferroelectric material film; Forming a second conductive film on the ferroelectric film to form an upper electrode of the capacitor; And a sixth step of patterning the second conductive film, the ferroelectric film, and the first conductive film to form an upper electrode, a ferroelectric film pattern, and a lower electrode.
본 발명은 페롭스카이트 핵 형성 공정인 급속열처리(RTA)를 종래의 상압(atmosphere) 방식에서 상압보다 낮은 저압(low pressure) 방식으로 전환하는데 특징이 있다. 즉, SBT, SBTN 핵의 플루라이트에서 페롭스카이트로의 전이는 저압 상태, 700 ℃ RTA 열공정으로 충분히 이루어진다. 또한, SBT, SBTN 강유전체막은 RTA 과정 중 산화반응에 의해 체적 증가가 제한되므로 극히 평탄(smooth)하고 치밀(densify)한 표면 상태를 갖게된다.The present invention is characterized in converting a rapid heat treatment (RTA), a perovskite nucleation process, from a conventional atmospheric pressure method to a low pressure method lower than the normal pressure. That is, the transition from the polite to the perovskite of the SBT and SBTN nuclei is sufficiently performed by a low pressure, 700 ° C. RTA thermal process. In addition, the SBT and SBTN ferroelectric films have a very smooth and densified surface state because the volume increase is limited by the oxidation reaction during the RTA process.
이하, 첨부된 도면 도1 내지 도6을 참조하여 본 발명의 일실시예에 따른 FeRAM 소자 제조 방법을 상세히 설명한다.Hereinafter, a method of manufacturing a FeRAM device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도1에 도시한 바와 같이 트랜지스터 등의 하부 구조 형성이 완료된 반도체 기판(10) 상에 제1 층간절연막(13)을 형성한다. 도면에서 도면부호 '11'은 필드산화막, '12'는 접합영역(junction)을 각각 나타낸다.First, as shown in FIG. 1, a first interlayer insulating film 13 is formed on a semiconductor substrate 10 on which a lower structure such as a transistor is formed. In the drawing, reference numeral '11' denotes a field oxide film and '12' denotes a junction.
다음으로, 제1 층간절연막(13)을 화학적 기계적 연마법(chemical mechanical polishing)으로 연마하고, 제1 층간절연막(13) 상에 하부전극 접착층으로서 Ti막을 형성하고, 후속 강유전체 박막 열처리 공정에서 Ti가 확산되는 것을 억제하기 위하여 Ti막을 산화시켜 도2에 도시한 바와 같이 제1 층간절연막(13) 상에 TiOx막(14)을 형성한다.Next, the first interlayer insulating film 13 is polished by chemical mechanical polishing, a Ti film is formed as a lower electrode adhesive layer on the first interlayer insulating film 13, and in a subsequent ferroelectric thin film heat treatment process, Ti is deposited. In order to suppress diffusion, the Ti film is oxidized to form a TiO x film 14 on the first interlayer insulating film 13 as shown in FIG.
다음으로, TiOx막(14) 상에 하부전극을 이룰 Pt막(15)을 형성한다. 이어서, Pt막(15) 상에 SrxBi2+yTa2O9(SBT), SrxBi2+y(TaiNbj)2O9(SBTN) 등과 같은 강유전체 물질막을 형성한다.Next, a Pt film 15 is formed on the TiO x film 14 to form a lower electrode. Subsequently, a ferroelectric material film such as Sr x Bi 2 + y Ta 2 O 9 (SBT), Sr x Bi 2 + y (Ta i Nb j ) 2 O 9 (SBTN), or the like is formed on the Pt film 15.
이때, 강유전체 물질막은 스핀-온(spin-on), 스퍼터(sputter) 등의 물리기상증착법(physical vapor deposition, PVD), 유기금속화학기상증착법(metal organic chemical vapor deposition, MOCVD), 플라즈마 유기금속화학기상증착법(plasma enhanced metal organic chemical vapor deposition, PE-MOCVD), LSMCD(liquid source misted chemical deposition) 등과 같은 다양한 증착 방법으로 형성한다.In this case, the ferroelectric material film may include spin-on, sputter, physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD), plasma organic metal chemistry. It is formed by various deposition methods such as plasma enhanced metal organic chemical vapor deposition (PE-MOCVD), liquid source misted chemical deposition (LSMCD).
스퍼터 등과 같은 PVD 방식으로 강유전체 물질막을 형성할 때 박막의 조성을 유지하기 위해 상온에서 증착하고, CVD를 이용할 경우 반응 소스로 O2, H2O, N2O, H2O2등을 이용하며, PE-MOCVD를 이용하는 경우는 5 mtorr 내지 50 mtorr 증착압력, 400 ℃ 내지 700 ℃ 조건으로 형성한다.When the ferroelectric material film is formed by a PVD method such as a sputter, it is deposited at room temperature to maintain the composition of the thin film, and when CVD is used, O 2 , H 2 O, N 2 O, H 2 O 2, etc. are used as a reaction source. In the case of using PE-MOCVD, it is formed under conditions of 5 mtorr to 50 mtorr deposition pressure and 400 ° C to 700 ° C.
또한, 스핀-온 방식으로 SBT, SBTN 강유전체 물질막을 형성할 때 액상 소스(liquid source)를 사용하며 Sr, Bi, Ta, Nb 등 출발 금속 분말을 용해 시킬 때 혼합용액으로는 옥탄(octane)을 사용하며, 옥탄으로 형성된 액상 소스에 함유된 Sr, Bi, Ta, Nb 금속 물질의 안정제로 엔-부틸 아세테이트(n-butyl acetate)를 사용한다. SBT, SBTN의 액상 소스에서 Bi의 과잉(excess) 원자비는 2.05 % 내지 2.5 %가 되도록 하고, Sr의 원자비를 0.7 % 내지 1.0 %가 되도록 한다.In addition, a liquid source is used to form an SBT, SBTN ferroelectric material film by spin-on method, and octane is used as a mixed solution when dissolving starting metal powders such as Sr, Bi, Ta, and Nb. In addition, n-butyl acetate is used as a stabilizer of Sr, Bi, Ta, and Nb metal materials contained in a liquid source formed of octane. The excess atomic ratio of Bi in the liquid phase source of SBT and SBTN is 2.05% to 2.5%, and the atomic ratio of Sr is 0.7% to 1.0%.
이와 같이 다양한 증착방식을 이용한 SBTN 강유전체 물질막을 형성할 때 Nb의 도핑농도는 15 at.% 내지 30 at.% 가 되도록 한다.As such, when forming the SBTN ferroelectric material film using various deposition methods, the doping concentration of Nb is set to 15 at.% To 30 at.%.
다음으로, 강유전체 물질막의 핵 형성을 위하여 30 torr 내지 150 torr 의 저압, 670 ℃ 내지 800 ℃ 온도 범위의 O2와 N2의 혼합가스, O2또는 N2O 가스 분위기에서 급속열처리(RTA)를 실시한다. 이때, RTA 승온속도(ramp-up rate)는 80 ℃/sec. 이상이 되도록 한다.Next, in order to nucleate the ferroelectric material film, rapid thermal treatment (RTA) is carried out in a low pressure of 30 torr to 150 torr, a mixed gas of O 2 and N 2 in a temperature range of 670 ° C. to 800 ° C., and an O 2 or N 2 O gas atmosphere. Conduct. At this time, the RTA ramp-up rate is 80 ℃ / sec. Make it ideal.
이어서, 결정립 성장을 위한 후속 노(furnace) 열처리를 700 ℃ 내지 850 ℃ 온도 범위에서 O2와 N2의 혼합가스, O2또는 N2O 가스 분위기에서 실시하여 도3에 도시한 바와 같이 강유전체막(16)을 형성한다.Subsequent furnace heat treatment for grain growth was then carried out in a mixed gas of O 2 and N 2 , O 2 or N 2 O gas atmosphere at a temperature range of 700 ° C. to 850 ° C., as shown in FIG. 3. (16) is formed.
다음으로, 도4에 도시한 바와 같이 PVD 또는 CVD 방식을 이용하여 강유전체막(16) 상에 금속막을 증착하고 패터닝하여 상부전극(17)을 형성한다.Next, as shown in FIG. 4, the upper electrode 17 is formed by depositing and patterning a metal film on the ferroelectric film 16 using PVD or CVD.
다음으로, 강유전체막(16), Pt막(15), TiOx막(14)을 패터닝하여 도5에 도시한 바와 같이 상부전극(17), 강유전체막 패턴(16A), 하부전극(15A) 및 TiOx막 패턴(14A)을 형성함으로써, MFM(metal ferroelectric metal) 구조의 캐패시터를 형성한다.Next, the ferroelectric film 16, the Pt film 15, and the TiO x film 14 are patterned, and as shown in FIG. 5, the upper electrode 17, the ferroelectric film pattern 16A, the lower electrode 15A, and the like. By forming the TiO x film pattern 14A, a capacitor having a metal ferroelectric metal (MFM) structure is formed.
이어서, 캐패시터 절연막(capacitor level dielectric)으로서 SiO2확산방지막(capping oxide)(18)을 형성하고, 확산방지막(18) 상에 제2 층간절연막(19)을 형성한 다음, 제2 층간절연막(19) 및 확산방지막(18)을 선택적으로 식각하여 캐패시터의 상부전극(17)을 노출시키는 제1 콘택홀(C1)을 형성하고, 제2 층간절연막(19), 확산방지막(18) 및 제1 층간절연막(13)을 선택적으로 식각하여 접합영역(12)을 노출시키는 제2 콘택홀(C2)을 형성한다.Subsequently, a SiO 2 diffusion oxide 18 is formed as a capacitor level dielectric, a second interlayer dielectric 19 is formed on the diffusion barrier 18, and then a second interlayer dielectric 19 ) And the diffusion barrier 18 are selectively etched to form a first contact hole C1 exposing the upper electrode 17 of the capacitor, the second interlayer dielectric 19, diffusion barrier 18 and the first interlayer. The insulating layer 13 is selectively etched to form a second contact hole C2 exposing the junction region 12.
다음으로, Ti, TiN으로 이루어지는 금속확산방지막(20) 및 Al 등의 금속막(21)을 차례로 증착한 후, 금속막(21) 및 금속확산방지막(20)을 선택적으로 식각하여 금속배선을 형성한다.Next, the metal diffusion prevention film 20 made of Ti and TiN and the metal film 21 such as Al are sequentially deposited, and then the metal film 21 and the metal diffusion prevention film 20 are selectively etched to form metal wiring. do.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 강유전 특성이 우수하며 막구조가 치밀하고 안정된 표면을 갖는 SBT, SBTN 강유전체막을 형성할 수 있어 안정한 전기적 특성을 확보할 수 있다.According to the present invention, the SBT and SBTN ferroelectric films having excellent ferroelectric characteristics, dense film structure, and stable surface can be formed, thereby ensuring stable electrical characteristics.
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