KR100513796B1 - Capacitor having Bismuth-base ferroelectric layer and method for fabricating the same - Google Patents
Capacitor having Bismuth-base ferroelectric layer and method for fabricating the same Download PDFInfo
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- KR100513796B1 KR100513796B1 KR10-2002-0086265A KR20020086265A KR100513796B1 KR 100513796 B1 KR100513796 B1 KR 100513796B1 KR 20020086265 A KR20020086265 A KR 20020086265A KR 100513796 B1 KR100513796 B1 KR 100513796B1
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- 238000000034 method Methods 0.000 title description 44
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000000576 coating method Methods 0.000 claims abstract description 10
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- 239000013078 crystal Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 6
- 238000011282 treatment Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 230000010287 polarization Effects 0.000 abstract description 18
- 229910052797 bismuth Inorganic materials 0.000 abstract description 8
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 abstract description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 64
- 239000010410 layer Substances 0.000 description 20
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 14
- 239000010409 thin film Substances 0.000 description 14
- 239000010936 titanium Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- 229910052697 platinum Inorganic materials 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
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- 238000010899 nucleation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000007888 film coating Substances 0.000 description 4
- 238000009501 film coating Methods 0.000 description 4
- 239000005416 organic matter Substances 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- ONIKNECPXCLUHT-UHFFFAOYSA-N 2-chlorobenzoyl chloride Chemical compound ClC(=O)C1=CC=CC=C1Cl ONIKNECPXCLUHT-UHFFFAOYSA-N 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000007669 thermal treatment Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- DKPFZGUDAPQIHT-UHFFFAOYSA-N butyl acetate Chemical compound CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 description 2
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910000457 iridium oxide Inorganic materials 0.000 description 2
- 229910052746 lanthanum Inorganic materials 0.000 description 2
- JLRJWBUSTKIQQH-UHFFFAOYSA-K lanthanum(3+);triacetate Chemical compound [La+3].CC([O-])=O.CC([O-])=O.CC([O-])=O JLRJWBUSTKIQQH-UHFFFAOYSA-K 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- JMXKSZRRTHPKDL-UHFFFAOYSA-N titanium ethoxide Chemical compound [Ti+4].CC[O-].CC[O-].CC[O-].CC[O-] JMXKSZRRTHPKDL-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
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- QYIGOGBGVKONDY-UHFFFAOYSA-N 1-(2-bromo-5-chlorophenyl)-3-methylpyrazole Chemical compound N1=C(C)C=CN1C1=CC(Cl)=CC=C1Br QYIGOGBGVKONDY-UHFFFAOYSA-N 0.000 description 1
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical compound COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 description 1
- PPNFILUQDVDXDA-UHFFFAOYSA-K 2-ethylhexanoate;lanthanum(3+) Chemical compound [La+3].CCCCC(CC)C([O-])=O.CCCCC(CC)C([O-])=O.CCCCC(CC)C([O-])=O PPNFILUQDVDXDA-UHFFFAOYSA-K 0.000 description 1
- NJLQUTOLTXWLBV-UHFFFAOYSA-N 2-ethylhexanoic acid titanium Chemical compound [Ti].CCCCC(CC)C(O)=O.CCCCC(CC)C(O)=O.CCCCC(CC)C(O)=O.CCCCC(CC)C(O)=O NJLQUTOLTXWLBV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- NUMHJBONQMZPBW-UHFFFAOYSA-K bis(2-ethylhexanoyloxy)bismuthanyl 2-ethylhexanoate Chemical compound [Bi+3].CCCCC(CC)C([O-])=O.CCCCC(CC)C([O-])=O.CCCCC(CC)C([O-])=O NUMHJBONQMZPBW-UHFFFAOYSA-K 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- TVMXDCGIABBOFY-UHFFFAOYSA-N octane Chemical compound CCCCCCCC TVMXDCGIABBOFY-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- UMJSCPRVCHMLSP-UHFFFAOYSA-N pyridine Natural products COC1=CC=CN=C1 UMJSCPRVCHMLSP-UHFFFAOYSA-N 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- KNPRLIQQQKEOJN-UHFFFAOYSA-N tri(propan-2-yloxy)bismuthane Chemical compound [Bi+3].CC(C)[O-].CC(C)[O-].CC(C)[O-] KNPRLIQQQKEOJN-UHFFFAOYSA-N 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 c축으로 배향이 이루어짐에 따른 분극값 저하를 방지하는데 적합한 비스무스계 강유전체막을 구비하는 캐패시터 및 그 제조 방법을 제공하기 위한 것으로, 본 발명의 캐패시터의 제조 방법은 본 발명의 캐패시터의 제조 방법은 금속막으로 이루어진 하부전극 상에 스퍼터법을 이용하여 상기 하부전극의 결정 방향을 따라 배향되는 BLT 시드층을 증착하는 단계, 상기 BLT 시드층 상에 BLT 강유전체막을 코팅하는 단계, 상기 코팅된 BLT 강유전체막을 고체화시키기 위한 베이크 단계, 상기 고체화된 BLT 강유전체막의 핵성장을 위한 급속열처리 단계, 상기 급속열처리된 BLT 강유전체막 상에 상부전극을 형성하는 단계, 및 상기 급속열처리된 BLT 강유전체막을 결정화시키기 위한 로열처리 단계를 포함한다.The present invention is to provide a capacitor having a bismuth-based ferroelectric film suitable for preventing a decrease in polarization value due to the alignment of the c-axis, and a method of manufacturing the capacitor of the present invention is a method of manufacturing the capacitor of the present invention Depositing a BLT seed layer oriented along a crystal direction of the lower electrode by using a sputtering method on a lower electrode formed of a silver metal film, coating a BLT ferroelectric film on the BLT seed layer, and coating the coated BLT ferroelectric Bake step for solidifying the film, Rapid heat treatment step for nuclear growth of the solidified BLT ferroelectric film, Forming an upper electrode on the fast heat-treated BLT ferroelectric film, and Royal treatment for crystallizing the fast heat-treated BLT ferroelectric film Steps.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 비스무스계 강유전체막을 구비하는 캐패시터 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a capacitor having a bismuth ferroelectric film and a method of manufacturing the same.
반도체 메모리 소자에서 강유전체(ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random AccessMemory) 소자에서 필요한 리프레쉬(refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(ferroelectric random access memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when the power supply is cut off, but also has an operation speed that is comparable to that of conventional DRAMs.
강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 1과 0을 저장하는 원리를 이용하는 것이다.A nonvolatile memory device using a ferroelectric thin film uses a principle of storing digital signals 1 and 0 by controlling the direction of polarization in the direction of an applied electric field, and storing the digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. will be.
FeRAM의 축전물질로는 SrBi2Ta2O9(이하 'SBT'라 약칭함)와 Pb(Zr,Ti)O3 (이하 'PZT'라 약칭함)와 같은 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(nonvolatile) 메모리 소자로의 응용이 실현되고 있다.As the storage material of FeRAM, thin films such as SrBi 2 Ta 2 O 9 (hereinafter abbreviated as 'SBT') and Pb (Zr, Ti) O 3 (hereinafter abbreviated as 'PZT') are mainly used. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices.
한편, SBT의 우수한 신뢰성과 PZT의 낮은 결정화 온도 및 높은 분극 특성 등 각각의 장점을 고루 갖춘 새로운 강유전체 물질로서 BLT(Bi4-xLaxTi3O12 )와 BTO(Bi4Ti3O12)가 있다.On the other hand, the new ferroelectric materials that combine the excellent reliability of SBT, the low crystallization temperature of PZT, and the high polarization characteristics, respectively, are BLT (Bi 4-x La x Ti 3 O 12 ) and BTO (Bi 4 Ti 3 O 12 ). There is.
비스무스계 강유전체막인 BLT, BTO 박막은 강한 비등방성(anisotropy)의 분극 특성을 갖는데, c축으로는 약 4μC/cm2으로 매우 작은 반면에, a축으로는 약 50μC/cm2의 분극값을 갖는다. 따라서, 분극값이 증가된 BLT 또는 BTO 박막을 얻기 위해서는 c축 배향성은 억제하고 a축 배향성은 증가시켜야 한다.BLT and BTO thin films, which are bismuth-based ferroelectric films, have strong anisotropy polarization characteristics, which are very small at about 4 μC / cm 2 on the c-axis, while having a polarization value of about 50 μC / cm 2 on the a-axis. Have Therefore, in order to obtain a BLT or BTO thin film having an increased polarization value, the c-axis orientation should be suppressed and the a-axis orientation should be increased.
도 1은 종래기술에 따른 캐패시터의 제조 방법을 간략히 도시한 공정 흐름도로서, BLT막을 유전막으로 이용하는 캐패시터이다.1 is a process flow diagram briefly illustrating a method of manufacturing a capacitor according to the prior art, which is a capacitor using a BLT film as a dielectric film.
도 1을 참조하면, 종래 캐패시터 제조 과정은, 금속막으로 된 하부전극 형성 과정(S11), BLT막 코팅(coating) 과정(S12), 베이크(bake) 과정(S13), BLT막의 핵성장을 위한 급속열처리(Rapid Thermal Annealing; RTA) 과정(S14) 상부전극 형성 과정(S15), BLT막의 결정화를 위한 로열처리(Furnace Annealing; FA) 과정(S16)으로 구성된다.Referring to FIG. 1, a conventional capacitor manufacturing process includes forming a lower electrode made of a metal film (S11), coating a BLT film (Sating), baking (S13), and nuclear growth of a BLT film. Rapid Thermal Annealing (RTA) process (S14) The upper electrode forming process (S15), and the thermal treatment (Furnace Annealing (FA)) process for crystallization of the BLT film (S16).
도 1에 도시된 바와 같이, 금속막으로 된 하부전극을 형성한 후, 하부전극 상에 BLT막을 코팅하고, 코팅과정(S12)을 통해 초기 액상으로 형성된 BLT 박막이 베이크과정(S13)을 통해 고체화되며, 후속 급속열처리 과정(S14)을 통해 핵생성이 이루어지고, 상부전극 형성과정(S15) 후에 진행하는 로열처리 과정(S16)을 통해 결정화가 이루어진다. As shown in FIG. 1, after forming the lower electrode made of a metal film, the BLT film is coated on the lower electrode, and the BLT thin film formed in the initial liquid phase through the coating process (S12) is solidified through the baking process (S13). The nucleation is performed through the subsequent rapid heat treatment process (S14), and crystallization is performed through the royal heat treatment process (S16) that proceeds after the upper electrode forming process (S15).
그러나, 금속막을 이용하는 하부전극 상에 BLT막을 코팅한 후 로 열처리 과정(S16)을 수행하면 박막 배향성은 대부분 c축으로 이루어지고, a축은 거의 성장하지 않으며, 분극값이 극히 낮아지는 문제가 있다.However, when the BLT film is coated on the lower electrode using the metal film and then the low heat treatment process (S16) is performed, the thin film orientation is mostly made of the c-axis, the a-axis hardly grows, and the polarization value is extremely low.
따라서, 우수한 분극 특성을 가지는 BLT 박막을 형성하기 위해서는 BLT 박막의 분극 방향을 a축 또는 랜덤(random)한 특성을 가지도록 하는 것이 중요하다. 아울러, BTO 박막에서도 배향성은 중요하다.Therefore, in order to form a BLT thin film having excellent polarization characteristics, it is important to have the a-axis or random characteristics in the polarization direction of the BLT thin film. In addition, orientation is important in BTO thin films.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, c축으로 배향이 이루어짐에 따른 분극값 저하를 방지하는데 적합한 비스무스계 강유전체막을 구비하는 캐패시터 및 그 제조 방법을 제공하는데 그 목적이 있다. Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a capacitor having a bismuth-based ferroelectric film suitable for preventing a decrease in the polarization value caused by the alignment of the c-axis, and a method of manufacturing the same. .
삭제delete
상기 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 금속막으로 이루어진 하부전극 상에 스퍼터법을 이용하여 상기 하부전극의 결정 방향을 따라 배향되는 BLT 시드층을 증착하는 단계, 상기 BLT 시드층 상에 BLT 강유전체막을 코팅하는 단계, 상기 코팅된 BLT 강유전체막을 고체화시키기 위한 베이크 단계, 상기 고체화된 BLT 강유전체막의 핵성장을 위한 급속열처리 단계, 상기 급속열처리된 BLT 강유전체막 상에 상부전극을 형성하는 단계, 및 상기 급속열처리된 BLT 강유전체막을 결정화시키기 위한 로열처리 단계를 포함하는 것을 특징으로 한다.The method of manufacturing a capacitor of the present invention for achieving the above object is a step of depositing a BLT seed layer oriented along the crystal direction of the lower electrode by using a sputtering method on a lower electrode made of a metal film, on the BLT seed layer Coating a BLT ferroelectric film on the substrate, baking the solidified BLT ferroelectric film, rapid thermal treatment for nucleation of the solidified BLT ferroelectric film, and forming an upper electrode on the rapid heat-treated BLT ferroelectric film, And a royal treatment step for crystallizing the rapid thermally treated BLT ferroelectric film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 흐름도이다.2 is a process flow diagram illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
도 2에 도시된 바와 같이, 본 발명의 캐패시터 제조 과정은, 노블계 금속막으로 된 하부전극 형성 과정(S21), BLT 시드층 형성 과정(S22), BLT막 코팅 과정(S23), 베이크 과정(S24), BLT막의 핵성장을 위한 급속열처리 과정(S25), 상부전극 형성 과정(S26) 및 BLT막의 결정화를 위한 로열처리(FA) 과정(S27)으로 구성된다.As shown in Figure 2, the capacitor manufacturing process of the present invention, the lower electrode forming process of the noble metal film (S21), the BLT seed layer forming process (S22), BLT film coating process (S23), baking process ( S24), a rapid heat treatment process (S25) for nuclear growth of the BLT film, an upper electrode formation process (S26), and a royal process (FA) process (S27) for crystallization of the BLT film.
먼저, 하부전극 형성 과정(S21)은 백금(Pt), 이리듐(Ir), 루테늄(Ru), 루테늄산화막(RuO2), 이리듐산화막(IrO2), 티타늄나이트라이드(TiN), 텅스텐(W), 텅스텐질화막(WN) 등을 이용하여 하부전극을 형성하는 과정이다.First, the lower electrode forming process S21 may include platinum (Pt), iridium (Ir), ruthenium (Ru), ruthenium oxide film (RuO 2 ), iridium oxide film (IrO 2 ), titanium nitride (TiN), and tungsten (W). , A lower electrode is formed by using a tungsten nitride film (WN).
다음으로, BLT 시드층 형성 과정(S22)은 금속막으로 된 하부전극 상에 스퍼터법(Sputter)을 이용하여 BLT막을 증착하는 과정으로서, 금속유기증착법에 의한 BLT막 코팅과 달리 스퍼터법을 이용하여 BLT를 증착하는 경우에는 하부전극인 금속막의 결정 방향에 의해 그 성장이 좌우된다.Next, the BLT seed layer forming process (S22) is a process of depositing a BLT film using a sputtering method on a lower electrode made of a metal film, using a sputtering method unlike a BLT film coating by a metal organic deposition method. In the case of depositing BLT, the growth depends on the crystal direction of the metal film as the lower electrode.
에컨대, 하부전극이 백금막(Pt)인 경우, 백금막은 (111) 방향으로 결정이 성장되어 있고, 이 백금막의 (111) 결정 방향의 영향에 의해 백금막 상에 BLT를 스퍼터증착하면 BLT가 (117) 방향으로 우선 성장한다. 이와 같이, (117) 방향으로 성장하는 BLT는 표면거칠기가 낮고 박막의 치밀도가 우수하다.For example, when the lower electrode is a platinum film Pt, crystals are grown in the (111) direction of the platinum film. When the BLT is sputter-deposited on the platinum film under the influence of the (111) crystal direction of the platinum film, the BLT becomes It grows first in the (117) direction. As such, the BLT growing in the (117) direction has a low surface roughness and excellent thin film density.
한편, BLT막의 시드층 형성 과정(S22)의 조건을 살펴보면, 온도는 상온∼600℃이고, 압력은 300mtorr∼10torr이며, 반응가스는 O2, N2 또는 Ar을 이용하고, 파워는 500W∼10KW를 인가한다. 위와 같은 조건에 의해 BLT 시드층은 1Å∼700Å의 두께로 증착되고, 하부전극으로 이용되는 금속막에 따라 결정방향이 다를 수 있으나, 주로 (117), (104), (200) 방향의 배향성을 갖고 증착된다. 결국, BLT 시드층은 후속 강유전체막인 BLT막의 c축 배향성을 억제하는 층이다.On the other hand, looking at the conditions of the seed layer forming process (S22) of the BLT film, the temperature is from room temperature to 600 ℃, the pressure is 300mtorr ~ 10torr, the reaction gas using O 2 , N 2 or Ar, the power is 500W ~ 10KW Apply. Under the above conditions, the BLT seed layer is deposited to a thickness of 1 Å to 700 ,, and the crystal direction may be different depending on the metal film used as the lower electrode, but the orientation of the (117), (104), and (200) directions is mainly different. And deposited. As a result, the BLT seed layer is a layer that suppresses the c-axis orientation of the BLT film, which is a subsequent ferroelectric film.
다음으로, BLT 시드층 상에 BLT막을 코팅하는 BLT막 코팅 과정(S23)을 진행하는데, Bi[OCOC7H15]3(Bismuth 2-ethylhexanoate), La[OCOC7H 15]3(Lanthanum 2-ethylhexanoate), Ti[OCOC7H15]4(Titanium 2-ethylhexanoate)와 같은 금속유기소스를 C7H15COOH(2-ethylhexanoic acid) 및 C8H18(octane) 용매에 용해시킨 후 CH3COO(CH2)3CH3 (n-butyl acetate) 희석액으로 희석시켜 농도를 조절하여 금속유기 용액을 형성하고 금속유기증착법(MOD) 또는 LSMCD(Liquid Source Mist Chemical Deposition)법으로 BLT 박막을 코팅한다.Next, the BLT film coating process (S23) for coating the BLT film on the BLT seed layer is performed, Bi [OCOC 7 H 15 ] 3 (Bismuth 2-ethylhexanoate), La [OCOC 7 H 15 ] 3 (Lanthanum 2- ethylhexanoate), Ti [OCOC 7 H 15] 4 ( after dissolving the metal organic sources, such as Titanium 2-ethylhexanoate) for C 7 H 15 COOH (2- ethylhexanoic acid) and C 8 H 18 (octane) solvent is CH 3 COO Dilute with (CH 2 ) 3 CH 3 (n-butyl acetate) diluent to adjust the concentration to form a metal organic solution and coat the BLT thin film by metal organic deposition (MOD) or Liquid Source Mist Chemical Deposition (LSMCD).
또한, Bi[OC3H7]3(Bismuth iso-propoxide), La[CH3COO]3 (Lanthanum acetate), Ti[OC2H5]4(Titanium ethoxide)와 같은 금속유기소스를 CH3OC 2H4OH(2-methoxyethanol) 용매에 용해시켜 금속유기 용액을 형성하고 졸-겔(Sol-gel) 또는 LSMCD법으로 BLT 박막을 코팅할 수도 있다.In addition, Bi [OC 3 H 7] 3 (Bismuth iso-propoxide), La [CH 3 COO] 3 (Lanthanum acetate), Ti [OC 2 H 5] 4 the metal-organic sources such as (Titanium ethoxide) CH 3 OC It may be dissolved in 2 H 4 OH (2-methoxyethanol) solvent to form a metal organic solution, and the BLT thin film may be coated by a sol-gel or LSMCD method.
그리고, Bi[CH3COO]3(Bismuth acetate)를 피리딘(pyridine)에 용해시키고, La[CH3COO]3(Lanthanum acetate)와 Ti[OC2H5]4(Titanium ethoxide)를 CH3COOH(acetic acid)에 용해시킨 후 두 용액을 혼합하여 금속유기용액을 형성하고 졸겔(sol-gel)법 또는 LSMCD법으로 BLT막을 코팅할 수도 있다.Bi [CH 3 COO] 3 (Bismuth acetate) was dissolved in pyridine, and La [CH 3 COO] 3 (Lanthanum acetate) and Ti [OC 2 H 5 ] 4 (Titanium ethoxide) were CH 3 COOH. After dissolving in acetic acid, the two solutions may be mixed to form a metal organic solution, and the BLT membrane may be coated by a sol-gel method or an LSMCD method.
다른 방법으로, BLT막 코팅을 스핀온(spin-on)법으로 수행할 수 있다.Alternatively, the BLT film coating may be performed by a spin-on method.
이와 같이 BLT 박막을 코팅한 후에는, 액상의 BLT막을 고체화시키는 베이크과정(S24)을 수행한다.After coating the BLT thin film as described above, a baking process (S24) of solidifying the liquid BLT film is performed.
베이크 과정(S24)은, 100℃∼200℃ 온도에서 1분∼10분간 1차 베이크 과정을 수행한 후, 200℃∼350℃ 온도에서 1분∼10분간 2차 베이크 과정을 수행한다.Baking process (S24), after performing the first bake process for 1 minute to 10 minutes at 100 ℃ to 200 ℃ temperature, performs a secondary bake process for 1 minutes to 10 minutes at 200 ℃ to 350 ℃ temperature.
상술한 1차 베이크 및 2차 베이크 과정을 통해 코팅된 BLT 막내 유기물을 제거하여 막질을 조밀화한다. 즉, 베이크 과정(S24)은 액체 상태의 BLT 케미컬에 함유된 용매, Bi, La, Ti와 결합된 저온 유기물을 제거하는 과정이다. The film quality is densified by removing the organic matter in the coated BLT film through the above-described first and second bake processes. That is, the baking process (S24) is a process of removing the low temperature organic matter combined with the solvent, Bi, La, Ti contained in the liquid BLT chemical.
한편, Bi, La, Ti과 강한 결합을 이루고 있는 유기물은 후속 급속열처리 과정에서 제거된다.On the other hand, organic matter which has a strong bond with Bi, La, Ti is removed during the subsequent rapid heat treatment.
베이크 과정(S24)을 수행한 후, BLT막의 핵생성을 위한 급속열처리 과정(S25)을 수행한다. 이때, 급속열처리 과정(S25)은 두 번의 열처리, 즉 1차 급속열처리와 2차 급속열처리를 수행한다.After performing the baking process (S24), a rapid heat treatment process (S25) for nucleation of the BLT film is performed. At this time, the rapid heat treatment process (S25) performs two heat treatments, that is, the first rapid heat treatment and the second rapid heat treatment.
1차 급속열처리는 400℃∼500℃의 온도범위에서 30℃∼300℃/분의 램프업률(Ramp up rate)로 이루어지고, 2차 급속열처리는 500℃∼800℃의 온도범위에서 30℃∼300℃/분의 램프업율로 이루어진다.The primary rapid heat treatment is at a ramp up rate of 30 ° C. to 300 ° C./min in the temperature range of 400 ° C. to 500 ° C., and the second rapid heat treatment is 30 ° C. to 500 ° C. to 800 ° C. Ramp-up rate of 300 ° C / min.
상술한 바와 같은 핵생성을 위한 급속열처리 과정(S25)을 저온에서 수행한 후 고온에서 수행하면, BLT 막내 유기물이 표면과 내부에서 용이하게 제거되고 산소와 결합되어 이루어지는 페로브스카이트 핵생성도 균일하게 이루어져 치밀한 박막을 얻을 수 있다.If the rapid thermal treatment (S25) for nucleation as described above is carried out at a low temperature and then carried out at a high temperature, the perovskite nucleation is also uniform because organic matter in the BLT membrane is easily removed from the surface and the inside and combined with oxygen. It is possible to obtain a dense thin film.
다음에 핵성장이 완료된 BLT막 상에 상부전극을 형성한다(S26). 이때, 상부전극으로는 백금, 루테늄, 루테늄산화막, 이리듐산화막, 티타늄나이트라이드, 텅스텐 또는 텅스텐질화막을 이용한다.Next, an upper electrode is formed on the BLT film where nuclear growth is completed (S26). In this case, a platinum, ruthenium, ruthenium oxide film, iridium oxide film, titanium nitride, tungsten or tungsten nitride film is used as the upper electrode.
다음으로, BLT의 결정화를 위한 로열처리 과정(S27)을 수행한다. 이때, 로열처리 과정(S27)은, 600℃∼700℃의 온도에서 이루어지고, O2, N2O, N2, Ar, Ne, Kr, Xe 또는 He 분위기에서 진행한다.Next, a royal process (S27) for the crystallization of the BLT is performed. At this time, the royal treatment process (S27) is made at a temperature of 600 ℃ to 700 ℃, and proceeds in O 2 , N 2 O, N 2 , Ar, Ne, Kr, Xe or He atmosphere.
전술한 일련의 공정에 따르면, BLT막을 코팅하기 전에 스퍼터법을 이용하여 BLT 시드층을 형성하면, 하부전극에 의해 배향성이 좌우되는 BLT 시드층의 결정 방향에 따라 BLT막이 a축 또는 랜덤한 방향으로 배향성을 갖고 코팅된다. 이와 같이, BLT막의 a축 배향성 또는 랜덤한 배향성을 증가시키면 분극값이 높아진다(도 3 참조).According to the above-described series of processes, if the BLT seed layer is formed by the sputtering method before coating the BLT film, the BLT film may be in the a-axis or random direction depending on the crystallographic direction of the BLT seed layer whose orientation is determined by the lower electrode. Coated with orientation. As such, when the a-axis orientation or random orientation of the BLT film is increased, the polarization value is increased (see FIG. 3).
도 3은 본 발명과 종래 기술에 따른 분극특성을 비교한 도면으로서, BLT 시드층을 미적용한 종래 기술(a)보다 BLT 시드층을 적용한 본 발명(b)에서 분극값이 향상됨을 알 수 있다.Figure 3 is a view comparing the polarization characteristics according to the present invention and the prior art, it can be seen that the polarization value is improved in the present invention (b) to which the BLT seed layer is applied than the prior art (a) without applying the BLT seed layer.
도 4는 도 2에 따른 방법을 적용한 비휘발성 소자를 도시한 구조 단면도이다.4 is a cross-sectional view illustrating a nonvolatile device to which the method of FIG. 2 is applied.
도 4에 도시된 바와 같이, 비휘발성 소자의 캐패시터를 살펴보면, 금속막으로 된 하부전극(21) 상에 BLT 시드층(22)이 형성되고, BLT 시드층(22) 상에 BLT막(23)이 형성되며, BLT막(23) 상에 금속막으로 된 상부전극(24)이 형성되고 있다.As shown in FIG. 4, the capacitor of the nonvolatile device is described. The BLT seed layer 22 is formed on the lower electrode 21 made of a metal film, and the BLT film 23 is formed on the BLT seed layer 22. Is formed, and an upper electrode 24 made of a metal film is formed on the BLT film 23.
그리고, 비휘발성 소자는 소자분리막(12)이 형성된 반도체 기판(11)에 소스/드레인영역(15a, 15b), 게이트산화막(13) 및 워드라인(14)을 포함하는 트랜지스터가 형성되고, 반도체 기판(11) 상부를 제1 층간절연막(16)이 덮고 있으며, 제1 층간절연막(16)을 관통하여 일측 소스/드레인영역(15a)에 비트라인콘택(17)이 연결되며, 비트라인콘택(17)에 비트라인(18)이 연결된다. 그리고, 제1 층간절연막(16) 상에 제2 층간절연막(19)이 형성되고, 제2 층간절연막(19)과 제1 층간절연막(16)을 동시에 관통하여 타측 소스/드레인영역(15b)에 스토리지노드콘택(20)이 연결된다. 이와 같은 스토리지노드콘택(20)은 하부전극(21)과 연결되고, 통상적으로 폴리실리콘플러그, 티타늄실리사이드 및 티타늄나이트라이드의 순서로 적층된 구조물이다.In the nonvolatile device, a transistor including source / drain regions 15a and 15b, a gate oxide film 13, and a word line 14 is formed on a semiconductor substrate 11 on which the device isolation film 12 is formed. The first interlayer insulating layer 16 covers the upper portion, and the bit line contact 17 is connected to one source / drain region 15a through the first interlayer insulating layer 16 and the bit line contact 17. Is connected to the bit line 18. A second interlayer insulating film 19 is formed on the first interlayer insulating film 16, and simultaneously passes through the second interlayer insulating film 19 and the first interlayer insulating film 16 to the other source / drain region 15b. The storage node contact 20 is connected. The storage node contact 20 is connected to the lower electrode 21 and is typically a structure stacked in the order of polysilicon plug, titanium silicide and titanium nitride.
전술한 실시예들에서는 BLT 시드층과 BLT막을 예로 들어 설명하였으나, BTO를 강유전체막으로 이용하는 캐패시터에서 BTO 코팅전에 BTO 시드층을 형성하는 경우에도 분극값 증대의 효과를 얻을 수 있다.In the above embodiments, the BLT seed layer and the BLT film have been described as an example. However, the polarization value may be increased even when the BTO seed layer is formed before the BTO coating in the capacitor using the BTO as the ferroelectric film.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 BLT, BTO와 같은 비스무스계 강유전체막의 a축 배향성 또는 랜덤 배향성을 증가시켜 분극값을 증가시켜 비스무스계 강유전체막을 유전막으로 이용하는 캐패시터의 전기적 특성을 개선시킬 수 있는 효과가 있다. As described above, the present invention has the effect of increasing the polarization value by increasing the a-axis orientation or random orientation of the bismuth ferroelectric films such as BLT and BTO, thereby improving the electrical characteristics of the capacitor using the bismuth ferroelectric film as the dielectric film.
도 1은 종래기술에 따른 캐패시터의 제조 방법을 간략히 도시한 공정 흐름도,1 is a process flow diagram briefly showing a method of manufacturing a capacitor according to the prior art;
도 2는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 흐름도,2 is a process flow diagram illustrating a method of manufacturing a capacitor according to an embodiment of the present invention;
도 3은 본 발명과 종래 기술에 따른 분극특성을 비교한 도면,3 is a view comparing polarization characteristics according to the present invention and the prior art;
도 4는 도 2에 따른 방법을 적용한 비휘발성 소자를 도시한 구조 단면도.4 is a cross-sectional view illustrating a nonvolatile device to which the method according to FIG. 2 is applied.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 하부전극 22 : BLT 시드층21: lower electrode 22: BLT seed layer
23 : BLT막 24 : 상부전극23: BLT film 24: upper electrode
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| US11848366B2 (en) | 2019-12-23 | 2023-12-19 | Samsung Electronics Co., Ltd. | Electronic device and method of manufacturing the same |
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