KR100384846B1 - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR100384846B1 KR100384846B1 KR10-2000-0073112A KR20000073112A KR100384846B1 KR 100384846 B1 KR100384846 B1 KR 100384846B1 KR 20000073112 A KR20000073112 A KR 20000073112A KR 100384846 B1 KR100384846 B1 KR 100384846B1
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- capacitor
- lower electrode
- sccm
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- dielectric film
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- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 31
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000001301 oxygen Substances 0.000 claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000009832 plasma treatment Methods 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 26
- 229910052707 ruthenium Inorganic materials 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 239000002994 raw material Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000003085 diluting agent Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 2
- 239000007800 oxidant agent Substances 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000007547 defect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 27
- 239000010409 thin film Substances 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 230000008021 deposition Effects 0.000 abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 239000000126 substance Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- NGCRLFIYVFOUMZ-UHFFFAOYSA-N 2,3-dichloroquinoxaline-6-carbonyl chloride Chemical compound N1=C(Cl)C(Cl)=NC2=CC(C(=O)Cl)=CC=C21 NGCRLFIYVFOUMZ-UHFFFAOYSA-N 0.000 description 1
- OXJUCLBTTSNHOF-UHFFFAOYSA-N 5-ethylcyclopenta-1,3-diene;ruthenium(2+) Chemical group [Ru+2].CC[C-]1C=CC=C1.CC[C-]1C=CC=C1 OXJUCLBTTSNHOF-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000007983 Tris buffer Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- LENZDBCJOHFCAS-UHFFFAOYSA-N tris Chemical group OCC(N)(CO)CO LENZDBCJOHFCAS-UHFFFAOYSA-N 0.000 description 1
- 239000006200 vaporizer Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 DRAM 및 FeRAM의 캐패시터 제조 방법에 관한 것으로, 소정 공정이 완료된 반도체기판상에 하부전극을 형성하는 단계, 상기 하부전극이 형성된 반도체기판을 유전막 반응 챔버로 이동시키는 단계, 상기 유전막 반응 챔버내에서 상기 하부전극을 플라즈마처리하는 단계, 상기 유전막 반응 챔버내에서 상기 플라즈마 처리된 하부전극상에 유전막을 형성하는 단계, 및 상기 유전막상에 상부전극을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method for manufacturing a capacitor of DRAM and FeRAM, the method comprising: forming a lower electrode on a semiconductor substrate having a predetermined process, moving the semiconductor substrate on which the lower electrode is formed to a dielectric film reaction chamber, and in the dielectric film reaction chamber Plasma processing the lower electrode, forming a dielectric film on the plasma-treated lower electrode in the dielectric film reaction chamber, and forming an upper electrode on the dielectric film.
본 발명은 유전막 반응 챔버내에서 하부전극용 금속박막을 NH3플라즈마처리하여 하부전극용 금속박막내의 산소를 제거하므로써 유전막 증착 및 후속 열공정시 산소 확산에 의한 하부 확산방지막의 산화를 방지할 수 있다.The present invention can prevent oxidation of the lower diffusion barrier due to oxygen diffusion during dielectric deposition and subsequent thermal process by removing oxygen in the lower electrode metal thin film by NH 3 plasma treatment of the lower electrode metal thin film in the dielectric film reaction chamber.
Description
본 발명은 메모리소자의 제조 방법에 관한 것으로, 특히 MIM 구조의 캐패시터의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a memory device, and more particularly, to a method of manufacturing a capacitor of the MIM structure.
일반적으로, 반도체 메모리 소자에서 강유전체(Ferroelectric) 재료를 캐패시터에 사용함으로써 기존 DRAM(Dynamic Random Access Memory) 소자에서 필요한 리프레쉬(Refresh)의 한계를 극복하고 대용량의 메모리를 이용할 수 있는 소자의 개발이 진행되어왔다. FeRAM(Ferroelectric Random Access Memory) 소자는 비휘발성 메모리 소자의 일종으로 전원이 끊어진 상태에서도 저장 정보를 기억하는 장점이 있을 뿐만 아니라 동작 속도도 기존의 DRAM에 필적하여 차세대 기억소자로 각광받고 있다.In general, by using a ferroelectric material in a capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional DRAM (Dynamic Random Access Memory) device is in progress. come. Ferroelectric Random Access Memory (FeRAM) is a type of nonvolatile memory device that not only stores the stored information even when the power supply is turned off, but also has an operation speed comparable to that of conventional DRAMs.
이러한 FeRAM 소자의 축전물질로는 SrBi2Ta2O9(이하 SBT)와 Pb(Zr,Ti)O3(이하 PZT) 박막이 주로 사용된다. 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(Remnant polarization) 상태를 갖고 있어 이를 박막화하여 비휘발성(Nonvolatile) 메모리 소자로의 응용이 실현되고 있다. 강유전체 박막을 이용하는 비휘발성 메모리 소자는, 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호 '1'과 '0'을 저장하는 히스테리시스(Hysteresis) 특성을 이용한다.SrBi 2 Ta 2 O 9 (hereinafter referred to as SBT) and Pb (Zr, Ti) O 3 (hereinafter referred to as PZT) thin films are mainly used as storage materials for such FeRAM devices. Ferroelectrics have hundreds to thousands of dielectric constants at room temperature and have two stable Remnant polarization states, making them thinner and realizing their application to nonvolatile memory devices. Non-volatile memory devices using ferroelectric thin films store the digital signals '1' and '0' by controlling the direction of polarization in the direction of the applied electric field and inputting the signal, and the residual polarization remaining when the electric field is removed. The hysteresis characteristic is used.
FeRAM 소자에서 캐패시터의 강유전체 재료로서 PZT, SBT, SrxBiy(TaiNbj)2O9(이하 SBTN) 등의 페로브스카이트(perovskite) 구조를 갖는 강유전체를 사용하는 경우 통상적으로 백금(Pt), 이리듐(Ir), 루테늄(Ru), 백금합금(Pt-alloy) 등의 금속박막을 이용하여 상/하부전극을 형성한다.As the ferroelectric material of the capacitor in the FeRAM device When using a ferroelectric having a perovskite (perovskite) structure such as PZT, SBT, Sr x Bi y (Ta i Nb j) 2 O 9 ( hereinafter SBTN) typically platinum ( Upper and lower electrodes are formed using a metal thin film such as Pt), iridium (Ir), ruthenium (Ru), and platinum alloy (Pt-alloy).
메모리소자의 Ta2O5를 구비하는 캐패시터의 제조 공정시, 하부전극으로 금속박막을 사용하면, 금속박막의 배향성에 따라 유전막이 우선 방향성을 나타내어 유전상수가 증가한다. 또한 금속박막은 폴리실리콘과의 전기적 에너지 장벽이 크므로 유효산화막 두께를 감소시킬 수 있으며 동일 유효산화막 두께에서의 누설전류를 감소시킬 수 있는 장점을 갖는다.In the manufacturing process of the capacitor including Ta 2 O 5 of the memory device, when the metal thin film is used as the lower electrode, the dielectric film first shows the orientation according to the orientation of the metal thin film, and the dielectric constant increases. In addition, since the metal thin film has a large electrical energy barrier with polysilicon, the effective oxide film thickness can be reduced and the leakage current at the same effective oxide film thickness can be reduced.
이러한 금속박막은 다양한 방법으로 증착가능하지만 단차 피복성이 우수한 화학적기상증착법(Chemical Vapor Deposition; CVD)에 대한 연구가 활발히 진행되고 있다. 실제로 금속박막 중 루테늄(Ru)의 경우, 백금과 비교하여 식각공정이 상대적으로 쉬울 뿐만 아니라 화학적기상증착법(CVD)에 대한 상대적으로 높은 가능성 때문에 많은 연구가 진행되고 있다.Such metal thin films can be deposited by various methods, but research on chemical vapor deposition (CVD) with excellent step coverage is being actively conducted. In fact, in the case of ruthenium (Ru) of the metal thin film, much research is being conducted because of the relatively easy etching process compared with platinum and the relatively high possibility of chemical vapor deposition (CVD).
루테늄(Ru)을 DRAM 및 FeRAM의 하부전극으로 이용하기 위하여 저압화학기상증착법(Low Pressure CVD; LPCVD)에 의해 형성할 경우, 소스 분해를 위해 필연적으로 첨가되는 산소(O2) 또는 N2O가 루테늄(Ru) 내에 잔류하게 된다. 루테늄막 내에 잔류하는 산소는 루테늄막의 치밀도 향상이나, 루테늄막상에 형성되는 BST 등의 강유전체막을 결정화시키는 후속 열처리동안, 확산방지막으로 이용되는 TiN 등을 산화시켜 전체 캐패시터의 유전 용량을 감소시키는 원인으로 작용하는 문제점이 있다.When ruthenium (Ru) is formed by low pressure CVD (LPCVD) in order to use the lower electrodes of DRAM and FeRAM, oxygen (O 2 ) or N 2 O, which is inevitably added for source decomposition, It remains in ruthenium (Ru). Oxygen remaining in the ruthenium film causes the reduction of the dielectric capacity of the entire capacitor by oxidizing TiN or the like used as a diffusion barrier during subsequent heat treatment to improve the density of the ruthenium film or to crystallize the ferroelectric film such as BST formed on the ruthenium film. There is a problem at work.
따라서 루테늄막 내에 함유되어 있는 산소를 효과적으로 제거할 수 있는 방법이 필요하다.Therefore, there is a need for a method capable of effectively removing oxygen contained in the ruthenium film.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 하부전극 하부의 확산방지막의 산화를 방지하면서 하부전극용 금속박막 내에 잔류하는 산소를 제거하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, to provide a method of manufacturing a capacitor suitable for removing oxygen remaining in the metal thin film for the lower electrode while preventing the oxidation of the diffusion barrier under the lower electrode. have.
도 1a 내지 도 1b는 본 발명의 실시예에 따른 캐패시터의 제조 공정 단면도,1a to 1b is a cross-sectional view of the manufacturing process of the capacitor according to the embodiment of the present invention,
도 2는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 공정 흐름도.2 is a process flow diagram illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film
23 : 폴리실리콘 플러그 24 : Ti23: polysilicon plug 24: Ti
25 : TiN 26 : 식각방지막25: TiN 26: etching prevention film
27 : 캐패시터 산화막 28 : 루테늄27: capacitor oxide film 28: ruthenium
29 : Ta2O530 : 상부전극29: Ta 2 O 5 30: the upper electrode
상기 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 반도체기판상에 확산방지막을 형성하는 단계, 상기 확산방지막상에 하부전극을 형성하는 단계, 상기 하부전극이 형성된 반도체기판을 유전막 증착을 위한 반응 챔버로 이동시키는 단계, 상기 반응 챔버내에서 인시튜로 상기 하부전극을 NH3플라즈마처리하여 상기 하부전극내 잔류하는 산소를 제거하는 단계, 상기 반응 챔버내에서 상기 NH3플라즈마 처리된 하부전극상에 유전막을 형성하는 단계, 및 상기 유전막상에 상부전극을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor, which includes forming a diffusion barrier on a semiconductor substrate, forming a bottom electrode on the diffusion barrier, and depositing a semiconductor substrate on which the bottom electrode is formed. Moving to the chamber, removing the oxygen remaining in the lower electrode by NH 3 plasma treatment in-situ in the reaction chamber, on the NH 3 plasma treated lower electrode in the reaction chamber. Forming a dielectric film, and forming an upper electrode on the dielectric film.
바람직하게, 상기 NH3플라즈마 처리시 100W∼300W의 파워를 유지하고, NH3가스는 100sccm∼300sccm의 유량을 유지하며, 0.1torr∼2torr의 압력을 유지한 상태에서 60∼12초동안 이루어지는 것을 특징으로 한다.Preferably, the NH 3 plasma is maintained at a power of 100W to 300W, the NH 3 gas is maintained at a flow rate of 100sccm to 300sccm, it is made for 60 to 12 seconds while maintaining a pressure of 0.1torr to 2torr It is done.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1a 내지 도 1b는 본 발명의 실시예에 따른 캐패시터의 제조 공정 단면도이고, 도 2는 본 발명의 실시예에 따른 캐패시터의 제조 공정 흐름도이다. 도 2에서 트랜지스터 제조 공정은 생략하며, 이후 도 1a 내지 도 1b 및 도 2를 참조하여 설명한다.1A to 1B are cross-sectional views illustrating a manufacturing process of a capacitor according to an embodiment of the present invention, and FIG. 2 is a flowchart illustrating a manufacturing process of a capacitor according to an embodiment of the present invention. The transistor fabrication process is omitted in FIG. 2 and will be described with reference to FIGS. 1A to 1B and FIG. 2.
도 1a에 도시된 바와 같이, 소정 공정, 예컨대 워드라인, 비트라인, 소스/드레인을 포함하는 트랜지스터(도시 생략)의 제조 공정이 완료된 반도체기판(21)상에 층간절연막(22)을 형성한 후, 층간절연막(22)을 선택적으로 패터닝하여 후속 캐패시터와 트랜지스터를 접속시키는 플러그용 콘택홀을 형성한다. 계속해서, 오픈된 플러그용 콘택홀을 포함한 층간절연막(22)상에 폴리실리콘을 증착한 다음, 폴리실리콘을 리세스 에치백(Recess etchback)하여 콘택홀을 소정 깊이만큼 매립시키는 폴리실리콘 플러그(23)를 형성한다.As shown in FIG. 1A, after the interlayer insulating film 22 is formed on the semiconductor substrate 21 on which a predetermined process, for example, a process of manufacturing a transistor (not shown) including a word line, a bit line, and a source / drain is completed, The interlayer insulating film 22 is selectively patterned to form a plug contact hole for connecting the subsequent capacitor and the transistor. Subsequently, polysilicon is deposited on the interlayer insulating layer 22 including the open plug contact hole, and then the recess is etched back into the polysilicon to fill the contact hole by a predetermined depth. ).
이어서, 폴리실리콘 플러그(23)을 포함한 층간절연막(22)상에 확산방지막으로서 Ti(24), TiN(25)을 순차적으로 형성한 다음, 층간절연막(22)이 드러나도록 Ti(24), TiN(25)을 화학적기계적연마(CMP) 또는 에치백하여 폴리실리콘 플러그(23) 상부에만 Ti(24), TiN(25)을 잔류시킨다.Subsequently, Ti (24) and TiN (25) are sequentially formed on the interlayer insulating film 22 including the polysilicon plug 23, and then Ti (24) and TiN are exposed so that the interlayer insulating film 22 is exposed. Chemical mechanical polishing (CMP) or etching back 25 leaves Ti (24) and TiN (25) only on the polysilicon plug (23).
이어서, 확산방지막이 형성된 층간절연막(22)상에 식각방지막(26)으로서 SiN을 형성하고, SiN상에 캐패시터 산화막(27)을 형성한 다음, 캐패시터 산화막(27)과식각방지막(26)을 순차적으로 식각하여 하부의 확산방지막에 접속되는 캐패시터의 하부전극이 형성될 영역을 오픈시킨다(도 2의 100).Subsequently, SiN is formed as an etch stop layer 26 on the interlayer insulating film 22 having the diffusion barrier layer, a capacitor oxide layer 27 is formed on the SiN, and then the capacitor oxide layer 27 and the etch barrier layer 26 are sequentially formed. Etching to open the region where the lower electrode of the capacitor to be connected to the lower diffusion barrier film is formed (100 in FIG. 2).
도 1b에 도시된 바와 같이, 오픈된 영역에 하부전극으로서 루테늄(28)을 증착하고, 화학적기계적연마 또는 에치백하여 인접한 루테늄(28)간을 분리시킨다(도 2의 101).As shown in FIG. 1B, ruthenium 28 is deposited as a lower electrode in the open region and chemically polished or etched back to separate adjacent ruthenium 28 (101 in FIG. 2).
루테늄(28)의 증착 방법에 대해 상술하면, 저압화학기상증착법(LPCVD)으로 형성되는데, 루테늄의 원료물질은 Ru(OD)3또는 Ru(Etcp)2중 어느 하나를 이용하고, 기화기(Vaporizer)를 이용하여 원료물질을 기상상태로 변환한다. 위와 같은 원료 물질들의 화학식 및 화학명은 다음과 같다.The deposition method of ruthenium 28 is described in detail by low pressure chemical vapor deposition (LPCVD), and the raw material of ruthenium is either Ru (OD) 3 or Ru (Etcp) 2 , and a vaporizer. Convert the raw material to the gas phase using. The chemical formula and chemical name of the above raw materials are as follows.
Ru(OD)3의 화학식은 Ru(CH3COCHCOCH2CH2CH2CH3)3, 화학명은 Tris(2,4-octanedionato)ruthenium이며, Ru(Etcp)2의 화학식은 (Ru(C2H5C5H4)2), 화학명은 Bis(ethylcyclopentadienyl)ruthenium이다.The chemical formula of Ru (OD) 3 is Ru (CH 3 COCHCOCH 2 CH 2 CH 2 CH 3 ) 3 , the chemical name is Tris (2,4-octanedionato) ruthenium, and the formula of Ru (Etcp) 2 is (Ru (C 2 H). 5 C 5 H 4 ) 2 ), the chemical name is Bis (ethylcyclopentadienyl) ruthenium.
상술한 원료물질의 운반가스는 아르곤(Ar)을 이용하되 50sccm∼200sccm의 유량을 유지하며, 원료물질을 분해하기 위한 반응가스는 50sccm∼400sccm을 유지하는 산소(O2)를 이용한다. 아울러, 희석가스로는 400sccm∼800sccm의 유량을 유지하는 아르곤을 이용하며, 반응챔버는 0.1torr∼10torr을 유지한다.Argon (Ar) is used as the carrier gas of the above-described raw material, but the flow rate of 50 sccm to 200 sccm is maintained, and the reaction gas for decomposing the raw material uses oxygen (O 2 ) to maintain 50 sccm to 400 sccm. In addition, as the diluent gas, argon maintaining a flow rate of 400 sccm to 800 sccm is used, and the reaction chamber maintains 0.1 to 10 tor.
상술한 원료물질을 이용하여 루테늄(28)을 증착할 때, 반도체기판(21)은 230℃∼350℃의 온도를 유지하며, 증착되는 루테늄(28)의 두께는 100Å∼300Å이다.When the ruthenium 28 is deposited using the above-described raw material, the semiconductor substrate 21 maintains a temperature of 230 ° C to 350 ° C, and the thickness of the deposited ruthenium 28 is 100 kPa to 300 kPa.
루테늄(28) 증착후, 강유전체 박막을 증착하기 전에 강유전체 박막을 증착하기 위한 반응챔버에서 인시튜(In-situ)로 NH3플라즈마처리를 실시하여 루테늄(28) 내에 잔류하는 산소를 제거한다(도 2의 102).After ruthenium 28 is deposited, NH 3 plasma treatment is performed in-situ in the reaction chamber for depositing the ferroelectric thin film to remove oxygen remaining in the ruthenium 28 (FIG. 2, 102).
인시튜 NH3플라즈마 처리시, 먼저 반도체기판(21)은 후속 강유전체 박막의 증착 온도와 동일한 온도로 유지되며, 플라즈마 파워는 100W∼300W를 유지한다. 그리고, NH3가스는 100sccm∼300sccm의 유량을 유지하고, 반응챔버는 0.1torr∼2torr의 압력을 유지하며 플라즈마 처리는 60∼12초 동안 진행된다.In the in-situ NH 3 plasma treatment, the semiconductor substrate 21 is first maintained at the same temperature as the deposition temperature of the subsequent ferroelectric thin film, and the plasma power is maintained at 100W to 300W. The NH 3 gas maintains a flow rate of 100 sccm to 300 sccm, the reaction chamber maintains a pressure of 0.1 tor to 2 torr, and the plasma treatment proceeds for 60 to 12 seconds.
NH3플라즈마 처리된 루테늄(28)상에 강유전체 박막으로서 Ta2O5(29)를 증착한다(도 2의 103).Ta 2 O 5 29 is deposited as a ferroelectric thin film on the NH 3 plasma treated ruthenium 28 (103 in FIG. 2).
Ta2O5(29) 증착시, 원료물질로 탄탈륨 에톡사이드(Tantalum Etoxide) [Ta(C2H5O)5]를 사용하고 반응원료의 운반가스는 N2, 산화제는 O2를 이용한다. 이 때, N2는 350sccm∼450sccm의 유량을 유지하고 O2는 20sccm∼50sccm의 유량을 유지한다. 그리고, 반응챔버는 0.1∼2torr의 압력을 유지하며, 300℃∼450℃의 온도에서 Ta2O5(29)이 증착된다.In the deposition of Ta 2 O 5 (29), tantalum ethoxide [Ta (C 2 H 5 O) 5 ] is used as a raw material, and the carrier gas of the reaction material is N 2 , and an oxidant is O 2 . At this time, N 2 maintains a flow rate of 350 sccm to 450 sccm, and O 2 maintains a flow rate of 20 sccm to 50 sccm. The reaction chamber maintains a pressure of 0.1 to 2 torr, and Ta 2 O 5 (29) is deposited at a temperature of 300 to 450 ° C.
후속 공정으로 Ta2O5(29) 내에 잔류하는 탄소, 수소 등의 불순물 및 산소 공공(vacancy)과 같은 결함을 제거하기 위한 열처리를 진행하는데(도 2의 104), 이러한 열처리는 저온에서 플라즈마 열처리 또는 UV/O3열처리 중 어느 하나의 열처리를 실시한다.Subsequent processes proceed with a heat treatment to remove impurities such as carbon, hydrogen and other impurities remaining in the Ta 2 O 5 (29) (104 in FIG. 2), which is a plasma heat treatment at low temperatures. Or UV / O 3 heat treatment.
먼저, 플라즈마 열처리시, 300℃∼450℃의 온도로 O2, N2O 또는 N2와 O2의 혼합가스 분위기에서 30초∼120초동안 200W∼500W의 파워로 진행한다.First, the process advances to the plasma heat treatment, temperature 300 ℃ as O 2, N 2 O or N 2 and O 2 in 200W~500W power in a mixed gas atmosphere for 30-120 seconds of ~450 ℃.
다음으로, UV/O3열처리시, 300℃∼450℃의 온도로 2분∼10분동안 15mW/cm2∼30mW/cm2의 강도로 실시한다.Next, UV / O 3 for 2-10 minutes to heat treatment, a temperature of 300 ℃ ~450 ℃ carried out at an intensity of 15mW / cm 2 ~30mW / cm 2 .
계속해서, Ta2O5(29)의 유전특성을 확보하고 루테늄(28)의 산화를 방지하기 위해 급속열처리(RTA) 또는 노열처리(Furnace annealing)을 실시한다(도 2의 105).Subsequently, rapid thermal treatment (RTA) or furnace annealing is performed to secure the dielectric properties of Ta 2 O 5 29 and to prevent oxidation of ruthenium 28 (105 in FIG. 2).
급속열처리를 실시할 경우, 산소와 질소, 아르곤, 헬륨 등의 비활성 가스의 혼합분위기로 500℃∼600℃에서 30초∼60초동안 실시하며, 노열처리를 실시할 경우, 산소 및 비활성 가스의 혼합 분위기로 500℃∼600℃에서 10분∼30분동안 실시한다. 급속열처리 및 노열처리 모두 산소와 비활성가스의 혼합비는 1:10∼10:10을 유지한다.In the case of rapid heat treatment, oxygen and nitrogen, argon, helium, etc., are mixed at 500 ° C to 600 ° C for 30 seconds to 60 seconds, and in the case of furnace treatment, oxygen and inert gas are mixed. 10 minutes-30 minutes at 500 to 600 degreeC by atmosphere. In both rapid heat treatment and furnace heat treatment, the mixing ratio of oxygen and inert gas is maintained at 1:10 to 10:10.
상술한 열처리후 상부전극으로서 TiN 또는 Ru 중 어느 하나를 증착한다(도 2의 106).After the heat treatment described above, either TiN or Ru is deposited as the upper electrode (106 in FIG. 2).
도면에 도시되지 않았지만, 본 발명은 루테늄을 하부전극으로 사용하는 MIM구조의캐패시터에 한정되지 않고 실린더형 캐패시터의 제조 공정, BST와 같은 고유전체 캐패시터의 제조 공정, PZT와 같은 강유전체 캐패시터의 제조 공정에서 루테늄 이외의 다른 금속박막을 하부전극으로 사용하는 모든 경우에 적용하여 금속박막내의 산소를 제거할 수 있다.Although not shown in the drawings, the present invention is not limited to a capacitor of a MIM structure using ruthenium as a lower electrode, and is used in a manufacturing process of a cylindrical capacitor, a manufacturing process of a high dielectric capacitor such as BST, and a manufacturing process of a ferroelectric capacitor such as PZT. In all cases where a metal thin film other than ruthenium is used as the lower electrode, oxygen in the metal thin film can be removed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 캐패시터의 제조 방법은 하부전극용 금속박막내에 잔류하는 산소를 유전막 증착 챔버에서 인시튜로 NH3플라즈마 처리하므로써 유전막 증착 및 후속 열공정시 산소확산에 의한 확산방지막의 산화를 방지하여 캐패시터의 전기적 특성을 향상시킬 수 있는 효과가 있다.Prevent oxidation of the film The method of manufacturing the capacitor of the invention is spread by a dielectric deposition and subsequent tear-time oxygen diffusion By NH 3 plasma process of oxygen remaining on the lower electrode foil membrane for in-situ in a dielectric deposition chamber, as described above Therefore, there is an effect that can improve the electrical characteristics of the capacitor.
그리고, 유전막 증착 챔버에서 인시튜로 산소를 제거하기 위한 플라즈마 처리 공정이 진행되므로 하부전극내 산소를 제거하기 위한 별도의 장비를 추가하지 않아도 되는 효과가 있다.In addition, since the plasma processing process for removing oxygen in situ in the dielectric film deposition chamber proceeds, there is an effect of not having to add a separate equipment for removing oxygen in the lower electrode.
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