KR100359785B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention is to prevent the oxidation of the barrier layer to prevent the reaction between the lower electrode and the plug in the high-density semiconductor device using a high-k dielectric film and to improve the etching profile according to the lower electrode etching, the semiconductor of the present invention The device includes a semiconductor substrate, a first insulating layer formed with a contact hole on the substrate, a plug and barrier layer sequentially stacked in the contact hole, a second insulating layer formed in a predetermined region on the first insulating layer; And an upper electrode selectively formed on the second insulating layer, a ferroelectric thin film heat-treated in a nitrogen atmosphere firstly formed on the upper electrode side surface and the second insulating layer, and secondly heat-treated in an oxygen atmosphere, and on the ferroelectric thin film. A first lower electrode formed on the barrier layer and a second lower electrode formed integrally with the first lower electrode; Characterized in that configured to include.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to semiconductor devices suitable for highly integrated cells and methods of manufacturing the same.

Hereinafter, a semiconductor device manufacturing method according to the related art will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As illustrated in FIG. 1A, after the silicon oxide film 12 is deposited on the semiconductor substrate 11, a contact hole 13 through which a predetermined portion of the substrate is exposed is formed by using a photolithography process.

Subsequently, as shown in FIG. 1B, the plug 14 made of polysilicon and the barrier layer 15 are sequentially formed in the contact hole 13. At this time, the barrier layer 15 is a laminated film of titanium (Ti) 15a and titanium nitride (TiN) 15b.

As shown in FIG. 1C, a lower electrode material layer is formed on the entire surface including the barrier layer 15 and the silicon oxide layer 12, and then patterned to form a stack type lower electrode 16.

Subsequently, a ferroelectric material, for example, BST (Ba: Sr: Ti) 17 is formed on the entire surface including the lower electrode 16. Thereafter, the BST 17 is crystallized by heat treatment in a high temperature oxygen atmosphere.

Subsequently, as shown in FIG. 1D, after forming the upper electrode material on the BST 17 and patterning the upper electrode 18, the semiconductor device manufacturing process according to the related art is completed.

However, in the conventional method of manufacturing a semiconductor device as described above, after forming the BST, which is a ferroelectric thin film, the barrier layer for preventing the reaction between the lower electrode and the plug is oxidized during the high temperature heat treatment for crystallization, so that a desired capacitance cannot be obtained. In addition, there is a problem that the composition of the ferroelectric thin film can be caused because the electrode only the cell portion and the remaining portion is an oxide film over the entire substrate.

The present invention has been made to solve the above problems of the prior art, in the highly integrated semiconductor device using a high-k dielectric layer to prevent the oxidation of the barrier layer to prevent the reaction between the lower electrode and the plug and the etching according to the lower electrode etching It is an object of the present invention to provide a semiconductor device suitable for improving a profile and a method of manufacturing the same.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.

2 is a structural cross-sectional view of a semiconductor device according to the present invention.

3A to 3I are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

Explanation of symbols for main parts of the drawings

11, 21: semiconductor substrate 22: first insulating layer

13,23: plug 15,24: barrier layer

25, 26, 28: second, third, fourth insulating layer

18,27a: upper electrode 30,31: first and second lower electrodes

A semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a first insulating layer formed with a contact hole on the substrate, a plug and barrier layer sequentially stacked in the contact hole, and the first insulation A second insulating layer formed in a predetermined region on the layer, an upper electrode selectively formed on the second insulating layer, and a first heat treatment in a first nitrogen atmosphere formed on the upper electrode side surface and the second insulating layer, and then in a second oxygen atmosphere. And a heat treated ferroelectric thin film, a first lower electrode formed on the ferroelectric thin film, and a second lower electrode formed on the barrier layer and integrally formed with the first lower electrode.

The semiconductor device manufacturing method of the present invention comprises the steps of forming a first insulating layer having a contact hole on a semiconductor substrate, sequentially forming a plug and a barrier layer in the contact hole, and forming a first insulating layer and a barrier layer on the semiconductor substrate. Depositing a second insulating layer and a third insulating layer on the entire surface, selectively removing the third insulating layer to form a third insulating layer pattern, and forming an upper electrode between the third insulating layer pattern Forming a fourth insulating layer over the upper electrode and the third insulating layer pattern, removing the fourth insulating layer leaving portions other than the upper electrode, and removing the third insulating layer pattern; Forming a ferroelectric thin film on the entire surface of the second insulating layer including the upper electrode and the fourth insulating layer, and performing a first heat treatment in a nitrogen atmosphere to crystallize the ferroelectric thin film; Performing a second heat treatment in the air, forming a first lower electrode on the side of the ferroelectric thin film, removing the ferroelectric thin film using the first lower electrode as a mask, and exposing the barrier layer to expose the barrier layer. Removing the layer and removing the fourth insulating layer by a predetermined thickness; and forming a second lower electrode integral with the first lower electrode on the barrier layer.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

2 is a structural cross-sectional view of a semiconductor device according to the present invention.

As shown in FIG. 2, the semiconductor device of the present invention includes a semiconductor substrate 21, a first insulating layer 22 having a contact hole on the substrate, a plug 23 and a barrier layer sequentially formed in the contact hole. 24, a second insulating layer pattern 25a formed on the first insulating layer 22, and an upper electrode 27a and a fourth insulating layer pattern selectively formed on the second insulating layer pattern 25a. (28a), the ferroelectric thin film 29b formed on the side surfaces of the upper electrode 27a and the fourth insulating layer pattern 28a, the first lower electrode 30 formed on the ferroelectric thin film 29b, and And a second lower electrode 31 formed on the barrier layer 24 and integrally formed with the first lower electrode 30.

Here, the barrier layer 24 is composed of a laminated film of Ti (24a) / TiN (24b), it is possible to use a ternary nitride material such as TiSiN or TiAlN instead of the TiN.

The material of the upper electrode and the first and second lower electrodes may be any one of Pt, Ru, RuOx, and IrOx.

A method of manufacturing a semiconductor device of the present invention configured as described above will be described with reference to FIGS. 3A to 3I. The reason why the fourth insulating layer pattern 28a is described immediately after the second insulating layer pattern 25a is because of the process. This is because all of the third insulating layers are removed. Such matters are referred to in the following method for manufacturing a semiconductor device.

As shown in FIG. 3A, a first insulating layer 22 is formed on the semiconductor substrate 21, and contact holes are formed to expose a predetermined portion of the substrate. Thereafter, the plug 23 and the barrier layer 24 are sequentially formed in the contact hole.

At this time, the plug 23 is made of polysilicon, and the barrier layer 24 is a laminated film of titanium (Ti) 24a / titanium nitride (TiN) 24b.

Here, the barrier layer is to prevent the reaction between the polysilicon and the lower electrode to be formed in a later process, using a binary nitride-based material such as TiN, but to increase the oxidation resistance TiSiN or TiAlN Ternary nitride-based materials such as the like may be used.

Subsequently, as shown in FIG. 3B, after planarizing the entire surface, the second insulating layer 25 and the third insulating layer 26 are sequentially formed. Here, the second insulating layer 25 is a silicon nitride film, and the third insulating layer 26 is a silicon oxide film.

The second insulating layer 25 is deposited to a thickness of 100 ~ 200Å and the lower portion generated after the deposition and heat treatment of the ferroelectric thin film formed thereafter, together with the function to protect the lower layer when etching the third insulating layer 26 It has a function to prevent oxidation of the electrode barrier layer.

As shown in FIG. 3C, the third insulating layer 26 is selectively etched to form a third insulating layer pattern 26a defining a region in which the upper electrode is to be formed.

At this time, the electrode material is deposited and then etched to define the region where the electrode is to be formed as an insulating layer instead of forming the electrode, and then the electrode is formed when the electrode material Pt, Ru, Ir, etc. is etched. This is because there is a limit to the formation and application to highly integrated cells. That is, after the electrode formation region is defined by the silicon oxide film in which the etching profile is almost vertical, the electrode is formed in a substantially right angle.

Another reason is to prevent a change in the composition ratio of the ferroelectric thin film by allowing all areas of the wafer except for the cell portion to be made of the same material.

The upper electrode material 27 is then formed by chemical vapor deposition (CVD). In this case, good leakage current characteristics can be obtained by using materials having a large work function such as Pt, Ru, RuOx, IrOx, and the like as the upper electrode material.

Thereafter, as illustrated in FIG. 3D, the upper electrode 27a is formed through the etchback or chemical mechanical polishing (CMP) process. At this time, the height of the upper electrode (27a) is adjusted to 5000 or more. This is to ensure the desired capacitance in the highly integrated cell.

Subsequently, a fourth insulating layer 28 is formed on the upper electrode 27a and the third insulating layer pattern 26a. At this time, the fourth insulating layer 28 is a silicon nitride film and the reason for forming the silicon nitride film. First, to protect the upper electrode 27a when removing the third insulating layer pattern 26a between neighboring upper electrodes, its thickness is at least twice as thick as that of the second insulating layer 25. To form. Second, after the deposition of the ferroelectric thin film and the lower electrode material, during the etching process for forming the lower electrode, the upper electrode 27a and the lower electrode are simultaneously exposed to cause redeposition of the etched electrode material. In this case, since it is electrically conductive and cannot function as a capacitor, a silicon nitride film is formed in advance to solve this problem, so that the upper electrode 27a is not exposed during the etching process after the ferroelectric thin film and the lower electrode material are deposited. to be.

Subsequently, as shown in FIG. 3E, the fourth insulating layer 28 is formed of the fourth insulating layer pattern 28a so that only a portion on the upper electrode 27a remains, and then the fourth insulating layer pattern 28a is formed. The third insulating layer pattern 26a is etched to expose the surface of the second insulating layer 25 using the mask.

Then, for example, BST is deposited on the front surface as a ferroelectric material by CVD. Thereafter, heat treatment is performed in a nitrogen atmosphere of 700 to 800 ° C. to crystallize the BST thin film. And in order to supply oxygen escaped from the BST surface during the crystallization process, heat treatment is performed in an oxygen atmosphere of 350 ~ 450 ℃.

Thus, the ferroelectric thin film 29 having an optimal Perovskite structure is formed.

Here, the heat treatment step is a step of depositing a ferroelectric material, in the first step in addition to the heat treatment in a high temperature nitrogen atmosphere of 700 ~ 800 ℃ and heat treatment in a low temperature oxygen atmosphere of 350 ~ 450 ℃ in the first step After the ferroelectric material is deposited, the second step may be performed after completing the capacitor electrode.

Instead of the heat treatment in the oxygen atmosphere, it is possible to perform N ₂ O plasma treatment at low temperature.

As shown in FIG. 3F, after the first lower electrode material layer is formed on the ferroelectric thin film 29, the first lower electrode 30 is formed only on the side surface of the ferroelectric thin film 29 in the vertical direction through anisotropic etching. Form. Here, the first lower electrode material layer uses the same material as the upper electrode material.

As shown in FIG. 3G, an etching process is performed using the first lower electrode 30 as a mask to form side surfaces of the fourth insulating layer pattern 28a and the upper electrode 27a and the first lower electrode 30. Only the ferroelectric thin film 29a below is left. At this time, since the fourth insulating layer pattern 28a is formed on the upper electrode 27a, the upper electrode 27a is not exposed and etched while the ferroelectric thin film 29a is formed. . This means that the re-oxidation phenomenon in which the upper electrode is etched and redeposited on the lower electrode does not occur. As shown in FIG. 3H, the ferroelectric thin film 29a is continuously exposed as a mask. The second insulating layer 25 is removed to form a second insulating layer pattern 25a. During this process, the titanium nitride layer 24b over the plug 23 is exposed and the fourth insulating layer pattern ( 28a) is etched to a predetermined thickness to form 28b, and the ferroelectric thin film 29a is also etched to the same thickness as the second insulating layer pattern 28a to form 29b.

As shown in FIG. 3I, after forming the second lower electrode material layer on the entire surface including the exposed titanium nitride layer 24b, the second lower electrode 31 is formed using an etch back or CMP process. Then, the semiconductor device manufacturing process according to the present invention is completed. In this case, the second lower electrode 31 is electrically connected to the first lower electrode 30 and also to the titanium nitride layer 24b of the barrier layer 24.

As described above, the semiconductor device of the present invention and the manufacturing method thereof have the following effects.

First, as the cell size decreases and the aspect ratio increases, the etching profile of the electrode, which is one of the most important processes, can be improved. That is, when forming the electrode using a noble metal, there was a limit to apply to a very small cell size due to the inclination of the electrode after etching, but after depositing the silicon oxide film is patterned and electrode using a CVD process Filling the material allows the formation of electrodes without slopes.

Second, it is possible to prevent the oxidation of the lower electrode barrier layer that may occur during ferroelectric thin film deposition and heat treatment. That is, the lower electrode barrier layer is used to prevent the reaction between the lower electrode and the polysilicon plug. The barrier layer is oxidized during the high temperature heat treatment to improve the characteristics after deposition of the ferroelectric thin film, but the desired capacitance cannot be obtained. Even after the nitride film is deposited and the ferroelectric thin film is deposited and heat treated in an oxygen atmosphere, the silicon nitride film serves as a blocking layer to prevent oxidation of the barrier layer.

Third, the reliability of the device can be improved by proceeding to two steps of the high temperature heat treatment for crystallization of the ferroelectric thin film and the low temperature heat treatment to improve the liquid current characteristics.

Fourth, the dielectric properties of the capacitor may be improved by forming a ferroelectric thin film having a uniform composition by preventing a change in composition due to the deposition of the ferroelectric thin film.

Claims (9)

Semiconductor substrates; A first insulating layer formed on the substrate with contact holes; A plug and a barrier layer sequentially stacked in the contact hole; A second insulating layer formed in a predetermined region on the first insulating layer; An upper electrode selectively formed on the second insulating layer; A ferroelectric thin film heat-treated in an oxygen atmosphere after the first heat treatment in the nitrogen atmosphere formed on the upper electrode side and the second insulating layer; A first lower electrode formed on the ferroelectric thin film; And a second lower electrode formed on the barrier layer and integrally formed with the first lower electrode. The semiconductor device according to claim 1, wherein the barrier layer uses one of Ti / TiN laminated films or Ti / TiSiN or Ti / TiAlN. The semiconductor device of claim 1, wherein a material of the upper electrode and the first and second lower electrodes is any one of Pt, Ru, RuOx, and IrOx. Forming a first insulating layer having a contact hole on the semiconductor substrate; Sequentially forming a plug and a barrier layer in the contact hole; Forming a third insulating layer pattern by depositing a second insulating layer and a third insulating layer on the first insulating layer and the barrier layer, and selectively removing the third insulating layer; Forming an upper electrode between the third insulating layer patterns; Forming a fourth insulating layer over the upper electrode and the third insulating layer pattern; Removing the fourth insulating layer leaving portions other than the upper electrode, and removing the third insulating layer pattern; Forming a ferroelectric thin film on the entire surface of the second insulating layer including the upper electrode and the fourth insulating layer; First heat treating in a nitrogen atmosphere to crystallize the ferroelectric thin film; Secondary heat treatment in an oxygen atmosphere; Forming a first lower electrode on a side of the ferroelectric thin film; Removing the ferroelectric thin film using the first lower electrode as a mask, removing the second insulating layer so that the barrier layer is exposed, and removing the fourth insulating layer by a predetermined thickness; And forming a second lower electrode integral with the first lower electrode on the barrier layer. The method of claim 4, wherein the heat treatment temperature is 700 to 800 ° C. during the heat treatment in the nitrogen atmosphere. The method of claim 4, wherein the heat treatment temperature is performed at 350 ° C. to 450 ° C. during the heat treatment in the oxygen atmosphere. The method of claim 4, wherein the secondary heat treatment is performed in an N ₂ O atmosphere. Forming a first insulating layer having a contact hole on the semiconductor substrate; Sequentially forming a plug and a barrier layer in the contact hole; Forming a third insulating layer pattern by depositing a second insulating layer and a third insulating layer on the first insulating layer and the barrier layer, and selectively removing the third insulating layer; Forming an upper electrode between the third insulating layer patterns; Forming a fourth insulating layer over the upper electrode and the third insulating layer pattern; Removing the fourth insulating layer leaving portions other than the upper electrode, and removing the third insulating layer pattern; Forming a ferroelectric thin film on the entire surface of the second insulating layer including the upper electrode and the fourth insulating layer; First heat treating in a nitrogen atmosphere to crystallize the ferroelectric thin film; Forming a first lower electrode on a side of the ferroelectric thin film; Removing the ferroelectric thin film using the first lower electrode as a mask, removing the second insulating layer so that the barrier layer is exposed, and removing the fourth insulating layer by a predetermined thickness; Forming a second lower electrode integral with the first lower electrode on the barrier layer; A semiconductor device manufacturing method comprising the step of performing a second heat treatment in an oxygen atmosphere. The method of claim 4, wherein the first and third insulating layers use a silicon oxide film, and the second and fourth insulating layers use a silicon nitride film.