KR100280503B1 - How to Form Storage Nodes for Cell Capacitors - Google Patents
How to Form Storage Nodes for Cell Capacitors Download PDFInfo
- Publication number
- KR100280503B1 KR100280503B1 KR1019980040358A KR19980040358A KR100280503B1 KR 100280503 B1 KR100280503 B1 KR 100280503B1 KR 1019980040358 A KR1019980040358 A KR 1019980040358A KR 19980040358 A KR19980040358 A KR 19980040358A KR 100280503 B1 KR100280503 B1 KR 100280503B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- etching
- oxide film
- mask material
- forming
- Prior art date
Links
- 238000003860 storage Methods 0.000 title abstract description 28
- 239000003990 capacitor Substances 0.000 title abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 239000000126 substance Substances 0.000 abstract description 4
- 150000001805 chlorine compounds Chemical class 0.000 abstract description 3
- 238000007517 polishing process Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910010037 TiAlN Inorganic materials 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910008486 TiSix Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 셀 커패시터의 스토리지 노드 형성방법에 관한 것으로, 종래에는 배리어층의 형성공정이 복잡하고, 화학기계적 연마공정을 사용함에 따라 제조비용이 상승하는 문제점과; 염소 화합물을 사용하여 스토리지 노드의 식각이 이루어지므로, 식각 프로파일의 경사가 완만해지고, 배리어층과 산화막의 식각선택비를 제어할 수 없는 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부에 산화막을 형성한 후, 그 산화막 상에 콘택 홀을 형성하는 공정과; 상기 콘택 홀이 형성된 산화막의 상부 전면에 제1폴리실리콘을 증착한 후, 에치백하여 콘택 홀을 채우는 공정과; 상기 제1폴리실리콘 및 산화막의 상부에 제2폴리실리콘을 증착하여 실리사이드층을 형성하는 공정과; 상기 실리사이드층의 상부에 Pt를 증착한 후, 그 Pt층의 상부에 마스크물질을 형성하는 공정과; 상기 마스크물질을 감광막을 사용하여 패터닝하는 공정과; 상기 패터닝된 마스크물질을 적용하여 상기 Pt층을 식각하는 공정과; 상기 Pt층의 식각에 의해 노출된 실리사이드층과 상기 마스크물질을 등방성 플라즈마를 이용하여 제거하는 공정으로 이루어지는 셀 커패시터의 스토리지 제조방법을 제공하여 배리어층의 형성이 단순하고, 스토리지 노드의 식각 프로파일이 경사지게 유지되며, 실리사이드층을 식각할 때, 산화막과의 식각선택비가 우수한 효과가 있다.The present invention relates to a method for forming a storage node of a cell capacitor, which is a complicated process of forming a barrier layer, and a manufacturing cost increases by using a chemical mechanical polishing process; Since the storage node is etched using the chlorine compound, the inclination of the etch profile is gentle and there is a problem in that the etching selectivity of the barrier layer and the oxide layer cannot be controlled. Therefore, the present invention provides a process for forming a contact hole on an oxide film after forming an oxide film on the semiconductor substrate; Depositing first polysilicon on the entire upper surface of the oxide film on which the contact hole is formed, and then etching back to fill the contact hole; Depositing a second polysilicon on the first polysilicon and the oxide film to form a silicide layer; Depositing Pt on top of the silicide layer, and then forming a mask material on the Pt layer; Patterning the mask material using a photosensitive film; Etching the Pt layer by applying the patterned mask material; By providing a method of manufacturing a cell capacitor storage method comprising a process of removing the silicide layer and the mask material exposed by the etching of the Pt layer using an isotropic plasma, the formation of the barrier layer is simple and the etching profile of the storage node is inclined. When the silicide layer is etched, the etching selectivity with the oxide film is excellent.
Description
본 발명은 셀 커패시터의 스토리지 노드 형성방법에 관한 것으로, 특히 고유전막 커패시터 구조의 스토리지 노드로 사용되는 Pt와 배리어(barrier)층의 식각공정을 최적화할 수 있는 셀 커패시터의 스토리지 노드 형성방법에 관한 것이다.The present invention relates to a method of forming a storage node of a cell capacitor, and more particularly, to a method of forming a storage node of a cell capacitor capable of optimizing the etching process of a Pt and a barrier layer used as a storage node of a high-k dielectric capacitor structure. .
일반적으로, 반도체메모리의 고집적화에 대한 요구로 소자를 형성하는 셀의 면적을 최소화 하게 됨에 따라 셀에 형성되는 커패시터 스토리지 노드의 면적이 줄어들게 되어 커패시턴스의 감소가 초래되었다.In general, as the demand for high integration of semiconductor memories minimizes the area of the cell forming the device, the area of the capacitor storage node formed in the cell is reduced, resulting in a reduction in capacitance.
따라서, 일정한 커패시턴스를 확보하기 위해 스토리지 노드를 입체적구조로 형성하여 커패시터의 유효면적을 증가시키는 방법이 제시되었으나, 그 제조공정이 복잡하여 제조원가 상승 및 생산기간 장기화로 인한 생산력저하의 문제가 야기되었다.Therefore, a method of increasing the effective area of a capacitor by forming a storage node in a three-dimensional structure in order to secure a constant capacitance has been proposed, but the manufacturing process is complicated, resulting in a problem of a decrease in productivity due to an increase in manufacturing cost and a prolonged production period.
상기의 문제점을 해결하기 위하여 커패시터의 스토리지 노드와 플레이트 전극을 내열성 및 내산화성을 갖는 물질로 형성하고, 그 스토리지 노드와 플레이트 전극 사이에 고유전막을 채움으로써 커패시터를 제조하는 방법이 최근들어 각광받고 있다.In order to solve the above problems, a method of manufacturing a capacitor by forming a storage node and a plate electrode of a capacitor with a material having heat resistance and oxidation resistance, and filling a high dielectric film between the storage node and the plate electrode has recently been in the spotlight. .
상기의 스토리지 노드와 플레이트 전극에 적합한 물질로는 Pt, Ru 및 Pt 와 Ru의 산화물들을 들 수 있으며, 특히 일본의 회사들은 Pt의 식각기술이 어렵기 때문에 Ru 및 Pt 와 Ru의 산화물을 이용하여 스토리지 노드의 형성을 시도하고 있다.Suitable materials for the storage node and the plate electrode include Pt, Ru, and oxides of Pt and Ru. In particular, Japanese companies use the oxides of Ru and Pt and Ru to store the oxides because Pt etching is difficult. Attempting to form a node.
그러나, 우리나라의 경우에는 Pt 식각기술의 발달에 힘입어 Pt를 이용하여 스토리지 노드를 형성하고 있다. 이때, Pt는 산화막과 접착특성이 취약하고, Ba Sr TiO(이하, BST)로 구성된 고유전막을 증착할 때, 산소를 투과하는 등의 단점이 있다.However, in Korea, Pt is used to form storage nodes due to the development of Pt etching technology. At this time, Pt has a disadvantage in that the adhesion property of the oxide film is weak and transmits oxygen when depositing a high dielectric film composed of Ba Sr TiO (hereinafter, BST).
상기한 바와같은 단점들을 보완하기 위하여 배리어층을 사용하게 되었다.The barrier layer has been used to compensate for the above disadvantages.
따라서, 스토리지 노드를 형성하기 위한 식각기술은 Pt와 배리어층의 식각기술로 구분된다. 이와같은 종래 커패시터 제조의 일 실시예로 텍사스 인스트루먼츠사의 커패시터 제조공정을 도1의 단면도를 참조하여 설명하면 다음과 같다.Therefore, an etching technique for forming a storage node is divided into an etching technique of a Pt and a barrier layer. Referring to the cross-sectional view of Figure 1 as a capacitor manufacturing process of Texas Instruments as an embodiment of such a conventional capacitor as follows.
먼저, 반도체기판(미도시) 상에 산화막(1)을 증착한 후, 전자빔 리소그래피(electron beam lithography) 및 이온반응성 식각(reactive ion etching : RIE) 방법으로 지름 0.15㎛의 콘택 홀을 형성한다.First, an oxide film 1 is deposited on a semiconductor substrate (not shown), and then contact holes having a diameter of 0.15 μm are formed by electron beam lithography and reactive ion etching (RIE).
그 다음, 상기 콘택 홀이 형성된 산화막의 상부에 인이 도핑된 폴리실리콘(2)을 200㎚의 두께로 증착한 후, 에치백(etch back) 공정을 수행하여 폴리실리콘(2)이 상기 산화막(1)의 윗면으로부터 100㎚가 되도록 콘택 홀을 채운다.Subsequently, a polysilicon 2 doped with phosphorus is deposited to a thickness of 200 nm on the oxide film on which the contact hole is formed, and then an etch back process is performed to the polysilicon 2 to form the oxide film ( The contact hole is filled so that it may become 100 nm from the upper surface of 1).
그 다음, 상기 폴리실리콘(2)의 상부에 Ti를 증착한 후, 급속열처리(rapid thermal annealing : RTA) 공정을 수행하여 실리사이드(TiSix, 3)를 형성함으로써, 콘택저항을 줄이게 된다. 이때, 실리사이드(3)의 상부에 TiN층(미도시)이 형성된다.Then, after depositing Ti on the polysilicon (2), by performing a rapid thermal annealing (RTA) process to form a silicide (TiSix, 3), to reduce the contact resistance. At this time, a TiN layer (not shown) is formed on the silicide 3.
그 다음, 상기 TiN층을 제거한 후, TiAlN층(4)을 증착한 후, 화학기계적 연마공정(chemical mechanical polishing : CMP)을 수행하여 상기 콘택 홀을 채운다.Then, after the TiN layer is removed, the TiAlN layer 4 is deposited, followed by chemical mechanical polishing (CMP) to fill the contact hole.
그 다음, 상기 콘택 홀이 채워진 산화막(1)의 표면에 접착장벽층(5)으로 TiAlN을 5㎚의 두께로 증착한다. 이때, 접착장벽층(5)은 이후에 형성되는 Pt 스토리지 노드(6)와의 접착특성을 향상시키기 위하여 형성한다.Then, TiAlN is deposited to a thickness of 5 nm with the adhesive barrier layer 5 on the surface of the oxide film 1 filled with the contact hole. At this time, the adhesive barrier layer 5 is formed to improve the adhesive property with the Pt storage node 6 formed later.
그 다음, 상기 접착매몰층(5)의 상부에 Pt를 1000Å∼3000Å의 두께로 증착한 후, 사진식각공정을 통해 패터닝하여 스토리지 노드(6)를 형성한다. 이때, 사진식각공정에 사용되는 식각 화합물(chemistry)로는 염소(chlorine) 화합물을 사용한다.Next, Pt is deposited on the adhesive buried layer 5 to a thickness of 1000 Å to 3000 Å, and then patterned through a photolithography process to form a storage node 6. In this case, a chlorine compound is used as an etching compound (chemistry) used in the photolithography process.
그 다음, 상기 스토리지 노드(6)의 상부에 BST 고유전막(7)과 Pt 플레이트 전극(8)을 증착한 후, 사진식각공정을 통해 패터닝하여 공정을 완료한다.Next, the BST high-k dielectric layer 7 and the Pt plate electrode 8 are deposited on the storage node 6, and then patterned through a photolithography process to complete the process.
그러나, 상기한 바와같은 종래 셀 커패시터의 스토리지 노드 형성방법은 TiAlN층의 2회 증착으로 배리어층을 형성함에 따라 공정이 복잡해지는 문제점과; 화학기계적 연마공정을 사용함에 따라 제조비용이 상승하는 문제점과; 스토리지 노드의 식각 화합물로 염소 화합물을 사용함에 따라 식각 프로파일(profile)의 경사가 완만해지는 문제점과; 실리사이드의 상부에 형성되는 TiN층을 제거할 때, 산화막의 손실을 제어할 수 없는 문제점이 있었다.However, the storage node forming method of the conventional cell capacitor as described above has a problem in that the process becomes complicated as the barrier layer is formed by two depositions of the TiAlN layer; Manufacturing cost increases with the use of chemical mechanical polishing processes; Using a chlorine compound as an etching compound of the storage node causes the slope of the etching profile to be gentle; When removing the TiN layer formed on top of the silicide, there is a problem that the loss of the oxide film cannot be controlled.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 고유전막 커패시터 구조의 스토리지 노드로 사용되는 Pt와 배리어층의 식각공정을 최적화하여 상기한 종래기술의 제반 문제점들을 해결할 수 있는 셀 커패시터의 스토리지 노드 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to optimize the etching process of Pt and barrier layer used as a storage node of a high-k dielectric capacitor structure, thereby solving the problems of the related art. The present invention provides a method of forming a storage node of a cell capacitor that can solve these problems.
도1은 종래의 셀 커패시터를 보인 단면도.1 is a cross-sectional view showing a conventional cell capacitor.
도2는 본 발명의 일 실시예에 따른 셀 커패시터를 보인 단면도.Figure 2 is a cross-sectional view showing a cell capacitor according to an embodiment of the present invention.
도3은 본 발명의 일 실시예를 실험을 통해 보인 그래프도.Figure 3 is a graph showing an embodiment of the present invention through an experiment.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:산화막 12:폴리실리콘11: oxide film 12: polysilicon
13:실리사이드층 14,16:Pt층13: silicide layer 14, 16: Pt layer
15:고유전막15: dielectric film
상기한 바와같은 본 발명의 목적을 달성하기 위한 스토리지 노드 형성방법의 바람직한 일 실시예는 반도체기판의 상부에 산화막을 형성한 후, 그 산화막 상에 콘택 홀을 형성하는 공정과; 상기 콘택 홀이 형성된 산화막의 상부 전면에 제1폴리실리콘을 증착한 후, 에치백하여 콘택 홀을 채우는 공정과; 상기 폴리실리콘 및 산화막의 상부에 제2폴리실리콘을 증착하여 실리사이드층을 형성하는 공정과; 상기 실리사이드층의 상부에 Pt를 증착한 후, 그 Pt층의 상부에 마스크물질을 형성하는 공정과; 상기 마스크물질을 감광막을 사용하여 패터닝하는 공정과; 상기 패터닝된 마스크물질을 적용하여 상기 Pt층을 식각하는 공정과; 상기 Pt층의 식각에 의해 노출된 실리사이드층과 상기 마스크물질을 등방성 플라즈마를 이용하여 제거하는 공정을 포함하여 이루어짐을 특징으로 한다. 이하, 상기한 바와같은 본 발명의 일 실시예를 도2를 참조하여 상세히 설명한다.One preferred embodiment of the storage node forming method for achieving the object of the present invention as described above comprises the steps of forming an oxide film on top of the semiconductor substrate, and then forming contact holes on the oxide film; Depositing first polysilicon on the entire upper surface of the oxide film on which the contact hole is formed, and then etching back to fill the contact hole; Depositing a second polysilicon on the polysilicon and the oxide film to form a silicide layer; Depositing Pt on top of the silicide layer, and then forming a mask material on the Pt layer; Patterning the mask material using a photosensitive film; Etching the Pt layer by applying the patterned mask material; And removing the silicide layer and the mask material exposed by the etching of the Pt layer using an isotropic plasma. Hereinafter, an embodiment of the present invention as described above will be described in detail with reference to FIG.
먼저, 반도체기판(미도시)의 상부에 산화막(11)을 형성한 후, 그 산화막(11) 상에 콘택 홀을 형성한다.First, an oxide film 11 is formed on a semiconductor substrate (not shown), and then contact holes are formed on the oxide film 11.
그 다음, 상기 콘택 홀이 형성된 산화막(11)의 상부 전면에 폴리실리콘(12)을 증착한 후, 에치백하여 콘택 홀을 채운다.Next, the polysilicon 12 is deposited on the entire upper surface of the oxide film 11 on which the contact hole is formed, and then etched back to fill the contact hole.
그 다음, 상기 폴리실리콘(12) 및 산화막(11)의 상부에 폴리실리콘(미도시)을 증착한 후, 열처리하여 TiSix의 실리사이드층(13)을 형성한다. 이때, TiSix 실리사이드층(13)은 상기 폴리실리콘(미도시)의 상부에 Ti를 증착한 후, 급속열처리 공정을 통해 약 500Å의 두께로 형성하는 것이 바람직하다.Next, polysilicon (not shown) is deposited on the polysilicon 12 and the oxide film 11, and then heat-treated to form a silicide layer 13 of TiSix. At this time, the TiSix silicide layer 13 is preferably formed to have a thickness of about 500 kPa through a rapid heat treatment process after depositing Ti on the polysilicon (not shown).
그 다음, 상기 실리사이드층(13)의 상부에 Pt(14)를 2000Å∼3000Å의 두께로 증착한 후, 그 Pt층(14)의 상부에 마스크물질(미도시)을 형성한다. 이때, 마스크물질은 Ti계열을 사용한다.Then, Pt 14 is deposited on the silicide layer 13 to a thickness of 2000 kPa to 3000 kPa, and a mask material (not shown) is formed on the Pt layer 14. In this case, the mask material uses a Ti series.
그 다음, 상기 마스크물질을 감광막(미도시)을 사용하여 패터닝한다. 이때, 마스크물질의 패터닝으로 인해 이후의 공정에서 스토리지 노드가 형성되는 영역을 제외한 영역의 Pt층(14)이 노출된다.The mask material is then patterned using a photoresist (not shown). At this time, due to the patterning of the mask material, the Pt layer 14 in the region other than the region where the storage node is formed in the subsequent process is exposed.
그 다음, 상기 감광막을 제거한 후, 패터닝된 마스크물질을 적용하여 Pt층(14)을 식각한다. 이때, Pt층(14)의 식각은 O2와 Br의 혼합가스를 사용한다.After removing the photoresist, the Pt layer 14 is etched by applying a patterned mask material. At this time, the etching of the Pt layer 14 uses a mixed gas of O 2 and Br.
그 다음, 상기 Pt층(14)의 식각에 의해 노출된 실리사이드층(13) 및 상기 마스크물질을 등방성 플라즈마를 이용하여 제거함으로써, 셀 커패시터의 스토리지 노드를 형성한다.Next, the silicide layer 13 and the mask material exposed by the etching of the Pt layer 14 are removed using an isotropic plasma to form a storage node of a cell capacitor.
이후에 상기 스토리지 노드가 형성된 산화막(11)의 상부 전면에 고유전막(15) 및 Pt층(16)의 플레이트 전극을 증착하고, 패터닝하여 셀 커패시터를 제조한다.Thereafter, a plate electrode of the high-k dielectric layer 15 and the Pt layer 16 is deposited on the upper surface of the oxide layer 11 on which the storage node is formed, and patterned to manufacture a cell capacitor.
상기한 바와같은 본 발명은 Pt층(14)를 식각할 때는 그 식각 프로파일이 경사지게 유지되면서 배리어층인 실리사이드층(13)에서 종료되어야 하며, 또한 실리사이드층(13)을 식각할 때는 그 실시사이드층(13)과 Pt층(14) 및 산화막(11)과의 식각선택성이 우수한 식각물질을 사용하여야 한다.The present invention as described above should be terminated in the silicide layer 13, which is a barrier layer, while the etching profile remains inclined when etching the Pt layer 14, and the embodiment side layer when the silicide layer 13 is etched. An etching material excellent in etching selectivity between (13) and the Pt layer 14 and the oxide film 11 should be used.
따라서, 실험을 통해 상기한 바와같은 Pt층(14), Ti계열의 마스크물질 및 실리사이드층(13) 간의 선택비와 실리사이드층(13), Pt층(14) 및 산화막(11) 간의 선택비를 구한 결과를 도3의 그래프도에 도시하였다.Therefore, through the experiments, the selectivity between the Pt layer 14, the Ti-based mask material and the silicide layer 13 and the selectivity between the silicide layer 13, the Pt layer 14 and the oxide film 11 are determined. The obtained result is shown in the graph of FIG.
상기 도3의 그래프도에 나타난 바와같이 Pt층의 식각에 있어서는 HBr 과 O2의 혼합가스가 최적의 식각화합물임을 알수 있고, 실리사이드층의 식각에 있어서는 Cl2가 최적의 식각화합물임을 알수 있다.As shown in the graph of FIG. 3, it can be seen that the mixed gas of HBr and O 2 is an optimal etching compound in the etching of the Pt layer, and that Cl 2 is an optimum etching compound in the etching of the silicide layer.
상기한 바와같은 본 발명에 의한 셀 커패시터의 스토리지 노드 형성방법은 종래의 TiAlN층의 증착공정, 화학기계적 연마공정이 필요없어 공정이 단순해지고, 제조비용을 최소화할 수 있는 효과와; 스토리지 노드의 식각 프로파일이 경사지게 유지되어 공정의 효율을 향상시킬 수 있는 효과와; 실리사이드층을 식각할 때, 산화막과의 식각선택비가 우수하여 공정의 신뢰성을 향상시킬 수 있는 효과가 있다.The method of forming a storage node of a cell capacitor according to the present invention as described above does not require a deposition process and a chemical mechanical polishing process of the conventional TiAlN layer, the process is simplified and the manufacturing cost can be minimized; An effect of maintaining the etch profile of the storage node to be inclined to improve the efficiency of the process; When etching the silicide layer, the etching selectivity with the oxide film is excellent, there is an effect that can improve the reliability of the process.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040358A KR100280503B1 (en) | 1998-09-28 | 1998-09-28 | How to Form Storage Nodes for Cell Capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980040358A KR100280503B1 (en) | 1998-09-28 | 1998-09-28 | How to Form Storage Nodes for Cell Capacitors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000021337A KR20000021337A (en) | 2000-04-25 |
| KR100280503B1 true KR100280503B1 (en) | 2001-02-01 |
Family
ID=19552251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980040358A KR100280503B1 (en) | 1998-09-28 | 1998-09-28 | How to Form Storage Nodes for Cell Capacitors |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100280503B1 (en) |
-
1998
- 1998-09-28 KR KR1019980040358A patent/KR100280503B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000021337A (en) | 2000-04-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100418573B1 (en) | Method for fabricating semiconductor device | |
| JPH09139481A (en) | Semiconductor device-oriented capacitor forming method utilizing selective tungsten nitride thin film | |
| US6162671A (en) | Method of forming capacitors having high dielectric constant material | |
| JP3651557B2 (en) | Method of etching platinum film of semiconductor device | |
| JPH10173154A (en) | Capacitor of semiconductor storage device and its manufacturing method | |
| KR0147639B1 (en) | High dielectronics capacitor electrode & its fabrication method | |
| KR100818267B1 (en) | Capacitor, memory device provided with the same and method for manufacturing thereof | |
| KR0138308B1 (en) | Method of fabricating interlayer connection in semiconductor device | |
| JPH09199686A (en) | Manufacture of capacitor of semiconductor device | |
| US20030042609A1 (en) | Semiconductor device and method of fabricating the same | |
| KR100280503B1 (en) | How to Form Storage Nodes for Cell Capacitors | |
| KR100685674B1 (en) | Method of fabrication capacitor | |
| JPH11289055A (en) | Manufacture of capacitor of semiconductor element | |
| JPH0964313A (en) | Wiring method for semiconductor device | |
| KR19980086199A (en) | Capacitor Formation Method of Semiconductor Memory Using Ferroelectric | |
| KR100190055B1 (en) | White electrode manufacturing method of semiconductor device | |
| US6558999B2 (en) | Method for forming a storage electrode on a semiconductor device | |
| KR0151058B1 (en) | Ferroelectric capacitor and its fabrication method | |
| US6511880B2 (en) | Capacitor of a semiconductor device and method of manufacturing the same | |
| KR100424192B1 (en) | Capacitor Manufacturing Method | |
| KR100359785B1 (en) | Semiconductor device and method for fabricating the same | |
| KR100721546B1 (en) | Capacitor and method of fabrication for the same | |
| KR100292693B1 (en) | Capacitor and Manufacturing Method | |
| KR0168339B1 (en) | Capacitor fabrication method | |
| KR100624926B1 (en) | Method of manufacturing a capacitor in a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20071025 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |