JP3666877B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

Technical field
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a dynamic random access memory (DRAM) or a polarization inversion type nonvolatile memory suitable for a large scale integrated memory.
Background art
To obtain a small-area and large-capacity capacitor suitable for large-scale integrated memory, Ta is used as a capacitor insulating film. ₂ O _Five It is effective to use a high dielectric insulating film such as BST or BST. If a ferroelectric insulating film such as PZT is used as a capacitor insulating film, a nonvolatile memory using spontaneous polarization can be obtained. Ferroelectric materials have extremely large relative dielectric constants of hundreds to thousands, and are effective as capacitor insulating films for dynamic random access memories.
When a high dielectric insulating film or a ferroelectric insulating film is used as a capacitor insulating film, it is important to select an electrode material. This is because if the electrode material is oxidized during the formation of the insulating film to form an insulator having a low dielectric constant, the capacitance of the capacitor is reduced.
Therefore, materials that are difficult to oxidize or materials in which oxides become conductors have been selected as electrode materials. Pt, Os, Au, etc. are those that are not easily oxidized, and Pt is generally used. RuO is a material that makes oxides conductive ₂ , IrO ₂ Ru and RuO as electrode materials ₂ , Ir, IrO ₂ Etc. are used.
As a capacitor structure using these insulating films and electrode materials, a structure as shown in FIG. 26 was reported in 1994 IEDM (International ELECTRON DEVICES Meeting) Technical Digest, P.843-P.846. This structure requires a plurality of masks and has a small effective area with respect to the entire area of the capacitor.
A technique for processing the upper electrode, the insulating film, and the lower electrode as shown in FIG. Res. Soc. Symp. Proc. Vol. 310 (1993) P.127-P.133, JP-A 05-299601 and JP-A 6-342774.
Further, as a Pt etching method, a technique for performing etching while suppressing re-deposition of Pt using a Ti mask is disclosed in Japanese Patent Laid-Open No. 5-89662.
Further, Japanese Patent Application Laid-Open No. 4-159679 discloses a technique for eliminating the distortion of the film thickness change due to polarization inversion by changing the area of the upper electrode and the lower electrode or by obliquely processing the end of the ferroelectric insulating film. It is disclosed in the publication.
Further, a technique for increasing a mask alignment margin and preventing a short circuit between electrodes by forming a sidewall after etching the lower electrode and the ferroelectric insulating film and then forming the upper electrode is disclosed in JP This is disclosed in JP-A-6-132482.
By the way, it has been recognized by the inventors of the present invention that there are the following problems when the structure shown in FIG. 27 is dry-etched.
As shown in FIG. 28, there is a problem that the sidewall adhesion film 113 mainly composed of an electrode material adheres to the sidewalls of the mask 112, the upper metal electrode 111, the capacitor insulating film 109, and the lower metal electrode.
This is remarkable when Pt or the like that is hardly oxidized is used as an electrode material. The fact that it is difficult to oxidize means that it is difficult to change to a volatile substance by a chemical reaction, and the electrode material is etched mainly by physical sputtering. This sputtered electrode material adheres to the side walls. RuO with oxide as conductor ₂ Or IrO ₂ However, since the volatility of the etching reaction product is low, the sidewall adhesion film 113 is also formed.
The side wall adhesion film 113 causes a short circuit of the capacitor and needs to be removed. However, wet cleaning using an acid or the like has a problem that the capacitor insulating film deteriorates.
Next, techniques proposed prior to the present invention will be described below as a solution to the above problems.
The proposed technique uses the fact that the etching rate in dry etching varies depending on the incident angle of ions, thereby removing the side wall deposits of the electrode material by self-cleaning during dry etching.
The principle of this self-cleaning is shown in FIG. The etch rate depends on the angle θ. This is R (θ). Since θ = 0 at the bottom surface, the etching rate at the bottom surface of the electrode material is R (0). If the proportion α of the etched electrode material adheres to the pattern sidewall, the deposition rate is αR (0). When the taper angle of the pattern is θ, the etching rate of the deposited film on the side wall is R (θ). Here, in order to obtain a cleaner side wall than the self-cleaning, it is necessary that the etching rate R (θ) on the side wall is higher than the thickness αR (0) / cos θ in the vertical direction of the adhesion film. That is, αR (0) / cos θ ≦ R (θ) is a condition for obtaining a clean sidewall. When this conditional expression is modified, R (θ) cos θ / R (0) ≧ α is established, the left side is a value that can be calculated from literature values, and the right side is a value that can be obtained from experiments. These calculated values and experimental values are shown in FIG. When α = 0.3 obtained from experimental values is used, it can be seen that when the taper angle is 75 degrees or less, dry etching without a sidewall adhesion film is possible by self-cleaning. That is, if the taper angle of the mask and the capacitor is 75 degrees or less, the problem of the side wall deposit can be solved.
FIG. 31 shows an improved capacitor structure based on the above knowledge. The semiconductor memory device shown in FIG. 31 is a fragmentary cross-sectional view of the stage where even the capacitors of the semiconductor memory are formed.
In FIG. 31, an element isolation region 102 is first formed on a semiconductor substrate 101. Next, a MOS transistor including the gate electrode 104 and the diffusion layer 105 is formed. Next, after flattening with the interlayer insulating film 105, the plug 106 is formed in the through hole of the interlayer insulating film 105 by using CVD and dry etching. On this plug, a barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by deposition of each layer and dry etching using a mask 112. Here, the mask 112 has a taper shape with a taper angle of 75 degrees or less in advance, and the taper angle of the capacitor can be formed to 75 degrees or less by dry etching processing based on Ar physical sputtering. In this way, a capacitor without a sidewall adhesion film can be formed. Since the completed capacitor has a tapered shape, depending on the film thickness of each layer of the capacitor, there is a limit in the degree of integration due to an increase in the bottom area of the capacitor, but there is no problem in practical use.
However, in a semiconductor memory such as a gigabit generation DRAM, it is a big problem to reduce the cell area and increase the degree of integration as the capacity increases.
Therefore, a typical object of the present invention is to overcome the above-described problems, and to provide a highly integrated and highly reliable semiconductor memory device.
Another representative object of the present invention is to provide a manufacturing method capable of realizing the semiconductor memory device described above by a relatively simple process.
Disclosure of the invention
According to a semiconductor memory device according to a representative embodiment of the present invention, a multilayer capacitor including a lower electrode, an insulating film, and an upper electrode is provided on a main surface of a semiconductor substrate, and charges are accumulated in the capacitor. Alternatively, in a semiconductor memory device having a function of storing an electric signal by inversion of polarization of an insulating film, a side wall spacer is provided on a side of the capacitor, and the upper electrode is positioned inside the side wall spacer. Yes. As a result, the side portion of the lower electrode and the side portion of the upper electrode are reliably electrically separated, so that there is no short circuit between the two electrodes, and a semiconductor memory device particularly suitable for high integration is obtained.
According to a method of manufacturing a semiconductor memory device having a multilayer capacitor according to a representative embodiment of the present invention, a sidewall spacer is formed after dry etching of an upper electrode and prior to dry etching of a lower electrode. It is a feature. As a result, the tapered portion of the sidewall spacer is free of side-wall deposits due to self-cleaning during dry etching, so that processing without a short circuit is possible, and semiconductor memory with high reliability and high integration is achieved. A device is obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an essential part of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.
3 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.
4 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.
FIG. 5 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 4.
6 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.
FIG. 7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 6.
FIG. 8 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 7.
FIG. 9 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.
FIG. 10 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 9.
FIG. 11 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.
FIG. 12 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 11.
FIG. 13 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 12.
FIG. 14 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 13.
FIG. 15 is a fragmentary cross-sectional view showing a semiconductor memory device according to a second embodiment of the present invention.
FIG. 16 is a fragmentary cross-sectional view showing a semiconductor memory device according to a third embodiment of the present invention.
FIG. 17 is a fragmentary cross-sectional view showing a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 18 is a fragmentary cross-sectional view showing a manufacturing process of a semiconductor memory device according to a fifth embodiment of the present invention.
FIG. 19 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the fifth embodiment of the present invention, following FIG. 18.
FIG. 20 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the sixth embodiment of the present invention, following FIG. 19.
FIG. 21 is a plan view showing a memory cell layout according to the sixth embodiment, in particular, to which the first embodiment is applied.
22 is a cross-sectional view taken along line AA ′ shown in FIG.
FIG. 23 is a plan view showing another memory cell layout according to the seventh embodiment, in particular to which the first embodiment is applied.
FIG. 24 is a plan view showing another memory cell layout according to the eighth embodiment, in particular, to which the first embodiment is applied.
FIG. 25 is a cross-sectional view taken along line AA ′ shown in FIG.
FIG. 26 is a sectional view of a principal part of a conventionally known memory cell.
FIG. 27 is a cross-sectional view of a principal part of another conventionally known memory cell.
FIG. 28 is a fragmentary cross-sectional view for explaining a problem in the method of manufacturing the memory cell shown in FIG. 27.
FIG. 29 is an explanatory view of how to obtain the clean sidewall condition, which is a means of the present invention.
FIG. 30 is a graph showing the range of clean sidewall conditions, which is a means of the present invention.
FIG. 31 is a cross-sectional view of the main part of the previously proposed capacitor.
BEST MODE FOR CARRYING OUT THE INVENTION
For a more detailed description of the present invention, reference will now be made to the accompanying drawings.
(Example 1)
A first embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a cross-sectional view of a main part of a semiconductor memory device (hereinafter referred to as a semiconductor memory) at a stage where capacitors are formed. The manufacturing process of this semiconductor memory will be briefly described as follows.
First, an element isolation region 102 is formed on the substrate 101. Next, a MISFET (insulated gate field effect transistor) is formed by the gate electrode 104 and the semiconductor region (diffusion layer) 103.
Next, after flattening with the interlayer insulating film 105, the plug 106 is formed using CVD and dry etching. A barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed on the plug 106 by dry etching using the same mask as the deposition of each layer. A barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed on the plug 106 by dry etching using the same mask as the deposition of each layer.
In this embodiment, the sidewall spacer 114 is formed after etching the upper electrode 111 and the capacitor insulating film 109, and then the lower metal electrode 108 and the barrier layer 107 are etched to form a capacitor. Since the side wall spacer 114 has a taper angle (θ), the attached electrode material is removed by self-cleaning at this portion, so that a capacitor having no sidewall adhesion film can be formed.
As is clear from this example, the completed multilayer capacitor has the side portion of the upper electrode 111 covered with the side wall spacer 114. That is, the upper electrode 111 is positioned inside the sidewall spacer 114.
The method for forming the capacitor will be specifically described with reference to cross-sectional views of relevant parts showing the manufacturing process shown in FIGS.
First, as shown in FIG. 2, an element isolation region 102 is formed in a semiconductor substrate (for example, a P-type Si substrate or a P-type well region) 101. Specifically, the element isolation region 102 is made of an oxide film selectively formed on the main surface of the semiconductor substrate 101 by a LOCOS (Local Oxidation of Silicon) technique. Next, a MISFET is formed by the gate electrode 104 and the diffusion layer 103. Although the gate oxide film under the gate electrode 104 is omitted in FIG. 2, it is formed to a predetermined thickness prior to the formation of the gate electrode.
Next, an interlayer insulating film, for example, an SOG (Spin On Glass) film 105 is coated and planarized by a reflow process, and then a through hole is provided in the interlayer insulating film 105. Then, the W (tungsten) plug 106 is formed so as to fill the through hole provided in the interlayer insulating film 105 by using the CVD technique and the etch back by dry etching. A capacitor is formed on the plug 106. That is, a barrier layer 107, a lower metal layer 115, an insulating film layer 116, an upper metal layer 117, a hard mask layer 118, and a resist mask 119 are sequentially formed on the plug 106. When Pt is used for the lower metal layer and the upper metal layer, if P is used for the hard mask layer 118, a Pt / W selection ratio of 2 or more can be obtained by etching using Ar plasma. The hard mask layer 118 has SiO ₂ And Si ₂ N _Three Or Al ₂ O _Three An insulator such as Al or Cu may be used. The barrier layer 107 is preferably TiN. As the insulating film layer 116, Ta ₂ O _Five In addition to high dielectrics such as BST and ferroelectrics such as PZT and PLZT, SiO ₂ And Si ₂ N _Three In the case of using a dielectric such as the above, there is an effect in the case where the electrode material forms a sidewall deposit by etching.
Next, as shown in FIG. 3, a hard mask 120 is formed. The hard mask 120 is processed to have a taper angle of 75 degrees or less. As a taper processing method, when a metal is used as a hard mask, taper processing can be performed if processing is performed under the condition that side etching is performed by dry etching, or processing may be performed by wet etching. When an insulator is used as a hard mask, it can be processed by time modulation dry etching in which deposition and dry etching are alternately performed, or by wet etching. For example, when using W as a hard mask, SF ₆ If the temperature of the substrate (semiconductor substrate) is etched near room temperature by dry etching using plasma, taper processing by side etching is possible. By controlling the amount of side etching by substrate temperature and by controlling ion energy by bias, The taper angle can be controlled.
Next, as shown in FIG. 4, the resist mask on the hard mask 120 is removed by an ashing process.
Next, as shown in FIG. 5, the upper metal layer (117) is dry-etched to form an upper metal electrode 111. When Pt is used as the upper metal layer, etching can be performed at an etching rate of 20 nm / min by sputtering with Ar gas under conditions of a pressure of 10 mTorr and RF 500 W using, for example, a parallel plate type dry etching apparatus. When W is used as the hard mask 120, 3 is obtained as the mask selection ratio under this condition. Even when using materials that are not easily oxidized such as Pt, Os, Pd, and Au as electrode materials, Ru, Ir, and RuO ₂ Or IrO ₂ Even when a material such as oxide that exhibits conductivity is used, dry etching may be performed by physical sputtering using a rare gas plasma such as Ar, or dry etching using a halogen-based gas containing F, Cl, Br, or the like. But you can. Even with dry etching by physical sputtering using Ar gas plasma with Pt, if the hard mask 120 has a taper angle of 75 degrees or less, dry etching without sidewall deposits on the sidewall of the hard mask 120 by self-cleaning during dry etching Can do.
Next, as shown in FIG. 6, the capacitor insulating film 109 is processed by etching. When sputtering using Ar plasma or the like is used for this etching, since the selection ratio with the lower metal layer 115 is low, the base metal layer 115 is scraped off at the end of etching to form a sidewall adhesion film on the sidewall of the capacitor insulating film 109. However, there is no practical problem if the in-plane distribution of the etching rate is uniformly controlled. Also Cl ₂ And CF _Four And SF ₆ If a gas containing halogen such as the above, a mixed gas thereof, or a mixed gas with a rare gas is used, the selectivity with respect to the lower metal layer is increased, and the underlying metal layer 115 is less likely to be scraped. Further, as will be described later, before the etching of the capacitor insulating film 109 is completed, the process may proceed to the next step. When using PZT as the capacitor insulating film, for example, Ar and CF are used as etching gases. _Four Etching can be performed at a PZT etch rate of 40 nm / min with a parallel plate type etching apparatus at an RF of 500 W and a pressure of 10 mTorr using a gas mixed with a gas of 1: 1. When W is used as the hard mask 120, a mask-to-mask selection ratio of 4 under this condition is obtained. When Pt is used as the lower metal layer, a selectivity ratio of 3 to the lower metal under this etching condition is obtained.
Next, as shown in FIG. 7, an insulating film layer 121 is deposited by the CVD method. Specifically, the insulating film layer 121 is made of SiO. ₂ It is a membrane. Then, sidewall spacers 114 are formed by etching back as shown in FIG. The material of the insulating film layer 121 is SiO ₂ Besides Si _Three N _Four , Al ₂ O _Three , TiO ₂ , Ta ₂ O _Five A material that can be deposited by CVD is selected.
Next, as shown in FIG. 9, the lower metal layer (115) is etched to form the lower metal electrode. At this time, the sidewall adhesion film 113 adheres to the vertical part of the pattern, but the sidewall adhesion film does not adhere to the sidewalls of the hard mask 120 and the side wall spacer 114 because of the taper angle. For example, side wall spacer 114 has SiO ₂ When Pt is used as the lower metal layer using Ar, Pt / SiO is used for sputtering with Ar gas plasma. ₂ Since the etch rate ratio is about 1, the side wall spacer 114 is also etched during the lower Pt etching. If the side wall spacer 114 is etched by the height of the hard mask 120 during this lower Pt etching, the side wall spacer 114 is formed only beside the upper metal electrode 111 and the capacitor insulating film 109 as shown in FIG. Can be processed. Such processing controls the height of the hard mask when the side wall spacer shown in FIG. 8 is formed (this can be controlled by the deposited film thickness of the hard mask layer), and CF _Four Pt / SiO by adding gas etc. ₂ It can be formed by controlling the etch rate ratio. The conditions and film thickness for this processing differ depending on the material of the lower electrode, the material of the side wall spacer, the etching gas and the etching apparatus, but it can be processed by controlling the thickness of the hard mask layer and the etching rate ratio. .
The side wall adhesion film 113 does not need to be removed because there is no side wall spacer 114, so it does not have to be removed. However, it can be removed to improve process reliability and suppress product characteristic variations. desirable. Therefore, in this embodiment, as shown in FIG. 10, the sidewall adhesion film was removed by wet processing. As a treatment method, aqua regia is effective in the case of PT deposits, and in the case of other substances, solution treatment may be performed according to the type. Further, downflow plasma treatment, vapor treatment, etc. are also effective depending on the type of the lower metal material. When Pt is used as in this embodiment, aqua regia is effective, and when a metal material such as W is used as the hard mask, the hard mask is also removed at the same time.
Next, as shown in FIG. 11, the barrier layer 107 is etched. The order of this etching and removal of the sidewall adhesion film may be interchanged.
Next, as shown in FIG. 12, an insulating film layer 122 is deposited. If a reflow film such as BPSG or SOG is used as the deposited film, a flat surface necessary for the following wiring process can be formed at this point. Since a flat surface can be formed by using an etch back technique, a CMP (Chemical Mechanical Polishing) technique, or the like, a sputter insulating film or a CVD insulating film may be used.
Next, as shown in FIG. 13, the insulating film layer 122 is processed by etching or CMP until the upper metal electrode 111 is exposed.
Next, as shown in FIG. 14, a plate electrode 123 is formed. The plate electrode 123 is processed for wiring as necessary. Furthermore, a DRAM device is formed by performing necessary wiring processing.
By using the manufacturing method described above, it is possible to form a multilayer capacitor that does not have a short circuit due to a sidewall adhesion film even when a material with low volatility of an etching reaction product is used as an electrode material. A highly integrated and highly reliable semiconductor memory can be formed without degrading the characteristics of the high dielectric / ferroelectric insulator by using a simple electrode material.
(Example 2)
A second embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 15, even if the sidewall spacer 114 is formed immediately after the etching of the upper metal electrode 111 and the capacitor insulating film 109 and the lower metal electrode 108 are subsequently etched, Short circuit between the upper metal electrode 111 and the lower metal electrode 108 due to 113 can be prevented. In this example, since the capacitor insulating film 109 is in contact with the sidewall adhesion film 113, the electrical characteristics of the capacitor insulation film 109 may be deteriorated when the sidewall adhesion film 113 is removed by wet processing. A memory is formed with the film 113 left. If the sidewall adhesion film 113 can be removed without deteriorating the electrical characteristics, the treatment may be performed.
According to the present embodiment, the capacitor insulating film 109 and the lower metal electrode 108 have substantially the same size, and the length of the lower side of the upper metal electrode 111 is shorter than the length of the upper side of the insulating film 109. It is said. That is, in FIG. 15, the relationship is Le <Li.
(Example 3)
A third embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 16, a sidewall spacer 114 is formed during the etching process of the capacitor insulating film 109. In the method described in the third embodiment, when the in-plane uniformity of etching is poor, the base metal film is scraped at the end of the etching of the capacitor insulating film 109, and the upper metal electrode and the lower metal are formed before forming the sidewall spacer. A short circuit may occur between the layers due to the sidewall adhesion film.
According to this embodiment, the length of the upper side of the insulating film 109 is shorter than the length of the lower side of the insulator 109. That is, in FIG. 16, there is a relationship of Lbi> Lui.
By adopting the structure of this embodiment, this short-circuit problem can be prevented.
(Example 4)
A fourth embodiment of the present invention will be described with reference to FIG.
FIG. 17 shows a structure formed by the method described in Example 1 except that the step of removing the sidewall adhesion film 113 is omitted. When the sidewall adhesion film 113 is a stable material such as Pt, it is not necessary to remove it, so that it can be manufactured at low cost by omitting the process.
(Example 5)
A fifth embodiment of the present invention will be described with reference to FIGS.
In the present embodiment, some steps are omitted from the method of the first embodiment. The omitted process is a process of flattening with a reflow film or CMP after the capacitor is formed by etching.
The semiconductor memory shown in FIG. 18 is formed by the following process.
An element isolation region 102 is formed on the semiconductor substrate 101, and a gate electrode (not shown in the figure) and a diffusion layer 103 are formed. Then, after forming the interlayer insulating film 105 and the plug 106, the upper metal electrode 111, the capacitor insulating film 109, the sidewall spacer 114, and the lower metal electrode 108 are formed using a film deposition and etching process, and a sidewall adhesion film removing process. Then, the barrier layer 107 is etched to form a capacitor. Up to this point, the method is the same as that described in the first embodiment.
Thereafter, a CVD insulating film layer 121 is deposited. As shown in the figure, the deposited film thickness is a film thickness of 1/2 or more of the interval between adjacent capacitors. As the material for the insulating film layer, the materials described in Embodiment 3 may be used. Next, as shown in FIG. 19, the capacitor isolation portion 124 is formed by etching back the CVD insulating film layer. Etching back a CVD insulating film layer deposited at least half of the capacitor interval reduces the step between the capacitors. Next, as shown in FIG. 20, a plate electrode 123 is formed. Since the step is relaxed by the capacitor separation portion 124, the plate electrode 123 can be formed as a highly reliable plate electrode that does not break even when a sputtering method is used. In order to alleviate the level difference, the CVD insulating film layer may be thickened. However, if the thickness is increased, the processing time of the deposition and etching steps becomes long and the throughput decreases, but there is no problem in practical use. In addition, if the CVD insulating film layer is thinner than 1/2, the effect of reducing the step is reduced. However, in the case where the capacitor thickness is thin and the design is wide, the capacitor isolation portion 124 is not perpendicular to the capacitor side wall. It is effective because the steps are inclined. This embodiment is effective particularly when a fine and highly integrated memory is manufactured, when the height of the capacitor is approximately the same as the capacitor interval, and the step between the capacitors is steep. Even in such a case, processing can be performed without using time-consuming processes such as reflow and CMP, so that throughput can be increased.
(Example 6)
FIG. 21 shows an embodiment of the planar layout of the memory cell in the present invention.
This layout is a layout using a two-intersection cell and a COB (Capacitor Over Bitline) structure in which a capacitor is formed on a bit line. A transistor (not shown in the figure) of each memory cell is connected to a peripheral circuit (not shown) via a bit line 208. A connection portion between the transistor and the bit line 208 is a portion of the bit line plug 207 formed in a part of the active region 218. The operation of the transistor is controlled by a word line (gate electrode) 203. The word line (gate electrode) 203 is connected to a peripheral circuit (not shown). The transistor is connected to the capacitor unit 220 via a capacitor plug 211. The capacitor unit 220 is connected to a peripheral circuit (not shown) through the plate electrode 216.
The first feature of this planar layout is that one plate electrode 216 is wired for two word lines 203. With such a layout, the capacity of the plate electrode 216 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 216 can be easily controlled by a peripheral circuit. This facilitates nonvolatile memory operation using ferroelectricity. In this embodiment, an example in which one plate electrode is provided for two word lines has been described. However, the number of plate electrodes may be one plate electrode for one word line. One plate electrode may be provided for more than one word line. However, when the number of plate electrodes increases, it becomes difficult to increase the degree of integration, and when the number of plate electrodes decreases, the capacity of the plate electrodes increases and control by peripheral circuits becomes difficult. The optimum number of plate electrodes varies depending on the memory application.
The second feature of this planar layout is that the plate electrode 216 is wired in the same direction as the word line (gate electrode) 203. Therefore, when the potential of the plate electrode 216 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the word line 203.
FIG. 22 shows a cross sectional structure (cross section AA ′) of FIG. This cross-sectional structure will be described below.
An element isolating SiO2 202 is formed on the Si substrate 201. A MISFET composed of a gate oxide film (not explicitly shown), a word line (gate electrode) 203 and a diffusion layer 204 is formed in the element region. In this embodiment, the word line 203 is processed by dry etching using SiO2 222 as a mask, and SiO2 ₂ 222 is used as it is as an insulating protective film for the word line. This SiO ₂ Although it is not necessary to leave 222, if the structure of this embodiment is used, the removal step can be eliminated, and it also acts as a protective film when the gate electrode spacer 221 is formed. As the word line, doped poly Si often used as a normal gate electrode or silicide such as WSi, MoSi, CoSi may be used. Or metal materials, such as W and TiN, or those laminated films may be sufficient.
A gate electrode spacer 221 is formed on the word line (gate electrode) 203. Although this gate electrode spacer is not essential, it has the effect of relaxing the step and the effect of preventing electrical shorts, so that a highly reliable COB structure can be formed.
An insulating protective film 205 for word lines is formed on the word lines (gate electrodes) 203. This protective film is not necessarily required, but has an effect of preventing electrical short when dry etching for forming the bit line plug 207 and the capacitor plug 211, and the word line insulating protective film 205 The material is changed with the word line step flattening insulating film 206 (for example, Si _Three N _Four And SiO ₂ ), The above-described plug portion can be dry etched in a self-aligning manner by using highly selective dry etching between insulating films.
A step formed by the formation of the word line (gate electrode) 203 is flattened by a word line step flattening insulating film 206. As a material of this insulating film, a fluid insulating film (such as BPSG) or a CVD insulating film may be used. As a planarization method, reflow of a fluid insulating film, whole surface etch back by dry etching, polishing such as CMP, or a combination thereof may be used. In this embodiment, the word line step planarizing insulating film 206 is formed by polishing the BPSG reflow film with CMP. Since this film is easily etched by dry etching, an insulating protective film 223 for a planarizing insulating film is formed in this embodiment. If this film is formed by CVD or sputter deposition, a film denser than the reflow film can be formed. The material of the film is SiO ₂ And S _Three N _Four It may be used in a normal Si LSI process such as.
A bit line plug 207 is formed after the formation of the insulating protective film 223 for the planarization insulating film. In this embodiment, the bit line plug 207 is formed by forming a hole pattern by dry etching and then using n + poly Si by the CVD method. The bit line plug 207 may be made of a material such as TiN in addition to n + poly Si. As the bit line plug 207 is formed, a bit line 208 shown in FIG. 21 is also formed. As this material, a material such as n + poly Si, silicide, or a laminated film thereof may be used.
In this embodiment, the bit line insulating protective film 209 is formed after the bit line plug 207 and the bit line 208 (shown in FIG. 21) are formed. This film is not essential, but has the same effect as the insulating protection film 205 for word lines. Further, a bit line step flattening insulating film 210 is formed thereon. The formation method and material of this film may be considered in the same manner as the word line step flattening insulating film 206. Further, an insulating protective film 224 for the planarizing insulating film is formed on this film in this embodiment. This protective film is not essential, but has the same effect as the above-described insulating protective film for planarization insulating film 223. Furthermore, since this film becomes the base film in capacitor dry etching, Al ₂ O _Three When an insulating film containing Al atoms is used, highly selective dry etching can be performed in dry etching of capacitors. In this embodiment, Pt is used as the capacitor lower electrode 212. However, when Pt is dry-etched with an F-based gas, it can be processed in a shape closer to vertical than dry etching using Ar or Cl-based gas. At this time, if a material containing Al atoms is used as the underlayer, the reaction product AlF _Three Because of its low volatility, the etching resistance is high, so that highly selective dry etching can be performed. In this processing, if a material containing Al atoms such as Al is used as the mask material, Pt dry etching having a high selectivity with respect to the mask / underlayer can be performed.
After the formation of the planarization insulating film insulating protective film 224, a capacitor plug 211 is formed. In this formation, after the hole pattern is formed by dry etching, a conductive material is embedded in the hole pattern. As a material, n + poly Si used in the conventional Si LSI process may be used, or materials such as TiN, W, Ta, and Ti may be embedded by CVD. Also, Pt, Ru, Ir, Pd, Rh, Os, Hf, Zr and their oxides, which are compatible with ferroelectric insulating films, are conductive (for example, RuO ₂ , IrO ₂ ) Etc. may be used. Furthermore, you may use those laminated films. RuO ₂ Or IrO ₂ If a CVD process such as MOCVD method is used, it can be formed without disconnection in the hole pattern. If Ru or Ir is stacked on top of it, materials such as Ru and Ir can be used against oxygen. Since it functions as a barrier layer, it is possible to improve the oxidation resistance in the subsequent steps.
After the capacitor plug 211 is formed, the capacitor upper electrode 214, the capacitor insulating film 213, the sidewall spacer 217, the capacitor lower electrode 212, and the barrier metal 219 are formed by the process described in the third embodiment. As described in Example 3, the Pt etching is Ar sputtering using the W hard mask, and the PZT etching is CF. _Four It may be formed by collective dry etching with + Ar gas. Further, an insulator containing Al atoms is used as the side wall spacer 217 (for example, Al ₂ O _Three ) Pt dry etching may be performed with F-based gas. Even if a Cl-based or Br-based gas is used for PZT etching or Pt etching, if there are sufficient considerations of the etching conditions and the like, processing with no problem in practice is possible. In addition to Pt, Ru, Ir, Pd, Rh, Os, Hf, or an oxide thereof, which is conductive, may be used as the capacitor lower electrode. Alternatively, a ferroelectric insulator other than PZT (an insulating film containing Bi, an insulating film containing La or Y, an insulating film containing Ba or Sr, or an insulating film containing Cu) may be used. As the capacitor upper electrode, in addition to the capacitor lower electrode material, W or Al that can be used as a hard mask may be used, TiN or Ta may be used, or Cu, Ag, Au, or the like may be used. Alternatively, a laminated film thereof may be used.
In this embodiment, the capacitor insulating protective film 215 is formed after the capacitor portion is formed. In this embodiment, this film is flattened by a combination of a reflow film and CMP. Although complete flattening is not essential, it is desirable to flatten as much as possible in order to increase the reliability of subsequent wiring. The planarization method and material may be the same as the formation of the bit line step planarization insulating film and the word line step planarization insulating film. Furthermore, an oxide film such as Ti, Zr, or Pb that is compatible with the material of the capacitor portion may be formed as a protective insulating film of the capacitor portion using the CVD method, and then a reflow insulating film may be formed to form a laminated film. . Ferroelectric insulation films are susceptible to degradation in reducing atmospheres or atmospheres where H atoms are generated. ₂ A film or an organic insulator such as PIQ (polyimide isoindoloquinazolinedione) may be used.
In this embodiment, the plate electrode 216 is formed after the capacitor insulating protective film 215 is formed. As this material, a material used in a conventional Si LSI process such as n + poly Si or W may be used. If the base is sufficiently flattened, a conductive material deposited by sputtering may be used as this electrode material. In the case of a stepped structure as shown in FIG. 20, a CVD method or the like is used. Then, a conductive material may be deposited. The structure shown in FIG. 22 can be formed by processing the deposited conductive material by dry etching.
FIG. 22 shows a cross-sectional view of the memory cell portion up to plate electrode formation. It goes without saying that an actual memory needs to be further packaged by forming two or more wiring layers to connect the memory cell portion and the peripheral circuit.
(Example 7)
FIG. 23 shows another embodiment of the planar layout of the memory cell in the present invention. This layout is a layout using a two-intersection cell and a COB (Capacitor Over Bitline) structure in which a capacitor is formed on a bit line. A transistor (not shown in the figure) of each memory cell is connected to a peripheral circuit (not shown) via a bit line 208. A connection portion between the transistor and the bit line 208 is a portion of the bit line plug 207 formed in a part of the active region 218. The operation of the transistor is controlled by a word line (gate electrode) 203. The word line (gate electrode) 203 is connected to a peripheral circuit (not shown). The transistor is connected to the capacitor unit 220 via a capacitor plug 211. The capacitor unit 220 is connected to a peripheral circuit (not shown) through the plate electrode 216.
The first feature of this planar layout is that one plate electrode 216 is wired for one bit line 208. With such a layout, the capacity of the plate electrode 216 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 216 can be easily controlled by a peripheral circuit. This facilitates nonvolatile memory operation using ferroelectricity. In this embodiment, an example in which one plate electrode is provided for one bit line has been described. However, the number of plate electrodes may be one plate electrode for two or more bit lines. However, when the number of plate electrodes decreases, the capacity of the plate electrodes increases, and control by peripheral circuits becomes difficult. The optimum number of plate electrodes varies depending on the memory application.
The second feature of this planar layout is that the plate electrode 216 is wired in the same direction as the bit line 208. For this reason, when the potential of the plate electrode 216 is controlled by a peripheral circuit, the potential can be controlled in synchronization with the potential of the bit line 208.
(Example 8)
FIG. 24 shows another embodiment of the planar layout of the memory cell in the present invention. This layout is a layout using a two-intersection cell and a COB (Capacitor Over Bitline) structure in which a capacitor is formed on a bit line. A transistor (not shown in the figure) of each memory cell is connected to a peripheral circuit (not shown) via a bit line 208. A connection portion between the transistor and the bit line 208 is a portion of the bit line plug 207 formed in a part of the active region 218. The operation of the transistor is controlled by a word line (gate electrode) 203. The word line (gate electrode) 203 is connected to a peripheral circuit (not shown). The transistor is connected to the capacitor unit 220 via a capacitor plug 211. The capacitor unit 220 is connected to a peripheral circuit (not shown) through the plate electrode 216.
The first feature of this planar layout is that the capacitor is controlled by one plate electrode 216 considering DRAM operation as the main feature.
With such a layout, a reference potential necessary for DRAM operation can be applied to the capacitor. Further, if the driving capability of the peripheral circuit is sufficiently increased, a non-volatile operation is possible. The number of capacitors controlled by one plate electrode 216 may be adjusted according to the use of the memory.
FIG. 25 shows a cross sectional structure (cross section AA ′) in FIG. This cross-sectional structure is basically the same as that of FIG. 202 described in the eighth embodiment except for the plate electrode 216. The plate electrode 216 may be processed to a required size as in the eighth embodiment.
According to the present invention, in a semiconductor memory using a high dielectric / ferroelectric capacitor using an electrode material whose etching reaction product has low volatility, an electrode which has been a problem when a capacitor is processed by only one lithography process Short circuit between can be prevented. As a result, there is no need for mask alignment and a highly integrated semiconductor memory using a fine capacitor can be processed.
Industrial applicability
As described above, the present invention is useful as a highly reliable and highly integrated capacitor, and is suitable for use in a large capacity DRAM of 1 gigabit or more.

Claims (7)

A multilayer capacitor composed of a lower electrode, an insulating film, and an upper electrode on the main surface of the semiconductor substrate, and a function of storing electric signals in the capacitor or storing an electric signal by reversing the polarization of the insulating film A side wall spacer on the side of the upper electrode and the insulating film of the capacitor, the side wall spacer is formed in a self-aligned manner on the side of the upper electrode and the insulating film, The semiconductor memory device, wherein the lower electrode is patterned in a self-aligned manner with the sidewall spacer . 2. The semiconductor memory device according to claim 1, wherein the sidewall spacer covers all of the vertical side surfaces of the upper electrode and at least a part of the vertical side surfaces of the insulating film. _2. The semiconductor memory device according to claim 1, wherein the upper electrode is made of at least one material selected from Pt, Os, Pd, Au, Ru, Ir, RuO ₂ and IrO ₂ . The sidewall spacer is a CVD insulating film made of at least one material selected from SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , and Ta ₂ O ₅ . A semiconductor memory device according to item. A method of manufacturing a multilayer capacitor including a barrier layer, a lower electrode, an insulating film, and an upper electrode, wherein at least a part of the upper electrode and the insulating film is patterned before forming the lower electrode MLCC, wherein the pattern sidewall spacers formed on the formed side of the upper electrode and the insulating film, patterning the self-aligned manner lower electrode and the barrier layer with respect to the side wall spacers over Manufacturing method. In a method of manufacturing a semiconductor memory device having a multilayer capacitor composed of a lower electrode, a dielectric film, and an upper electrode on a main surface of a semiconductor substrate,
Depositing a first metal layer on the main surface of the semiconductor substrate;
Depositing a first insulating film layer on the principal surface of the first metal layer;
Depositing a second metal layer on the main surface of the first insulating film layer;
A mask having a predetermined pattern shape is provided on the main surface of the second metal layer, and the second metal layer and the first metal layer are etched by etching the second metal layer and the first insulating film layer using the mask. Patterning the insulating layer of 1;
Depositing a second insulating film layer on the second metal layer and the first insulating layer;
Etching back the second insulating film layer and providing a side wall spacer on the side of the second metal layer and the first insulating layer;
Patterning the first metal layer using the second metal layer and the sidewall spacer as a mask;
A method for manufacturing a semiconductor memory device, comprising: After patterning the first metal layer, after depositing a third insulating layer, the third insulating film is etched back and planarized to expose the second metal layer, 7. The method of manufacturing a semiconductor memory device according to claim 6, further comprising a step of patterning the third metal layer after depositing the metal layer.

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