KR20000014361A - FERROELECTRIC TRANSISTOR USING Ba-Sr-Nb-O AND METHOD THEREOF - Google Patents
FERROELECTRIC TRANSISTOR USING Ba-Sr-Nb-O AND METHOD THEREOF Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000001035 drying Methods 0.000 claims abstract description 11
- 230000010287 polarization Effects 0.000 claims abstract description 7
- 238000004528 spin coating Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 claims description 54
- 239000010408 film Substances 0.000 claims description 44
- 238000004519 manufacturing process Methods 0.000 claims description 16
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical compound COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000008096 xylene Substances 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 238000003852 thin film production method Methods 0.000 claims 2
- -1 Si 3 N 4 Inorganic materials 0.000 claims 1
- 238000013329 compounding Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 239000012212 insulator Substances 0.000 abstract 2
- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Chemical compound O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 abstract 2
- 229910019651 Nb(OC2H5)5 Inorganic materials 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- AEZNLERWSLVVOK-UHFFFAOYSA-N strontium barium(2+) niobium(5+) oxygen(2-) Chemical compound [O-2].[Nb+5].[Sr+2].[Ba+2] AEZNLERWSLVVOK-UHFFFAOYSA-N 0.000 description 9
- 238000002955 isolation Methods 0.000 description 8
- 239000010955 niobium Substances 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 238000003877 atomic layer epitaxy Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Memories (AREA)
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Abstract
Description
본 발명은 불휘발성 메모리소자의 강유전체 트랜지스터에 게이트 유전막으로서 적용되는 강유전체 및 그 제조방법에 관한 것이다.The present invention relates to a ferroelectric applied to a ferroelectric transistor of a nonvolatile memory device as a gate dielectric film and a method of manufacturing the same.
잘 알려진 바와 같이, 불휘발성 메모리소자에 대한 연구중에서 강유전체 박막을 게이트 유전막에 적용한 강유전체 트랜지스터가 메모리 셀로서 사용되고 있다. 이 강유전체 트랜지스터를 사용하는 메모리 셀은 강유전체 박막의 자발 분극 방향에 의하여 소오스/드레인 간의 저항이 변화한다는 것을 응용하여 "0" 또는 "1"의 데이터를 읽을 수 있도록 구성되어 있다.As is well known, a ferroelectric transistor in which a ferroelectric thin film is applied to a gate dielectric film is used as a memory cell in research on nonvolatile memory devices. The memory cell using the ferroelectric transistor is configured to read data of "0" or "1" by applying that the resistance between the source and the drain varies depending on the spontaneous polarization direction of the ferroelectric thin film.
이 구조는 일반적인 불휘발성 강유전체 메모리소자에 비하여 비파괴읽기(NDRO : non-destructive read-out)가 가능하고 한 메모리 셀당 소요 면적이 작은 장점이 있다.This structure has the advantage of being capable of non-destructive read-out (NDRO) and a smaller area per memory cell than the conventional nonvolatile ferroelectric memory device.
도1에는 강유전체 박막을 게이트 유전막에 적용한 통상적인 강유전체 트랜지스터의 구조가 도시되어 있다. 도1을 참조하면, 강유전체 트랜지스터는 실리콘기판(11)상에 절연막(12), 강유전체박막(13) 및 게이트전극(14)이 적층되고 패터닝되어 있으며, 상기 적층된 박막의 패턴들의 노출된 표면은 보호층(Protecting layer),(15)으로 덮혀 있다. 그리고, 게이트전극 양측방의 실리콘기판 내에는 소오스영역(16) 및 드레인영역(17)이 형성된다. 이렇듯, 실리콘기판(11) 상에 절연막(12), 강유전체박막(13), 및 메탈의 게이트전극(14)이 차례로 적층된 구조를 갖는 강유전체 트랜지스터를 소위 MFIS(metal-ferroelectrics-insulator-silicon; 이하 MFIS라 함) 구조라 일컷는다.1 shows a structure of a conventional ferroelectric transistor in which a ferroelectric thin film is applied to a gate dielectric film. Referring to FIG. 1, in a ferroelectric transistor, an insulating film 12, a ferroelectric thin film 13, and a gate electrode 14 are stacked and patterned on a silicon substrate 11, and an exposed surface of patterns of the stacked thin films may be formed. It is covered with a protective layer 15. A source region 16 and a drain region 17 are formed in the silicon substrate on both sides of the gate electrode. As described above, a ferroelectric transistor having a structure in which the insulating film 12, the ferroelectric thin film 13, and the metal gate electrode 14 are sequentially stacked on the silicon substrate 11 is called a metal-ferroelectrics-insulator-silicon (MFIS); It is called MFIS) structure.
한편, 현재까지 강유전체 박막으로 알려진 대부분은 PbTiO3, PZT, SBT, KNbO3등의 페롭스카이트 형태의 산화물인데, 이들은 절연막(12) 없이 실리콘기판(11)에 바로 형성되면, 실리콘과의 계면에 자연산화물을 형성하여 우수한 특성의 강유전성을 갖기 어렵다. 이러한 현상은 트랜지스터의 소오스/드레인을 형성하기 위하여 불순물의 활성화를 실시하는데 있어서 필히 고온(> 850℃)의 열처리가 필요하며, 이에 의해 고온에서 강유전체박막의 원소들이 휘발하기 때문이다. 따라서 강유전체와 실리콘기판 사이에 절연막을 끼워 상호간에 반응과 확산을 막는 구조들이 나왔고 현재에는 도1에 도시된 MFIS 구조가 응용가능성이 높다고 알려져 있다.On the other hand, most of the ferroelectric thin films known to date are perovskite oxides such as PbTiO 3 , PZT, SBT, and KNbO 3 , which are formed directly on the silicon substrate 11 without the insulating layer 12. It is difficult to form a natural oxide and have ferroelectric properties of excellent properties. This phenomenon is necessary because a high temperature (> 850 ° C.) heat treatment is required for the activation of impurities in order to form the source / drain of the transistor, whereby elements of the ferroelectric thin film are volatilized at a high temperature. Therefore, structures that sandwich an insulating film between the ferroelectric and the silicon substrate to prevent the reaction and diffusion between them have emerged. Currently, the MFIS structure shown in FIG. 1 is known to have high applicability.
그러나, 실리콘기판과 강유전체박막 사이에 절연막을 형성하여도 유전율 및 잔류분극 등 강유전체박막의 전기적특성이 저하되는 것은 막을 수 없으며, 따라서 이러한 고온 공정 이후에도 우수한 전기적특성을 갖는 강유전체박막을 제조하기 위하여 많은 연구와 실험이 진행되고 있는 실정이다.However, even if an insulating film is formed between the silicon substrate and the ferroelectric thin film, the electrical properties of the ferroelectric thin film, such as dielectric constant and residual polarization, cannot be prevented. Therefore, many studies have been made to produce ferroelectric thin films having excellent electrical properties even after such high temperature processes. And the experiment is in progress.
본 발명은 상기 제반적인 요구 사항들을 해결하기 위하여 안출된 것으로써, 고온 공정 이후에도 우수한 전기적 특성을 갖는 강유전체로서 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above general requirements, and provides a barium-strontium-niobium-oxide (Ba-Sr-Nb-O) as a ferroelectric having excellent electrical properties even after a high temperature process. have.
본 발명의 다른 목적은 상기 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 금속유기물증착법에 의해 박막화하는 방법을 제공하는데 있다.Another object of the present invention is to provide a method for thinning the barium-strontium-niobium-oxide (Ba-Sr-Nb-O) by metal organic vapor deposition.
본 발명의 또 다른 목적은 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 게이트 유전막으로 적용한 강유전체 트랜지스터를 제공하는데 있다.Another object of the present invention is to provide a ferroelectric transistor in which barium-strontium-niobium-oxide (Ba-Sr-Nb-O) is applied as a gate dielectric film.
도1은 MFIS 구조를 갖는 통상의 강유전체 트랜지스터를 나타내는 단면도.1 is a cross-sectional view showing a conventional ferroelectric transistor having a MFIS structure.
도2는 본 발명의 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 강유전체로서 적용한 MFIS 구조의 강유전체 트랜지스터를 나타내는 단면도.Fig. 2 is a sectional view showing a ferroelectric transistor of MFIS structure in which barium-strontium-niobium-oxide (Ba-Sr-Nb-O) of the present invention is applied as a ferroelectric.
도3은 본 발명의 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 박막으로 제조하는 과정을 나타내는 공정 흐름도.Figure 3 is a process flow diagram illustrating a process for producing a barium-strontium-niobium-oxide (Ba-Sr-Nb-O) of the present invention as a thin film.
도4a 내지 도4d는 상기 도2의 구조를 갖는 강유전체 트랜지스터를 제조하는 본 발명의 일실시예를 나타내는 공정 단면도.4A to 4D are cross-sectional views showing an embodiment of the present invention for manufacturing a ferroelectric transistor having the structure of FIG.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 실리콘기판21: silicon substrate
23 : 소자분리막23: device isolation film
24, 25 : 소오스확산층, 드레인확산층24, 25: source diffusion layer, drain diffusion layer
26 : 절연막26: insulating film
27 : 바륨-스트론튬-나이오븀-산화물 (Ba-Sr-Nb-O) 박막27: barium-strontium-niobium-oxide (Ba-Sr-Nb-O) thin film
28 : 게이트전극용 금속막28: metal film for the gate electrode
29 : 보호막29: protective film
상기 목적을 달성하기 위한 본 발명의 강유전체는 하기의 화학식 1과 같이 표현되어, 850℃ 이상의 고온 공정 후에 60∼180의 유전상수(ε)와 20∼30μC/㎠의 잔류분극(Pr)을 갖는 것을 특징으로 한다.The ferroelectric of the present invention for achieving the above object is represented by the following formula 1, having a dielectric constant (ε) of 60 to 180 and a residual polarization (Pr) of 20 to 30μC / ㎠ after a high temperature process of 850 ℃ or more It features.
또한 본 발명은 강유전체 박막으로서 Ba-Sr-Nb-O 계열 박막을 제조하는 방법에 있어서, Ba, Sr, 및 Nb의 소스물질로서 각각 Ba(C8H15O2)2, Sr(C8H15O2)2, 및 Nb(OC2H5)5를 사용하여 출발용액을 제조하는 단계; 상기 출발용액을 기판 상에 스핀 코팅하는 단계; 및 상기 코팅된 출발용액을 건조 및 어닐링하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In addition, the present invention is a method of manufacturing a Ba-Sr-Nb-O-based thin film as a ferroelectric thin film, Ba (C 8 H 15 O 2 ) 2 , Sr (C 8 H as a source material of Ba, Sr, and Nb, respectively Preparing a starting solution using 15 O 2 ) 2 , and Nb (OC 2 H 5 ) 5 ; Spin coating the starting solution onto a substrate; And drying and annealing the coated starting solution.
상기 본 발명의 강유전체 박막 제조방법에서, 바람직하게 상기 출발용액을 제조하는 단계는, Ba, Sr의 각 소스로서 Ba(C8H15O2)2, Sr(C8H15O2)2를 크실렌(Xylene) 용매에 녹이는 제1단계; Nb 소스로서 Nb(OC2H5)5를 2-methoxyethanol에 녹이는 제2단계; 및 상기 제1 및 제2단계에서 제조된 용액을 배합하는 제3단계를 포함하여 이루어진다.In the ferroelectric thin film manufacturing method of the present invention, preferably, the step of preparing the starting solution, Ba (C 8 H 15 O 2 ) 2 , Sr (C 8 H 15 O 2 ) 2 as each source of Ba, Sr First step of dissolving in xylene solvent; Dissolving Nb (OC 2 H 5 ) 5 in 2-methoxyethanol as an Nb source; And a third step of combining the solutions prepared in the first and second steps.
또한, 본 발명은 게이트 유전막으로서 강유전체 박막을 갖는 강유전체 트랜지스터에 있어서, 상기 강유전체 박막은 Ba-Sr-Nb-O 계열의 산화물인 것을 특징으로 하며, 상기 Ba-Sr-Nb-O 계열의 산화물은 상기 화학식으로 표현되는 것을 특징으로 한다.In addition, the present invention is a ferroelectric transistor having a ferroelectric thin film as a gate dielectric film, characterized in that the ferroelectric thin film is a Ba-Sr-Nb-O-based oxide, the Ba-Sr-Nb-O-based oxide is It is characterized by represented by the chemical formula.
상기 본 발명의 강유전체 트랜지스터에서, 상기 Ba-Sr-Nb-O 계열의 강유전체 박막은 절연막을 개재하여 반도체기판 상에 형성되어, MFIS(metal-ferroelectrics-insulator-silicon) 구조를 갖는 것을 특징으로 한다.In the ferroelectric transistor of the present invention, the Ba-Sr-Nb-O-based ferroelectric thin film is formed on a semiconductor substrate through an insulating film, and has a metal-ferroelectrics-insulator-silicon (MFIS) structure.
또한, 상기 본 발명의 강유전체 트랜지스터에서, 상기 Ba-Sr-Nb-O 계열의 강유전체 박막은 절연막과 금속성박막을 개재하여 반도체기판 상에 형성되어, MFMIS(metal-ferroelectrics-metal-insulator-silicon) 구조를 갖는 것을 특징으로 한다.In the ferroelectric transistor of the present invention, the Ba-Sr-Nb-O-based ferroelectric thin film is formed on a semiconductor substrate through an insulating film and a metallic thin film, and has a metal-ferroelectrics-metal-insulator-silicon (MFMIS) structure. Characterized in having a.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2는 본 발명의 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 강유전체로서 적용한 MFIS 구조의 강유전체 트랜지스터를 나타내고 있다.Fig. 2 shows a ferroelectric transistor of MFIS structure in which barium-strontium-niobium-oxide (Ba-Sr-Nb-O) of the present invention is applied as a ferroelectric.
도2를 참조하면, 실리콘기판(21)의 채널 영역 상에는 절연막(26), Ba-Sr-Nb-O 강유전체 박막(27) 및 금속게이트전극(28)이 적층되고 패터닝되어 있으며, 상기 적층된 박막들의 패턴 표면은 보호층(29)으로 덮혀 있다. 그리고, 게이트전극 양측방의 실리콘기판(21) 내에는 소오스확산층(24) 및 드레인확산층(25)이 형성된다. 한편, 실리콘기판(21)은 이웃하는 트랜지스터간의 격리(isolation)를 위해 소자분리막(23)으로서 실리콘산화막이 형성되어 소자분리영역과 활성영역이 정의된다.Referring to FIG. 2, an insulating film 26, a Ba—Sr—Nb—O ferroelectric thin film 27 and a metal gate electrode 28 are stacked and patterned on the channel region of the silicon substrate 21. The patterned surface of these is covered with a protective layer 29. The source diffusion layer 24 and the drain diffusion layer 25 are formed in the silicon substrate 21 on both sides of the gate electrode. On the other hand, in the silicon substrate 21, a silicon oxide film is formed as the device isolation film 23 for isolation between neighboring transistors to define the device isolation region and the active region.
도2의 구조에서, 본 발명은 게이트 유전막으로서 Ba-Sr-Nb-O 강유전체 박막(27)을 적용하였다는데 그 특징이 있는 것으로, 이 Ba-Sr-Nb-O 강유전체 박막(27)은 소오스확산층(24) 및 드레인확산층(25) 형성을 위한 고온 공정 후에도 그 전기적 특성이 우수하다는 것이 실험적으로 밝혀졌다. 일예로, (Bax, Sr1-x)Nb2O6박막을 제조하고 x를 0.7∼0.85 변화시키면서 측정한 결과, 고온공정 후에도 (Bax, Sr1-x)Nb2O6박막은 60∼180의 유전상수(ε)와 20∼30μC/㎠의 잔류분극(Pr)을 갖는 것으로 측정되었다.In the structure of Fig. 2, the present invention is characterized in that the Ba-Sr-Nb-O ferroelectric thin film 27 is applied as a gate dielectric film, and the Ba-Sr-Nb-O ferroelectric thin film 27 is a source diffusion layer. It has been found experimentally that the electrical characteristics are excellent even after the high temperature process for forming the (24) and the drain diffusion layer 25. For example, a (Ba x , Sr 1-x ) Nb 2 O 6 thin film was prepared and measured with x varying from 0.7 to 0.85. As a result, the (Ba x , Sr 1-x ) Nb 2 O 6 thin film was 60 It was measured to have a dielectric constant (?) Of ˜180 and a residual polarization (Pr) of 20 to 30 µC / cm 2.
한편, 본 실시예에서 절연막(26)은 실리콘기판과의 접합성이 좋고 고온에서도 역시 그 특성이 유지되는 실리콘산화막(SiO2)이나 실리콘질화막(Si3N4)을 적용할 수 있고, 이와 유사한 기타 다른 절연막으로서 Al2O3, CeO2, Ta2O5, ZrO2등을 적용할 수 있을 것이다. 또한 이러한 절연막들을 적층하여 다층으로 실시 구성할 수 있다. 금속게이트전극(28)은 통상적으로 이용되고 있는 백금(Pt)을 이용하였다.In the present embodiment, the insulating film 26 may be a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 ) having good adhesion to a silicon substrate and maintaining its properties even at high temperature. As another insulating film, Al 2 O 3 , CeO 2 , Ta 2 O 5 , ZrO 2, etc. may be used. In addition, the insulating films may be stacked and implemented in a multilayer. As the metal gate electrode 28, platinum (Pt), which is commonly used, was used.
도3은 본 발명의 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)을 박막으로 제조하는 과정, 즉 도2에서 상기 Ba-Sr-Nb-O 강유전체 박막(27)을 제조하는 일실시예를 나타내는 공정 흐름도이다.FIG. 3 illustrates a process of manufacturing the barium-strontium-niobium oxide (Ba-Sr-Nb-O) of the present invention as a thin film, that is, the Ba-Sr-Nb-O ferroelectric thin film 27 of FIG. 2. A process flow diagram illustrating one embodiment.
도3을 참조하면, 우선 Ba, Sr의 각 소스로서 Ba(C8H15O2)2, Sr(C8H15O2)2를 크실렌(Xylene) 용매에 녹이고(301), Nb 소스로서 Nb(OC2H5)5를 2-메틸에탄올기(2-methoxyethanol)에 녹여(302) 출발용액을 만들다(303).Referring to FIG. 3, first, Ba (C 8 H 15 O 2 ) 2 and Sr (C 8 H 15 O 2 ) 2 are dissolved in xylene (301) as a source of Ba and Sr (301), and as a Nb source. Nb (OC 2 H 5 ) 5 was dissolved in 2-methoxyethanol (302) to form a starting solution (303).
이어서, 기판에 상기 출발용액을 스핀코팅(Spin-coating)으로 증착하고(304) 건조를 두번에 걸쳐 수행한다. 첫번째 건조(305)는 약 200∼300℃의 비교적 저온에서 수행하고, 두 번째 건조는 약 350∼450℃에서 수행한다. 스핀코팅시 기판을 3000rpm으로 회전시킨다.The starting solution is then deposited onto the substrate by spin-coating (304) and drying is carried out twice. The first drying 305 is carried out at a relatively low temperature of about 200-300 ° C., and the second drying is carried out at about 350-450 ° C. The substrate is rotated at 3000 rpm during spin coating.
계속해서 최종 결정화를 위한 어닐링(Annealing)을 약 600∼800℃의 산소 분위기에서 2시간 정도 실시하여(307), (Bax, Sr1-x)Nb2O6(단 x=0.7∼0.85) 박막 제조를 완료한다(308).Then, annealing for final crystallization is carried out in an oxygen atmosphere of about 600 to 800 ° C. for about 2 hours (307), (Ba x , Sr 1-x ) Nb 2 O 6 (where x = 0.7 to 0.85) Complete thin film production (308).
도4a 내지 도4d는 도2의 구조를 갖는 강유전체 트랜지스터를 제조하는 공정을 나타내는 단면도로서, 이를 통해 본 발명의 일실시예에 따른 강유전체 트랜지스터 제조방법을 살펴본다. 도2와 동일한 구성요소에 대해서는 동일한 도면부호를 인용하였다.4A through 4D are cross-sectional views illustrating a process of manufacturing a ferroelectric transistor having the structure of FIG. 2, and thus, a method of manufacturing a ferroelectric transistor according to an embodiment of the present invention will be described. The same reference numerals are used for the same components as in FIG.
먼저, 도4a는 실리콘기판(21)에 통상의 트렌치 아이솔레이션 공정(trench isolation process)을 통해 소자분리막(23)을 형성한 상태를 도시하고 있다. 소자분리는 LOCOS 공정 등 현재 알려진 기타 모든 방법을 적용할 수 있을 것이다. 한편, 소자분리막 하부에 채널스탑영역을 형성하기 위한 도펀트 주입 등의 세부 공정은 여기서 그 서술을 생략한다.First, FIG. 4A shows a state in which the device isolation film 23 is formed on the silicon substrate 21 through a conventional trench isolation process. Device isolation may be applied to all other known methods, including the LOCOS process. In the meantime, detailed processes such as dopant implantation for forming the channel stop region under the device isolation layer will be omitted.
이어서, 도4b는 도4a의 기판 상에 절연막(26)과 Ba-Sr-Nb-O 강유전체 박막(27) 및 게이트전극용 금속막(28)을 차례로 적층한 상태를 나타낸다.4B shows a state in which an insulating film 26, a Ba-Sr-Nb-O ferroelectric thin film 27, and a gate electrode metal film 28 are sequentially stacked on the substrate of FIG. 4A.
구체적으로 절연막(26)은 실리콘기판(21)과의 접합이 우수하고 고온 공정에서 실리콘기판(21)과 Ba-Sr-Nb-O 강유전체 박막(27)과의 반응을 방지할 수 있는 물질을 적용하는데, 예컨대 실리콘산화막(SiO2)이나 실리콘질화막(Si3N4), 또는 알루미나(Al2O3)를 적용한다. 절연막(26)의 두께는 5∼8nm로 형성하고, 실리콘산화막을 적용할 경우는 열 산화 공정으로, 실리콘질화막을 적용할 경우는 LPCVD(Low pressure chemical vapor deposition) 방법으로, 알루미나를 적용할 경우에는 원자층 에피택시(Atomic layer epitaxy; ALE)법으로 제조한다. 이밖에 현재 알려진 CeO2, Ta2O5, ZrO2등을 적용할 수도 있다.Specifically, the insulating film 26 is a material that is excellent in bonding with the silicon substrate 21 and prevents the reaction between the silicon substrate 21 and the Ba-Sr-Nb-O ferroelectric thin film 27 in a high temperature process. For example, a silicon oxide film (SiO 2 ), a silicon nitride film (Si 3 N 4 ), or alumina (Al 2 O 3 ) is used. The thickness of the insulating film 26 is 5 to 8 nm, and the silicon oxide film is thermally oxidized, the silicon nitride film is LPCVD (low pressure chemical vapor deposition), and the alumina is applied. It is prepared by the atomic layer epitaxy (ALE) method. In addition, currently known CeO 2 , Ta 2 O 5 , ZrO 2 and the like may be applied.
Ba-Sr-Nb-O 강유전체 박막(27)을 제조하는 구체적인 방법은 앞서 도3을 참조하여 설명하였기에 여기서는 그 설명을 생략하기로 한다. 한편, 도3에서는 스핀코팅 방법인 MOD(Metal organic deposition) 방법에 의해 Ba-Sr-Nb-O 강유전체 박막(27)을 제조하는 방법을 설명하였으나, 그 밖에 스퍼터링 방법 및 화학기상증착 방법으로도 제조가 가능할 것이다.A detailed method of manufacturing the Ba-Sr-Nb-O ferroelectric thin film 27 has been described above with reference to FIG. 3, and thus description thereof will be omitted. Meanwhile, FIG. 3 illustrates a method of manufacturing the Ba-Sr-Nb-O ferroelectric thin film 27 by a metal organic deposition (MOD) method, which is a spin coating method, but is also manufactured by a sputtering method and a chemical vapor deposition method. Would be possible.
게이트전극용 금속막(28)은 스퍼터링에 의한 백금을 적용할 수 있다.The gate electrode metal film 28 may be made of platinum by sputtering.
이어서, 도4c는 적층된 박막들(26, 27, 28)을 통상의 리소그라피(lithography) 공정으로 패터닝하고, 패턴된 박막들을 감싸도록 보호막(29)을 형성한 상태이다. 적층된 박막들의 패터닝을 위한 식각은 RIE(Reactive ion etch)에 의해 실시하고, 보호막(9)은 CVD에 의한 실리콘산화막, 또는 실리콘질화막, 또는 알루미나 등을 적용할 수 있다.Subsequently, in FIG. 4C, the stacked thin films 26, 27, and 28 are patterned by a conventional lithography process, and a protective film 29 is formed to surround the patterned thin films. Etching for patterning the stacked thin films is performed by reactive ion etch (RIE), and the protective layer 9 may be a silicon oxide film, a silicon nitride film, or alumina by CVD.
도4d는 이온주입에 의해 소오스확산층(24) 및 드레인확산층(25)을 형성한 상태이다.4D shows the source diffusion layer 24 and the drain diffusion layer 25 formed by ion implantation.
이상의 설명에서는 MFIS(metal-ferroelectrics-insulator-silicon) 구조의 강유전체 트랜지스터에 대해서 설명하였으나, 절연막 위에 전도성 박막(예컨대 Pt와 같은 금속박막과 RuO2와 같은 산화물 전극박막)을 형성하고 그 위에 강유전체 박막과 게이트 전극을 적층한 구조의 MFMIS(metal-ferroelectrics-metal-insulator-silicon)형 강유전체 트랜지스터에도 본 발명의 Ba-Sr-Nb-O 강유전체 박막(27)은 응용될 수 있다.In the above description, the ferroelectric transistor having a metal-ferroelectrics-insulator-silicon (MFIS) structure has been described, but a conductive thin film (for example, a metal thin film such as Pt and an oxide electrode thin film such as RuO 2 ) is formed on the insulating film, and the ferroelectric thin film is formed thereon. The Ba-Sr-Nb-O ferroelectric thin film 27 of the present invention can be applied to a metal-ferroelectrics-metal-insulator-silicon (MFMIS) type ferroelectric transistor having a structure in which gate electrodes are stacked.
이렇듯, 본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.As such, although the technical idea of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명의 바륨-스트론튬-나이오븀-산화물(Ba-Sr-Nb-O)은 고온공정 후에도 유전상수 및 잔류분극 등 그 전기적 특성을 유지하여, 강유전체 트랜지스터의 게이트 유전막으로 적용하면 그 소자의 전기적 특성을 크게 향상시킬 수 있다. 특히 일반적인 MOSFET공정에서 사용하는 소스/드레인 확산 공정으로, 즉 고온공정으로 강유전체 트랜지스터의 제조가 가능하다.The barium-strontium-niobium-oxide (Ba-Sr-Nb-O) of the present invention retains its electrical characteristics such as dielectric constant and residual polarization even after a high temperature process, and when applied as a gate dielectric film of a ferroelectric transistor, the electrical characteristics of the device Can greatly improve. In particular, it is possible to manufacture ferroelectric transistors by a source / drain diffusion process used in a general MOSFET process, that is, a high temperature process.
Claims (13)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100363393B1 (en) * | 2000-06-28 | 2002-11-30 | 한국과학기술연구원 | Ndro-fram memory cell device and the fabrication method there of |
| KR100479517B1 (en) * | 2001-03-28 | 2005-03-30 | 샤프 가부시키가이샤 | Mfos mrmory transisor & fabricating same |
| KR100725700B1 (en) | 2005-10-17 | 2007-06-07 | 주식회사 엘지화학 | Metal composite oxides comprising strontium and ionic conductors using the same |
| KR100802248B1 (en) * | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | Non-volatile semiconductor memory device |
| US7590024B2 (en) | 2005-12-30 | 2009-09-15 | Hynix Semiconductor Inc. | Nonvolatile semiconductor memory device |
| WO2018021709A1 (en) * | 2016-07-28 | 2018-02-01 | 고려대학교 산학협력단 | Semiconductor device comprising hafnia-based ferroelectric and method for manufacturing same |
-
1998
- 1998-08-20 KR KR1019980033756A patent/KR20000014361A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100363393B1 (en) * | 2000-06-28 | 2002-11-30 | 한국과학기술연구원 | Ndro-fram memory cell device and the fabrication method there of |
| KR100479517B1 (en) * | 2001-03-28 | 2005-03-30 | 샤프 가부시키가이샤 | Mfos mrmory transisor & fabricating same |
| KR100725700B1 (en) | 2005-10-17 | 2007-06-07 | 주식회사 엘지화학 | Metal composite oxides comprising strontium and ionic conductors using the same |
| KR100802248B1 (en) * | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | Non-volatile semiconductor memory device |
| US7590024B2 (en) | 2005-12-30 | 2009-09-15 | Hynix Semiconductor Inc. | Nonvolatile semiconductor memory device |
| WO2018021709A1 (en) * | 2016-07-28 | 2018-02-01 | 고려대학교 산학협력단 | Semiconductor device comprising hafnia-based ferroelectric and method for manufacturing same |
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