JPH11312806A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a gate electrode, while preventing the junction leak caused by the damage of a semiconductor substrate and the short circuit between gate electrodes due to the residue of a gate electrode layer. SOLUTION: A photoresist 16, having the pattern of a gate electrode, is formed on a polycrystalline Si film 15, and after phosphorus 17 has been introduced by subjecting it to a plural times of ion implantations having different accelerated energies, etching treatment. As a result, the etching speed of the polycrystalline Si film l5 can be increased through the introduction of phosphorus 17 to a part adjacent to an SiO2 film 14 which is a gate oxide film. Accordingly, over-etching treatment can be conducted adequately, while the disappearance of the SiO2 film 14 is being prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device in which a gate electrode is formed on a semiconductor substrate via a gate insulating film.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional example of the present invention for manufacturing a MOS transistor. In this conventional example, as shown in FIG. 4, a trench 12 is formed in a portion of an Si substrate 11 which is to be an element isolation region.
Is filled with a SiO ₂ film 13. Then, an SiO ₂ film 14 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 13.

Thereafter, a polycrystalline Si film 15 is deposited on the SiO ₂ films 13 and 14, and a photoresist 16 is processed on the polycrystalline Si film 15 into a gate electrode pattern. Then, using the photoresist 16 as a mask, the polycrystalline Si film 1 is used.
5 is etched to form a gate electrode made of the polycrystalline Si film 15.

Meanwhile, miniaturization of MIS transistors in a semiconductor device is proceeding according to a scaling rule. For example, the thickness of the SiO ₂ film used as the gate oxide film of the MOS transistor constituting the logic LSI is about 5 nm when the gate length is 0.25 μm, but is about 5 nm when the gate length is 0.18 μm. In this case, the thickness needs to be about 3.5 nm, and when the gate length is 0.13 μm, it is necessary to reduce the thickness to about 2.5 nm.

However, even if the gate oxide film becomes thin, the gate electrode is not made thin in order to secure a low resistance value of the gate electrode. In particular, high-speed logic LS such as a microprocessor
I has this tendency.

[0006]

Meanwhile [0007], as shown in FIG. 4 (a), for such variations in thickness of the depth of the variations and the SiO ₂ film 13 of the trench 12, the surface of the SiO ₂ film 13 In general, a step occurs between the surface of the SiO ₂ film 14 and the surface of the SiO ₂ film 14. However, in the case where such a step is generated, if the polycrystalline Si film 15 is not sufficiently over-etched when etching, the polycrystalline Si
A residue of the film 15 is generated, and the residue causes a short circuit between the gate electrodes.

On the other hand, if sufficient over-etching is performed when etching the polycrystalline Si film 15, residues of the polycrystalline Si film 15 do not occur at the steps. However, as described above, even if the SiO ₂ film 14 as the gate oxide film becomes thinner, the polycrystalline Si film 15 as the gate electrode is not made thinner.
As shown in (b), the SiO ₂ film 14 disappears and the Si substrate 11 is also etched. As a result, the Si substrate 11 is damaged, causing a junction leak or the like.

That is, in the conventional example shown in FIG.
Junction leakage due to damage to substrate 11 and polycrystalline Si film 15
It is difficult to prevent both of the gate electrodes from being short-circuited due to the residue, and it is difficult to manufacture a semiconductor device having excellent characteristics and high reliability. Therefore, the invention of the present application is capable of preventing both a junction leak and the like due to damage to a semiconductor substrate and a short circuit between gate electrodes due to a residue of a gate electrode layer, and provides a semiconductor device having excellent characteristics and high reliability. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be manufactured.

[0009]

In the method of manufacturing a semiconductor device according to the present invention, the impurity is introduced into the gate electrode layer by a plurality of times of ion implantations having different acceleration energies. Even if the thickness of the layer varies, the impurity can be introduced into a portion of the gate electrode layer close to the gate insulating film. In addition, the impurity is ion-implanted in a self-aligned manner using the mask layer of the gate electrode pattern as a mask, and the ion-implanted impurity is an impurity that increases the etching rate of the gate electrode layer.

For this reason, the etching selectivity with respect to the gate insulating film can be increased even in a portion of the gate electrode layer other than the portion to be left as the gate electrode, near the gate insulating film. Accordingly, when the gate electrode layer is etched using the mask layer as a mask, overetching can be performed until the residue of the gate electrode layer is not generated while preventing the semiconductor substrate from being etched due to disappearance of the gate insulating film.

Further, since the impurity is introduced into the gate electrode layer by a plurality of ion implantations having different acceleration energies, the dose amount in each ion implantation is smaller than that in the case where the impurity is introduced only by one ion implantation. It may be less.
Therefore, even if ion implantation is performed with high acceleration energy to introduce impurities into a portion of the gate electrode layer close to the gate insulating film, the amount of impurities introduced into the gate insulating film is small.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the impurities implanted into the gate electrode layer are diffused by heat treatment, so that the impurities are introduced with high precision into a portion of the gate electrode layer close to the gate insulating film. can do.
In addition, since the heat-resistant layer is formed at least as a part of the mask layer in contact with the gate electrode layer, deformation of the mask layer can be prevented even when heat treatment is performed. No problem occurs when etching the electrode layer.

For this reason, the etching selectivity with respect to the gate insulating film can be increased with high accuracy even in a portion of the gate electrode layer other than the portion to be left as the gate electrode, even in a portion near the gate insulating film. Therefore, when etching the gate electrode layer using the heat-resistant layer as a mask, overetching is sufficiently performed until the residue of the gate electrode layer is not generated while preventing the etching of the semiconductor substrate due to disappearance of the gate insulating film with high accuracy. It can be carried out.

According to a third aspect of the present invention, the impurity is introduced into the gate electrode layer by ion implantation from a direction inclined with respect to the surface of the gate electrode layer, and the inclination angle from the surface is reduced. The acceleration energy increases as the value increases. For this reason, the width of the portion of the gate electrode layer where the impurity is not introduced can be made smaller than the width of the mask layer, and the portion where the impurity is not introduced is formed perpendicular to the surface of the gate electrode layer. Can be.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first to third embodiments of the present invention applied to the manufacture of a MOS transistor will be described with reference to FIGS.
3 will be described. FIG. 1 shows a first embodiment. In the first embodiment, as shown in FIG. 1A, a trench 12 is formed in a portion of an Si substrate 11 which is to be an element isolation region, and the trench 12 is formed by an SiO ₂ film 13.
Fill with.

Thereafter, an SiO ₂ film 1 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 13.
4 is formed by a thermal oxidation method. And the decompression C under the following conditions
SiO polycrystalline Si film 15 having a thickness of 250nm by VD method ₂
The photoresist 16 is deposited on the films 13 and 14 and the photoresist 16 is processed on the polycrystalline Si film 15 into a gate electrode pattern.

Decompression CVD conditions for polycrystalline Si film Source gas: SiH ₄ / He / N ₂ = 100/400/2
00sccm Pressure: 70Pa Temperature: 610 ° C

Next, as shown in FIG. 1B, using the photoresist 16 as a mask,
Phosphorus 17 is introduced into the polycrystalline Si film 15 by four ion implantations at eV, 30 keV, 50 keV, and 90 keV and a dose of 5 × 10 ¹⁴ / cm ² . Note that phosphorus 17 by ion implantation with an acceleration energy of 90 keV is used.
Is about 110 nm.

Next, as shown in FIG. 1C, the polycrystalline Si film 15 is subjected to two-stage dry etching under the following conditions using a photoresist 16 as a mask and a microwave etching apparatus. A gate electrode made of the polycrystalline Si film 15 is formed. At this time, the portion of the polycrystalline Si film 15 into which the phosphorus 17 has been ion-implanted has a higher etching selectivity with respect to the SiO ₂ film 14 than the portion where the ion has not been implanted. Thereafter, as shown in FIG. 1D, the photoresist 16 is removed.

Dry etching conditions in first stage of polycrystalline Si film Etching gas: Cl ₂ = 200 sccm Pressure: 0.7 Pa Microwave power: 900 W High frequency power: 100 W Current of magnetic field generating coil 1/2: 20/14 A temperature : 2
0 ° C

Dry etching condition of second stage of polycrystalline Si film Etching gas: HBr / O ₂ = 120/2 sccm Pressure: 1.3 Pa Microwave power: 900 W High frequency power: 30 W Current of magnetic field generating coil 1/2: 25 / 4A temperature: 20 ° C

FIG. 2 shows a second embodiment. Also in the second embodiment, as shown in FIG. 2A, steps similar to those of the first embodiment shown in FIG. 1 are executed until the photoresist 16 is processed into a gate electrode pattern.

However, in the second embodiment,
As shown in FIG. 2B, using the photoresist 16 as a mask, the acceleration energy and the angle from the surface of the polycrystalline Si film 15 are 20 keV and 30 °, 40 keV and 5 keV, respectively.
5 °, 80 keV and 70 °, 120 keV and 80 °
The phosphorus 17 is introduced into the polycrystalline Si film 15 by four ion implantations each having a dose of 5 × 10 ¹⁴ / cm ² .

At this time, each ion implantation is performed by either oblique ion implantation from two directions from both sides of the photoresist 16 and below the photoresist 16 or oblique rotation ion implantation. As a result, a portion of the polycrystalline Si film 15 under the photoresist 16 and into which the phosphorus 17 is not introduced is formed perpendicular to the surface of the polycrystalline Si film 15, but the width of this portion is Is smaller by 30 nm on both sides than the width of.

Next, using the photoresist 16 as a mask, the same dry etching as in the case of FIG. 1C in the first embodiment is performed again, and as shown in FIG.
A gate electrode made of the polycrystalline Si film 15 is formed. At this time, as described above, the phosphorus 17 in the polycrystalline Si film 15 is used.
Since the width of the portion where no is introduced is narrower by 30 nm on both sides than the width of the photoresist 16, the side etching progresses, and
A gate electrode narrow by nm is formed. Then, FIG.
As shown in (d), the photoresist 16 is removed.

FIG. 3 shows a third embodiment. Also in the third embodiment, as shown in FIG.
Until the film 15 is deposited, the same steps as in the first embodiment shown in FIG. 1 are performed. However, in the third embodiment, after that, the Si ₃ N ₄ film 18 is deposited on the polycrystalline Si film 15 by the low pressure CVD method under the following conditions, and the Si ₃ N ₄ film 1 is formed.
The photoresist 16 is processed on the gate electrode 8 into a gate electrode pattern. Then, using the photoresist 16 as a mask, dry etching is performed on the Si ₃ N ₄ film 18 under the following conditions using a magnetron etching apparatus.

Low pressure CVD conditions for Si ₃ N ₄ film Source gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 50/20
0 / 200sccm Pressure: 70Pa Temperature: 760 ° C

Dry etching conditions for Si ₃ N ₄ film Etching gas: CHF ₃ / O ₂ = 75/25 sccm Pressure: 5.3 Pa High frequency power: 600 W

Next, as shown in FIG. 3B, ion implantation similar to that of FIG. 1B in the first embodiment is performed again. Then, as shown in FIG. 3C, after removing the photoresist 16, a heat treatment is performed at 800 ° C. for 10 minutes in a nitrogen atmosphere to diffuse the phosphorus 17 implanted into the polycrystalline Si film 15. Let it.

As described above, the acceleration energy is 90 keV
The projection range of the phosphorus 17 due to the ion implantation is about 110 nm, but this heat treatment allows the phosphorus 17 to be introduced with high precision to the portion of the polycrystalline Si film 15 close to the SiO ₂ film 14. In addition, even if the heat treatment is performed, the Si ₃ N ₄ film 18 does not deform.

Next, as shown in FIG. 3D, Si ₃ N ₄
Using the film 18 as a mask, FIG.
By performing the same dry etching as in the case of (c), a gate electrode made of the polycrystalline Si film 15 is formed. afterwards,
As shown in FIG. 3E, only the Si ₃ N ₄ film 18 is selectively removed with hot phosphoric acid.

In the first to third embodiments, S
The SiO ₂ film 14 is used as a gate insulating film, the polycrystalline Si film 15 is used as a gate electrode layer, and phosphorus 17 is used as the polycrystalline Si film 15.
In the present invention, a gate insulating film other than the SiO ₂ film and a gate electrode layer other than the polycrystalline Si film can be formed, and impurities other than phosphorus are ion-implanted into the gate electrode layer. You can also.

[0033]

According to the first aspect of the present invention, in the method of manufacturing a semiconductor device, when the gate electrode layer is etched using the mask layer as a mask, the gate electrode layer is prevented from being etched due to the disappearance of the gate insulating film. Since over-etching can be performed until no residue remains, it is possible to prevent both a junction leak due to damage to the semiconductor substrate and a short circuit between gate electrodes due to a residue in the gate electrode layer.

Further, even if ion implantation is performed with high acceleration energy to introduce impurities into a portion of the gate electrode layer close to the gate insulating film, the amount of impurities introduced into the gate insulating film is small. Variations in voltage and the like can be prevented. Therefore, a semiconductor device having excellent characteristics and high reliability can be manufactured.

In the method of manufacturing a semiconductor device according to the present invention, when the gate electrode layer is etched using the heat-resistant layer as a mask, the etching of the semiconductor substrate due to the disappearance of the gate insulating film is prevented with high accuracy. Since over-etching can be sufficiently performed until no residue of the layer is generated, it is possible to accurately prevent both a junction leak due to damage to the semiconductor substrate and a short circuit between the gate electrodes due to the residue of the gate electrode layer. it can. Therefore, a semiconductor device having better characteristics and higher reliability can be manufactured.

In the method of manufacturing a semiconductor device according to the third aspect, the width of a portion of the gate electrode layer where impurities are not introduced can be made smaller than the width of the mask layer.
Since a portion into which impurities are not introduced can be formed perpendicular to the surface of the gate electrode layer, side etching proceeds, and a gate electrode narrower than the width of the mask layer can be formed. Accordingly, it is possible to manufacture a semiconductor device having excellent characteristics, high reliability, and high fineness and integration.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 3 is a side sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 4 is a side sectional view of a conventional example of the present invention;
(A) shows the case where the over-etching is small, and (b) shows the case where the over-etching is large.

[Explanation of symbols]

11: Si substrate (semiconductor substrate), 14: SiO ₂ film (gate insulating film), 15: polycrystalline Si film (gate electrode layer),
16 ... photoresist (mask layer), 17 ... phosphorus (impurity), 18 ... Si ₃ N ₄ film (heat resistant layer)

Claims (3)

[Claims] A step of forming a gate electrode layer on a semiconductor substrate via a gate insulating film; a step of forming a mask layer of a gate electrode pattern on the gate electrode layer; and using the mask layer as a mask. Introducing an impurity for increasing the etching rate of the gate electrode layer into the gate electrode layer by ion implantation with a plurality of different acceleration energies, and after the ion implantation, using the mask layer as a mask to form the gate electrode. And a step of etching a layer. 2. a step of forming a heat-resistant layer at least as a part of the mask layer in contact with the gate electrode layer; a step of diffusing the impurity by heat treatment after the ion implantation; and a step of forming the heat-resistant layer after the heat treatment. Etching the gate electrode layer using a mask as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: 3. The ion implantation of a relatively small inclination angle and a relatively small acceleration energy from the surface of the gate electrode layer, and a relatively large inclination angle and a relatively large acceleration energy from the surface of the gate electrode layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed a plurality of times.