JP2005222977A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing technique of a semiconductor device having an essential gate leak current reduction effect by suppressing a decrease in a drain current. <P>SOLUTION: Nitrogen active species (N<SP>*</SP>) are introduced into a silicon oxide film 8 in a state where reactivity near the surface of the silicon oxide film 8 is being improved by cutting the interatomic combination between silicon near the surface of the silicon oxide film 8 and oxygen by an argon ion (Ar<SP>+</SP>), for suppressing the introduction of nitrogen into the interface between the silicon oxide film 8 and a silicon substrate 1. The silicon oxide film 8 is used as a gate insulating film of a MISFET. In the silicon oxide film 8, nitrogen concentration is relatively high near the surface of the silicon oxide film 8, and the concentration near the interface of the silicon oxide film 8/silicon substrate 1 is relatively low. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  In the case of a silicon device, an insulating film containing silicon oxide as a main component is used for the gate insulating film of the MISFET.

Also, the nitrogen concentration and film density near the gate insulating film surface (gate electrode interface side) are high, the nitrogen concentration near the semiconductor substrate interface is low, and the intermediate nitrogen between the film surface and the semiconductor substrate interface is between them. There is a technique of using a silicon oxynitride film in which a region having a concentration exists as a gate insulating film (see, for example, Patent Document 1).
JP 2002-110673 A

  With the miniaturization of semiconductor integrated circuits, the MISFET gate insulating film needs to be thinned. However, when a silicon oxide film having a low dielectric constant used as a gate insulating film is thinned, the gate leakage current increases due to the direct tunneling phenomenon. Is a problem.

  Therefore, in order to reduce the gate leakage current by increasing the physical thickness of the gate insulating film while ensuring the capacitance, the introduction of a high dielectric constant gate insulating film such as an Hf oxide film or an Hf silicate film is considered. Has been. However, these high dielectric constant gate insulating films still have many problems in interface control and the like, and a process technology that can achieve performance exceeding that of a conventional silicon oxide film-based material has not yet been established. Therefore, it is considered that the gate leakage current will be reduced by nitriding the silicon oxide film for the time being as in the prior art. Therefore, it is necessary to further increase the nitrogen concentration in the gate insulating film in the future.

  As a nitriding treatment technique for a gate insulating film, a NO oxynitriding method has been used in which an interface between an oxide film and a substrate is nitrided with NO gas at high temperature. In addition to the effect of reducing the gate leakage current, the NO oxynitriding method can obtain high-quality interface characteristics that greatly improve hot carrier resistance and electron mobility. However, in the NO oxynitriding method, only the interface is nitrided and the vicinity of the oxide film surface cannot be nitrided. Therefore, the nitrogen concentration of the entire film cannot be increased, and the amount of nitrogen introduced is limited. In addition, excessive nitridation at the interface increases interface states and traps in the film and decreases carrier mobility.

  Therefore, in order to increase the amount of introduced nitrogen in the film, a method for introducing nitrogen near the surface of the film is required. Therefore, in order to suppress the diffusion of nitrogen to the interface, a method capable of nitriding at a low temperature, for example, a method using nitrogen active species generated by plasma (plasma nitriding) has been developed.

  However, in an extremely thin gate insulating film having a film thickness of 2 nm or less, the carrier mobility decreases as the amount of introduced nitrogen increases. This is presumably because nitrogen introduced by plasma nitriding diffuses near the interface with the semiconductor substrate. Therefore, the plasma nitriding method for the gate insulating film can reduce the gate leakage current, but reduces the drain current, so that the substantial gate leakage current reducing effect is reduced.

  An object of the present invention is to provide a manufacturing technique of a semiconductor device that suppresses a decrease in drain current of a MISFET and has a substantial gate leakage current reduction effect.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the method of manufacturing a semiconductor device of the present invention, by exposing a gate insulating film surface containing silicon oxide as a main component in a gas containing an active species of an inert element such as argon, silicon and oxygen near the surface of the gate insulating film After the bonds between the atoms are broken to increase the reactivity in the vicinity of the surface of the gate insulating film, the gate insulating film is subjected to nitriding treatment with an active species of nitrogen.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A gate insulating film having a region with a relatively low nitrogen concentration at the interface between the gate insulating film and the semiconductor substrate and a region with a relatively high nitrogen concentration near the surface of the gate insulating film is obtained, and the drain current of the MISFET is reduced. It is possible to realize a semiconductor device having a substantial effect of reducing gate leakage current while suppressing the above.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
An example of a method of manufacturing a complementary metal oxide semiconductor (CMOS) device according to the first embodiment of the present invention will be described in the order of steps.

  First, as shown in FIG. 1, a semiconductor substrate (a semiconductor wafer processed into a circular thin plate), for example, a silicon substrate 1 made of single crystal silicon having a specific resistance of about 10 Ω · cm is prepared. Subsequently, the silicon substrate 1 is heat-treated at about 850 ° C. in an oxidizing atmosphere to form a thin pad oxide film 2 having a thickness of about 10 nm on the main surface of the silicon substrate 1. Subsequently, a silicon nitride film 3 having a thickness of about 120 nm is formed on the pad oxide film 2 by a CVD (Chemical Vapor Deposition) method. The pad oxide film 2 is formed for the purpose of protecting the surface of the silicon substrate 1 when the silicon nitride film 3 is removed. Further, since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the surface of the silicon substrate 1 below (active region of the MISFET).

  Next, the silicon nitride film 3 and the pad oxide film 2 in the element isolation region are removed by dry etching using the photoresist pattern (not shown) and the silicon nitride film 3 as a mask. The photoresist pattern is patterned by applying a photoresist film on the silicon substrate 1 and then subjecting the photoresist film to light exposure and development.

  Next, an element isolation groove 5a having a depth of about 350 nm is formed in the silicon substrate 1 in the element isolation region by dry etching using the silicon nitride film 3 as a mask, and then a damage layer caused by etching generated in the element isolation groove 5a is removed. For this purpose, the silicon substrate 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the element isolation trench 5a.

  Next, after the silicon oxide film 4 is formed on the silicon substrate 1 by the CVD method, in order to improve the film quality of the silicon oxide film 4, the silicon substrate 1 is heat-treated to densify the silicon oxide film 4. .

  Next, the silicon oxide film 4 is polished by CMP (Chemical Mechanical Polishing) using the silicon nitride film 3 as an etching stopper film and left inside the element isolation groove 5a, whereby the element isolation portion 5 whose surface is flattened is formed. Form. Subsequently, the silicon nitride film 3 remaining on the active region of the silicon substrate 1 is removed by wet etching using hot phosphoric acid.

  Next, as shown in FIG. 2, using a photoresist pattern (not shown) as a mask, an impurity having an n-type conductivity (for example, P (phosphorus)) is formed in a region of the silicon substrate 1 where a p-channel MISFET is to be formed. ) Is ion-implanted to form an n-well 6. Subsequently, after removing the photoresist pattern, using the new photoresist pattern (not shown) as a mask, an impurity having a p-type conductivity (for example, in the region where the n-channel MISFET is formed on the silicon substrate 1) B (boron)) is ion-implanted to form the p-well 7. Subsequently, after removing the photoresist pattern, the pad oxide film 2 remaining on the silicon substrate 1 is removed using hydrogen fluoride.

  Next, the silicon substrate 1 is heat-treated in an oxidizing atmosphere to form a silicon oxide film 8 as a gate insulating film on the surfaces of the n-well 6 and the p-well 7 on the silicon substrate 1.

  Next, nitriding is performed on the silicon oxide film 8 on the silicon substrate 1. First, (a) an activated inert element ion breaks a bond between silicon and oxygen (Si—O bond) on the surface of the silicon oxide film 8 on the silicon substrate 1 (hereinafter referred to as “modified”). (B) activated species obtained by activating molecules having nitrogen as one constituent element are introduced into the silicon oxide film 8 (hereinafter referred to as nitriding treatment (b). )).

  Here, in the first embodiment, argon is used as an inert element in the reforming process (a), and nitrogen molecules are used as molecules having nitrogen as one constituent element in the nitriding process (b). In the reforming process (a), a mixed gas containing argon as a main component is activated by plasma to generate ions of inert elements. In the nitriding process (b), a mixed gas containing nitrogen molecules is generated. Was activated by plasma to generate nitrogen active species.

  Next, the reforming process (a) will be described with reference to FIG. 3, and the nitriding process (b) with reference to FIG. 3 and 4 show a state in which a part of the silicon oxide film 8 on the silicon substrate 1 (n well 6 or p well 7 is not shown) is enlarged.

As shown in FIG. 3, when a discharge occurs in a semiconductor manufacturing apparatus into which argon gas has been introduced, argon ions (Ar ⁺ ) having a positive charge are generated by repelling the electrons of argon by free electrons having energy. Occur. The argon ions (Ar ⁺ ) collide with the silicon oxide film 8 on the silicon substrate 1 and break the bond between atoms of silicon and oxygen near the surface of the silicon oxide film 8. Therefore, a layer (modified layer) containing highly reactive silicon atoms exists near the surface of the silicon oxide film 8. Note that by using argon as the inert element, a bond between atoms of silicon and oxygen can be cut, and the manufacturing cost of the semiconductor device can be suppressed.

Next, as shown in FIG. 4, when discharge occurs in the semiconductor manufacturing apparatus into which nitrogen gas is introduced, active species (N ^* ) of nitrogen are generated by free electrons having energy. The active species of nitrogen (N ^* ) are bonded to silicon atoms that are in a highly reactive state near the surface of the silicon oxide film 8 by the modification treatment (a). The reason why the nitrogen molecule is used as the molecule having nitrogen as one constituent element is to obtain only the active species of nitrogen.

As shown in FIG. 4, even if the active species (N ^* ) of nitrogen introduced into the silicon oxide film 8 tries to diffuse to the interface between the silicon oxide film 8 and the silicon substrate 1, it is near the surface of the silicon oxide film 8. Since there are many highly reactive silicon atoms, the nitrogen active species (N ^* ) are first bonded to highly reactive silicon atoms near the surface of the silicon oxide film 8. Therefore, a silicon oxide film 8 in which a region having a relatively low nitrogen concentration and a region having a relatively high nitrogen concentration near the surface of the silicon oxide film 8 are formed at the interface between the silicon oxide film 8 and the silicon substrate 1 is formed. can do.

  When modifying the silicon oxide surface with an inert element, it is important to consider that nitridation is not performed at all or that nitridation does not proceed excessively. This is to prevent nitriding of the portion other than the above-described modified layer on the surface, in particular, the interface between the silicon oxide film 8 and the silicon substrate 1. For this purpose, it is desirable that the concentration of molecules containing nitrogen as one constituent element is 0.3% or less.

  Next, referring to FIG. 5 and FIG. 6, n using the silicon oxide film that has been subjected to the nitriding treatment (the modification treatment (a) and then the nitriding treatment by the nitriding treatment (b)) of the first embodiment The characteristics of the type MISFET are compared with those of an n-type MISFET using a silicon oxide film subjected to a conventional plasma nitriding process (corresponding to the nitriding process of only the nitriding process (b) of the first embodiment).

  FIG. 5 shows the relationship between the gate leakage current and the electron mobility of the n-type MISFET. In FIG. 5, the gate leakage current and electrons of the n-type MISFET using the silicon oxide film subjected to the nitriding treatment of the first embodiment and the n-type MISFET using the silicon oxide film subjected to the conventional plasma nitriding treatment are shown. The mobility is plotted. The figure shows values normalized using the gate leakage current and electron mobility of an n-type MISFET using a silicon oxide film that has not been nitrided.

  From FIG. 5, the n-type MISFET including the silicon oxide film subjected to the nitriding treatment of the first embodiment and the n-type MISFET including the silicon oxide film subjected to the conventional plasma nitriding treatment are not subjected to nitriding treatment. In contrast to the n-type MISFET including the film, the gate leakage current is reduced in both cases. This is because the gate leakage current due to the direct tunneling phenomenon, which is a problem for thinning the silicon oxide film (gate insulating film) with miniaturization, uses the silicon oxide film that has been nitrided as the gate insulating film. It means to decrease by.

  Further, when comparing the electron mobility of the n-type MISFET including the silicon oxide film subjected to the nitriding treatment of the first embodiment and the n-type MISFET including the silicon oxide film subjected to the conventional plasma nitriding treatment, the present embodiment is compared. It can be seen that the n-type MISFET including the silicon oxide film subjected to the nitriding treatment of Form 1 suppresses the decrease in electron mobility. This is considered to be a difference in increase / decrease in interface states and traps in the film due to nitridation of the silicon oxide film. Therefore, the silicon oxide film subjected to the nitriding treatment of the first embodiment can keep the nitrogen concentration at the interface with the silicon substrate lower than the conventional silicon oxide film subjected to the plasma nitriding treatment. ing.

  FIG. 6 shows the relationship between drain current and gate leakage current when a certain voltage is applied. In FIG. 6, the drain current and gate leakage of the n-type MISFET including the silicon oxide film subjected to the nitriding treatment of the first embodiment and the n-type MISFET including the silicon oxide film subjected to the conventional plasma nitriding treatment are illustrated. The current is plotted. In the n-type MISFET including the silicon oxide film subjected to the nitriding treatment of the first embodiment and the n-type MISFET including the silicon oxide film subjected to the conventional plasma nitriding treatment, the drain current also decreases as the gate leakage current decreases. It tends to decrease.

  Here, when comparing the gate leakage current to be constant, the n-type MISFET including the silicon oxide film subjected to the nitriding treatment of the first embodiment includes the silicon oxide film subjected to the conventional plasma nitriding treatment. It can be seen that the drain current is larger than that of the n-type MISFET. Therefore, a silicon oxide film (gate insulating film) having a substantial gate leakage current reduction effect can be obtained by performing the nitriding treatment of the first embodiment.

  Next, as shown in FIG. 7, a polycrystalline silicon film 9a is formed on the silicon oxide film 8 by the CVD method. Subsequently, by using the photoresist pattern (not shown) as a mask, ion implantation is performed to separate the conductivity types of the polycrystalline silicon film 9a. Subsequently, an insulating film 10 is formed on the polycrystalline silicon film 9a.

  Next, a photoresist pattern (not shown) is formed on the insulating film 10. Subsequently, the insulating film 10 and the polycrystalline silicon film 9a are dry-etched using a photoresist pattern (not shown) as a mask, thereby forming the gate electrode 9 made of the polycrystalline silicon film 9a.

  Next, an n-type semiconductor region (extension) 11 is formed by ion-implanting phosphorus or arsenic (As) into the p-well 7 using photolithography technology, and p-type is formed by ion-implanting boron into the n-well 6. A semiconductor region (extension) 12 is formed.

  Next, sidewall spacers 13 are formed on the side surfaces of the gate electrode 9, and then n-type semiconductor regions (sources and drains) 14 are formed by ion implantation of phosphorus or arsenic into the n-type semiconductor regions (extensions) 11. Then, boron is ion-implanted into the p-type semiconductor region (extension) 12 to form a p-type semiconductor region (source, drain) 15. Through the steps so far, the p-channel type MISFET Qp is formed in the n-well 6 and the n-channel type MISFET Qn is formed in the p-well 7.

  Next, an interlayer insulating film 16 made of a silicon oxide film is formed on the n channel MISFET Qn and the p channel MISFET Qp by, for example, a CVD method.

  Next, as shown in FIG. 8, the surface of the interlayer insulating film 16 is polished by the CMP method, and the surface is processed to be flat. Subsequently, the interlayer insulating film 16 is dry-etched using a photoresist pattern (not shown) as a mask, so that the n-type semiconductor region (source / drain) 14 and the p-type semiconductor region (source / drain) 15 are formed on the upper portion. A contact hole 17 is formed.

  Next, on the silicon substrate 1 including the inside of the contact hole 17, a barrier conductor film is formed by sequentially accumulating, for example, a titanium (Ti) film and a titanium nitride (TiN) film by sputtering, and then further by CVD. For example, a tungsten film is formed and the contact hole 17 is filled with the tungsten film. Thereafter, the titanium film, the titanium nitride film, and the tungsten film on the interlayer insulating film 16 are removed by the CMP method, and the plug 18 is formed.

  Next, a silicon nitride film 19 is formed as an etching stopper film on the silicon substrate 1 by a CVD method. This is to avoid damaging the lower layer or degrading the processing dimensional accuracy when forming grooves or holes for wiring formation in the insulating film on the etching stopper film. is there.

  Next, a silicon oxide film to be the interlayer insulating film 20 is formed on the surface of the silicon nitride film 19 by a CVD method. Subsequently, by using the photoresist pattern as a mask, the silicon nitride film 19 and the interlayer insulating film 20 are dry-etched to form a wiring trench for forming a buried wiring. Subsequently, in order to remove the reaction layer on the surface of the plug 18 exposed at the bottom of the wiring groove, the surface treatment of the silicon substrate 1 is performed by sputter etching in an argon atmosphere.

  Next, a copper film is formed on the entire surface of the silicon substrate 1 so as to fill the wiring trenches, and this is used as a wiring layer 21. The wiring layer 21 and the interlayer insulating film 20 are polished by CMP to flatten the surface. Process.

  After the formation of the wiring layer, for example, by repeating the same process as described with reference to FIG. 8, wiring is formed in multiple layers on the wiring layer, and the entire silicon substrate 1 is covered with a passivation film. Thus, the CMOS device is almost completed.

(Embodiment 2)
Next, an example of a method for manufacturing a CMOS device according to the second embodiment of the present invention will be described in the order of steps. Since the MISFET device structure related to the second embodiment is the same as that of the first embodiment, detailed description thereof is omitted.

  In the second embodiment, the gate insulating film processing step is different from that of the first embodiment. Therefore, the process until the silicon oxide film 8 (gate insulating film) on the silicon substrate 1 is formed as shown in FIG.

  That is, as shown in FIG. 2, after the silicon oxide film 8 is formed on the silicon substrate 1, the mixed gas containing the inert element and the molecule having nitrogen as one constituent element is activated to oxidize. The silicon film 8 is nitrided. Here, in the second embodiment, activation is performed by plasma, argon is used as an inert element, and nitrogen molecules are used as molecules having nitrogen as one constituent element.

  FIG. 9 shows a state in which a part of the silicon oxide film 8 on the silicon substrate 1 (n well 6 or p well 7 is not shown) is enlarged.

When a discharge occurs in a semiconductor manufacturing system into which nitrogen gas and argon gas have been introduced, the active species of nitrogen (N ^* ) are generated by free electrons with energy, and positive electrons are discharged by repelling the argon electrons. Argon ions (Ar ⁺ ) are generated. The argon ions (Ar ⁺ ) collide with the silicon oxide film 8 on the silicon substrate 1 and break the bond between atoms of silicon and oxygen near the surface of the silicon oxide film 8. Therefore, highly reactive silicon atoms exist near the surface of the silicon oxide film 8. Further, the active species of nitrogen (N ^* ) are bonded to highly reactive silicon atoms.

As described above, even if the active species (N ^* ) of nitrogen introduced into the silicon oxide film 8 tries to diffuse to the interface between the silicon oxide film 8 and the silicon substrate 1, there is a reactivity near the surface of the silicon oxide film 8. Since there are many high-temperature silicon atoms, the nitrogen active species (N ^* ) are first bonded to highly reactive silicon atoms near the surface of the silicon oxide film 8. Therefore, a silicon oxide film 8 in which a region having a relatively low nitrogen concentration and a region having a relatively high nitrogen concentration near the surface of the silicon oxide film 8 are formed at the interface between the silicon oxide film 8 and the silicon substrate 1 is formed. can do.

  In addition, when excessive active species of nitrogen are generated in the processing atmosphere, there is a concern that portions other than the above-described modified layer on the surface, particularly the interface between the silicon oxide film 8 and the silicon substrate 1 may be nitrided. For this reason, it is desirable that the concentration of molecules having nitrogen as a constituent element be 0.3% or less.

  Needless to say, even if ions other than active species are generated with respect to nitrogen, there is no problem in achieving the present invention.

  Next, the process after nitriding the silicon oxide film 8 on the silicon substrate 1 leads to the process described with reference to FIGS. 7 and 8 in the first embodiment, and finally the CMOS device is substantially completed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first and second embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the first and second embodiments, argon is used as the inert element and nitrogen molecules are used as molecules having nitrogen as one constituent element, but He, Xe, or a mixed gas thereof is used instead of argon. May be used, and NH ₃ , NO, or the like may be used instead of nitrogen molecules.

For example, in the first and second embodiments, the silicon oxide film is used as the gate insulating film, but the same effect as described above can be obtained even if a silicon oxynitride film is used as the gate insulating film. As a method for forming a silicon oxynitride film, a method in which a silicon oxide film formed on a silicon substrate is annealed at a high temperature of about 900 to 1100 ° C. in an atmosphere containing NO gas or NO ₂ gas, It is formed by a method of directly annealing under conditions or a method of depositing on a silicon substrate by CVD.

  The manufacturing technology of the MISFET of the present invention can be applied to a logic device using a CMOS device, an SOC (System On a Chip), and a DRAM embedded LSI.

It is principal part sectional drawing explaining the manufacturing method of the semiconductor device by Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; It is a principal part expanded sectional view in the manufacturing process of a semiconductor device. It is a principal part expanded sectional view in the manufacturing process of a semiconductor device. FIG. 3 is a relationship diagram between a gate leakage current and an electron mobility of the n-type MISFET according to the first embodiment of the present invention. FIG. 4 is a relationship diagram between a drain current and a gate leakage current of the n-type MISFET according to the first embodiment of the present invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 7 is a diagram for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention, and is an enlarged cross-sectional view of the main part in the semiconductor device manufacturing process following FIG. 2.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Pad oxide film 3 Silicon nitride film 4 Silicon oxide film 5a Element isolation trench 5 Element isolation part 6 N well 7 P well 8 Silicon oxide film (gate insulating film)
9a Polycrystalline silicon film 9 Gate electrode 10 Insulating film 11 N-type semiconductor region (extension)
12 p-type semiconductor region (extension)
13 Side wall spacer 14 n-type semiconductor region (source, drain)
15 p-type semiconductor region (source, drain)
16 Interlayer insulation film 17 Contact hole 18 Plug 19 Silicon nitride film 20 Interlayer insulation film 21 Wiring layer Qn n channel type MISFET
Qp p-channel MISFET

Claims (4)

A method for manufacturing a semiconductor device for forming a MISFET on a semiconductor substrate, comprising:
(A) forming a gate insulating film containing silicon oxide as a main component on the main surface of the semiconductor substrate;
(B) exposing the gate insulating film to an atmosphere in which a mixed gas having an inert element as a main component and nitrogen as a constituent element and having a concentration of molecules of 0.3% or less is activated;
(C) after the step (b), introducing a molecular active species having nitrogen as a constituent element into the gate insulating film;
(D) after the step (c), forming a gate electrode of the MISFET on the gate insulating film;
A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device for forming a MISFET on a semiconductor substrate, comprising:
(A) forming a gate insulating film containing silicon oxide as a main component on the main surface of the semiconductor substrate;
(B) In an atmosphere in which a mixed gas containing an inert element and a molecule having nitrogen as one constituent element and having a concentration of the molecule having nitrogen as one constituent element is 0.3% or less is activated, Introducing the active species of molecules having nitrogen as a constituent element into the gate insulating film by exposing the gate insulating film;
(C) after the step (b), forming a gate electrode of the MISFET on the gate insulating film;
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the inert element is argon.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the molecule having nitrogen as one constituent element is a nitrogen molecule.

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