KR100259072B1 - Method for forming metal gate - Google Patents

Method for forming metal gate Download PDF

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KR100259072B1
KR100259072B1 KR1019970072484A KR19970072484A KR100259072B1 KR 100259072 B1 KR100259072 B1 KR 100259072B1 KR 1019970072484 A KR1019970072484 A KR 1019970072484A KR 19970072484 A KR19970072484 A KR 19970072484A KR 100259072 B1 KR100259072 B1 KR 100259072B1
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layer
metal
metal gate
etching
plasma
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KR1019970072484A
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Korean (ko)
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KR19990052941A (en
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하재희
지승헌
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen

Abstract

PURPOSE: A method of forming a metal gate is provided to improve an electrical characteristic of the device by minimizing the loss of the metal gate due to etching. CONSTITUTION: On the substrate(11), a first insulation layer(12) is formed. Thereon, a polysilicon layer(13) is formed on which a diffusion prevention layer(14) is formed. Here, instead of the polysilicon layer(13), a TiN layer can be formed. The diffusion prevention layer(14) is made of TiN or WSiN. After forming the diffusion prevention layer(14), a metal layer(15) is formed thereon. Material for the metal layer(15) is one of tungsten, molybden silicide, tungsten silicide, and molybden silicide. A second insulation layer(16) for hard mask is formed on the metal layer(15) and then photoresist is doped thereon. The photoresist is patterned by light-exposure or photo-developing process and used for a mask to remove the second insulation layer(16). Using a plasma including a fluorine, the metal layer and the diffusion prevention layer are etched. Using a plasma including a chlorine, the polysilicon layer(13) is selectively etched to form a sidewall protection layer on both sidewalls of the metal layer, the diffusion prevention layer and the polysilicon layer. A wet-cleaning process using H2O2 is performed to complete the process for forming metal gate.

Description

금속게이트 형성방법Metal gate formation method

본 발명은 반도체소자에 관한 것으로 특히, 반도체소자의 금속게이트 형성방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a method of forming a metal gate of a semiconductor device.

반도체소자가 고집적화 되면서 고속의 LSI의 필요성이 더욱 커지고 있다.As semiconductor devices are highly integrated, the need for high-speed LSI is increasing.

이를 만족시키기 위해서 저항이 낮은 금속게이트에 대한 관심이 커지고 있는 추세이다.In order to satisfy this, interest in metal gates with low resistance is increasing.

이중 폴리실리콘상에 텅스텐(W) 또는 몰리브덴(Mo) 또는 실리사이드층이 형성된 금속게이트의 전기적특성에 대한 연구가 계속되고 있다.Research on the electrical properties of metal gates in which tungsten (W), molybdenum (Mo), or silicide layers are formed on the polysilicon is continuing.

이하, 종래기술에 따른 금속게이트 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a metal gate according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 1d는 종래 금속게이트 형성방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a conventional method for forming a metal gate.

먼저, 도 1a에 도시한 바와같이, 기판(11)상에 제 1 절연층(12)을 형성하고, 상기 제 1 절연층(12)상에 폴리실리콘층(13)을 형성한다.First, as shown in FIG. 1A, a first insulating layer 12 is formed on a substrate 11, and a polysilicon layer 13 is formed on the first insulating layer 12.

상기 폴리실리콘층(13)상에 확산방지층(14)을 형성하고, 상기 확산방지층(14)상에 금속층(15)을 형성한다.The diffusion barrier layer 14 is formed on the polysilicon layer 13, and the metal layer 15 is formed on the diffusion barrier layer 14.

여기서, 상기 확산방지층(14)은 티타늄나이트라이드(TiN) 또는 텅스텐실리콘나이트라이드(WSiN)를 사용한다.Here, the diffusion barrier layer 14 uses titanium nitride (TiN) or tungsten silicon nitride (WSiN).

그리고, 상기 금속층(15)으로써는 텅스텐, 몰리브덴, 텅스텐 실리사이드, 몰리브텐 실리사이드층 중 어느하나를 사용한다.As the metal layer 15, any one of tungsten, molybdenum, tungsten silicide, and molybdenum silicide layer is used.

그리고, 상기 금속층(15)상에 하드 마스크용 제 2 절연층(16)을 형성하고, 상기 제 2 절연층(16)상에 포토레지스트(17)를 도포한다.A second insulating layer 16 for hard mask is formed on the metal layer 15, and a photoresist 17 is coated on the second insulating layer 16.

노광 및 현상공정으로 상기 포토레지스트(17)를 패터닝한다.The photoresist 17 is patterned by an exposure and development process.

이어, 도 1b에 도시한 바와같이, 상기 패터닝된 포토레지스트(17)를 마스크로 이용한 식각공정으로 상기 제 2 절연층(16)을 선택적으로 제거하여 마스크패턴(16a)을 형성한다.Subsequently, as illustrated in FIG. 1B, the mask pattern 16a is formed by selectively removing the second insulating layer 16 by an etching process using the patterned photoresist 17 as a mask.

이어, 도 1c에 도시한 바와같이, 상기 포토레지스트(17)를 제거하고, 상기 마스크패턴(16a)을 마스크로 이용한 식각공정으로 금속층(15), 확산방지층(14), 그리고 폴리실리콘층(13)을 차례로 식각한다.Subsequently, as illustrated in FIG. 1C, the metal layer 15, the diffusion barrier layer 14, and the polysilicon layer 13 are removed by the etching process using the photoresist 17 and using the mask pattern 16a as a mask. ) Is sequentially etched.

이때, 플루오린 가스와 HCl와, HBr가 혼합된 가스를 이용하여 1차적으로 식각하고, SiCl4에 불활성가스, CO, N2, O2가 혼합된 가스를 이용하여 2차적으로 식각한다.At this time, the fluorine gas, HCl and HBr is firstly etched using a gas mixed, and inert gas, CO, N 2 , O 2 is mixed with SiCl 4 by using a gas mixed.

이어서, 별도로 H2O2를 포함한 Wet 클리닝으로 식각시 발생한 잔류물을 제거하여 도 1d에 도시한 바와같이, 금속게이트를 형성한다.Subsequently, residues generated during etching are separately removed by wet cleaning including H 2 O 2 to form metal gates as shown in FIG. 1D.

그러나 상기와 같은 종래 금속게이트 형성방법을 다음과 같은 문제점이 있었다.However, the conventional metal gate forming method as described above has the following problems.

첫째, 텅스텐, 텅스텐나이트라이드등과 같은 금속은 식각시 손실량이 커지므로 H2O2를 포함하는 Wet크리닝을 진행할 수가 없다.First, metals such as tungsten, tungsten nitride, etc., cannot be subjected to wet cleaning including H 2 O 2 because the amount of loss during etching increases.

둘째, 후속으로 셀 리키지를 개선시키기 위해 진행하는 게이트 리옥시데이션(reoxidation)시 금속또한 산화되어 소자특성을 저하시킨다.Secondly, the metal is also oxidized during gate reoxidation, which is subsequently performed to improve the cell package, thereby degrading device characteristics.

본 발명은 상기한 문제점을 해결하기 위해 안출한 것으로써, 금속의 손실이 없고, 게이트저항 등의 소자의 특성이 악화되는 것을 방지하는데 적당한 금속게이트 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of forming a metal gate suitable for preventing the loss of metal and deteriorating characteristics of an element such as a gate resistance.

도 1a 내지 1d는 종래 금속게이트 형성방법을 설명하기 위한 공정단면도1A to 1D are cross-sectional views illustrating a method of forming a conventional metal gate.

도 2a 내지 2d는 본 발명의 금속게이트 형성방법을 설명하기 위한 공정단면도2A through 2D are cross-sectional views illustrating a method of forming a metal gate according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

11 : 기판 12 : 제 1 절연층11 substrate 12 first insulating layer

13 : 폴리실리콘층 14 : 확산방지층13: polysilicon layer 14: diffusion barrier layer

15 : 금속층 16 : 제 2 절연층15 metal layer 16 second insulating layer

16a : 마스크패턴 17 : 포토레지스트16a: mask pattern 17: photoresist

18 : 측벽보호막18: sidewall protective film

상기의 목적을 달성하기 위한 본 발명의 금속게이트 형성방법은 기판상에 제 1 절연층, 폴리실리콘층, 확산방지층, 금속층, 그리고 제 2 절연층을 적층형성하는 공정과, 플루오린을 포함한 플라즈마를 이용하여 상기 제 2 절연층을 선택적으로 제거하여 마스크패턴을 형성하는 공정과, 플루오린을 포함한 플라즈마를 이용하여 상기 금속층과 확산방지층을 선택적으로 식각하는 공정과, 클로린을 포함한 플라즈마를 이용하여 상기 폴리실리콘층을 선택적으로 식각하여 상기 금속층, 확산방지층, 그리고 폴리실리콘층의 양측면에 측벽보호막을 형성하는 공정과, H2O2를 포함한 크리닝을 진행하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The metal gate forming method of the present invention for achieving the above object is a step of laminating a first insulating layer, a polysilicon layer, a diffusion barrier layer, a metal layer, and a second insulating layer on a substrate, and a plasma containing fluorine Selectively removing the second insulating layer to form a mask pattern; selectively etching the metal layer and the diffusion barrier layer using a plasma containing fluorine; and using the plasma using chlorine. And selectively etching the silicon layer to form sidewall protective films on both sides of the metal layer, the diffusion barrier layer, and the polysilicon layer, and performing a cleaning process including H 2 O 2 .

이하, 본 발명의 금속게이트 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a metal gate of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 2d는 본 발명의 금속게이트 형성방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a metal gate according to the present invention.

먼저, 도 2a에 도시한 바와같이, 기판(11)상에 제 1 절연층(12)을 형성한다.First, as shown in FIG. 2A, the first insulating layer 12 is formed on the substrate 11.

상기 제 1 절연층(12)상에 폴리실리콘층(13)을 형성하고, 상기 폴리실리콘층(13)상에 확산방지층(14)을 형성한다.The polysilicon layer 13 is formed on the first insulating layer 12, and the diffusion barrier layer 14 is formed on the polysilicon layer 13.

이때, 상기 폴리실리콘층(13)대신에 티타늄나이트라이드(TiN)을 형성할 수도 있다. 그리고 상기 확산방지층(14)은 티타늄나이트라이드(TiN), 텅스텐실리콘나이트라이드(WSiN)중 어느하나를 사용한다.In this case, titanium nitride (TiN) may be formed instead of the polysilicon layer 13. The diffusion barrier layer 14 uses any one of titanium nitride (TiN) and tungsten silicon nitride (WSiN).

여기서, 상기 폴리실리콘층(13)대신에 티타늄나이트라이드를 사용할 경우, 상기 확산방지층(14)을 형성하지 않아도 무관하다.In this case, when titanium nitride is used instead of the polysilicon layer 13, the diffusion barrier layer 14 may not be formed.

이와같이, 폴리실리콘층(13)상에 확산방지층(14)을 형성한 후, 상기 확산방지층(14)상에 금속층(15)을 형성한다.As such, after the diffusion barrier layer 14 is formed on the polysilicon layer 13, the metal layer 15 is formed on the diffusion barrier layer 14.

여기서, 상기 금속층(15)의 물질은 텅스텐, 몰리브덴, 텅스텐 실리사이드, 몰리브텐 실리사이드중 어느하나를 사용한다.Here, the material of the metal layer 15 is any one of tungsten, molybdenum, tungsten silicide, molybdenum silicide.

이어서, 상기 금속층(15)상에 하드마스크용 제 2 절연층(16)을 형성하고, 상기 제 2 절연층(16)상에 포토레지스트(17)를 도포한다.Subsequently, a second insulating layer 16 for hard mask is formed on the metal layer 15, and a photoresist 17 is coated on the second insulating layer 16.

이후, 노광 및 현상공정으로 상기 포토레지스트(17)를 패터닝하고, 상기 패터닝된 포토레지스트(17)를 마스크로 이용한 식각공정으로 도 2b에 도시한 바와같이, 제 2 절연층(16)을 제거하여 마스크패턴(16a)을 형성한다.Thereafter, the photoresist 17 is patterned by an exposure and development process, and an etching process using the patterned photoresist 17 as a mask is performed to remove the second insulating layer 16 as illustrated in FIG. 2B. The mask pattern 16a is formed.

이때, 상기 제 2 절연층(16)은 플루오린 플라즈마에서 식각하며 식각장비로서는 반응성 이온식각장비를 사용한다.In this case, the second insulating layer 16 is etched in fluorine plasma, and the reactive ion etching equipment is used as the etching equipment.

이어, 도 2c에 도시한 바와같이, 플루오린(fluorine)를 포함한 가스, 클로린(chlorine)을 포함한 가스, 블로민(bromine)을 포함한 가스, 불활성가스를 포함한 가스, CO, N2, O2가스중 어느하나를 포함한 플라즈마를 사용하여 상기 금속층(15), 확산방지층(14)을 식각한다.Subsequently, as illustrated in FIG. 2C, a gas containing fluorine, a gas containing chlorine, a gas containing bromine, a gas containing an inert gas, CO, N 2 and O 2 gas The metal layer 15 and the diffusion barrier layer 14 are etched using a plasma including any one of them.

이때 식각장비로서는 MERIE(Magnetically enhanced reactixe ion etcher)를 사용한다.At this time, as an etching apparatus, MERIE (Magnetically enhanced reactixe ion etcher) is used.

상기 클로린을 포함한 가스로서는 Cl2, CCl4, BCl3, SiCl4, HCl, CHXClY등을 사용한다.As the gas containing chlorine, Cl 2 , CCl 4 , BCl 3 , SiCl 4 , HCl, CH X Cl Y and the like are used.

그리고 불활성가스로서는 He, Ar 등을 사용한다.And as an inert gas, He, Ar, etc. are used.

이후, 스퍼터링 또는 플라즈마내에서 폴리실리콘층(13)을 식각하며, 식각장비로서는 고밀도 플라즈마 식각장비(HDP :High density plasma etcher)를 사용한다.Thereafter, the polysilicon layer 13 is etched in the sputtering or plasma, and a high density plasma etcher (HDP) is used as the etching equipment.

여기서, Cl2와 O2를 포함하는 플라즈마를 사용할 경우, O2의 유량이 20sccm이하고 유지하며, O의 유량을 전체유량에 대해 8∼40%범위내로 유지한다. 그리고 바이어스 파워는 250W이하로 유지한다.Here, when using a plasma containing Cl 2 and O 2 , the flow rate of O 2 is maintained at 20 sccm or less, and the flow rate of O is maintained within the range of 8 to 40% with respect to the total flow rate. The bias power is kept below 250W.

이때, 상기 폴리실리콘층(13)을 식각함에 있어서, 상기 폴리실리콘과 패시베이션가스(passivation gas)의 반응에 의해서 도 2d에 도시한 바와같이, 상기 금속층(15), 확산방지층(14), 그리고 폴리실리콘층(13)의 양측면에 측벽보호막(18)이 형성된다.At this time, in etching the polysilicon layer 13, as shown in Figure 2d by the reaction of the polysilicon and the passivation gas (passivation gas), the metal layer 15, the diffusion barrier layer 14, and poly Sidewall protective films 18 are formed on both sides of the silicon layer 13.

여기서, 상기 플라즈마의 식각조건과 식각시간을 조절함으로써 상기 측벽보호막(18)의 두께를 조절할 수 있다.Here, the thickness of the sidewall passivation layer 18 may be adjusted by controlling the etching conditions and the etching time of the plasma.

이후, H2O2를 포함한 Wet크리닝을 진행하면 본 발명에 따른 금속게이트 형성공정이 완료된다.Subsequently, when the Wet cleaning including H 2 O 2 is performed, the metal gate forming process according to the present invention is completed.

이상 상술한 바와같이, 본 발명의 금속게이트 형성방법은 H2O2를 포함하는 Wet크리닝을 진행하더라도 측벽보호막에 의해 게이트용 금속층의 손실이 없다.As described above, the metal gate forming method of the present invention does not lose the gate metal layer by the sidewall protective film even when the wet cleaning including H 2 O 2 is performed.

또한, 후속으로 진행되는 게이트 리옥시데이션(reoxidation)시, 금속층이나 확산방지층이 산화되는 것을 방지하므로 소자의 특성을 향상시키는 효과가 있다.In addition, since the metal layer or the diffusion barrier layer is prevented from being oxidized during the subsequent gate reoxidation, there is an effect of improving the characteristics of the device.

Claims (11)

기판상에 제 1 절연층, 폴리실리콘층, 확산방지층, 금속층, 그리고 제 2 절연층을 적층형성하는 공정과,Laminating a first insulating layer, a polysilicon layer, a diffusion barrier layer, a metal layer, and a second insulating layer on the substrate; 플루오린을 포함한 플라즈마를 이용하여 상기 제 2 절연층을 선택적으로 제거하여 마스크패턴을 형성하는 공정과,Selectively removing the second insulating layer using a plasma containing fluorine to form a mask pattern; 플루오린을 포함한 플라즈마를 이용하여 상기 금속층과 확산방지층을 선택적으로 식각하는 공정과,Selectively etching the metal layer and the diffusion barrier layer using a plasma containing fluorine, 클로린을 포함한 플라즈마를 이용하여 상기 폴리실리콘층을 선택적으로 식각하여 상기 금속층, 확산방지층, 그리고 폴리실리콘층의 양측면에 측벽보호막을 형성하는 공정과,Selectively etching the polysilicon layer using a plasma containing chlorine to form sidewall protective films on both sides of the metal layer, the diffusion barrier layer, and the polysilicon layer, H2O2를 포함한 크리닝을 진행하는 공정을 포함하여 이루어지는 것을 특징으로 하는 금속게이트 형성방법.A metal gate forming method comprising the step of performing a cleaning including H 2 O 2 . 제 1 항에 있어서,The method of claim 1, 상기 금속층 및 확산방지층의 식각은 플루오린을 포함한 플라즈마 이외에 클로린(chlorine)을 포함한 가스, 블로민(bromine)을 포함한 가스, 불활성가스를 포함한 가스, CO, N2, O2가스중 어느하나를 포함한 플라즈마를 사용하여 식각하는 것을 특징으로 하는 금속게이트 형성방법.Etching of the metal layer and the diffusion barrier layer includes any one of a gas containing chlorine, a gas containing bromine, a gas containing an inert gas, and a CO, N 2 , and O 2 gas in addition to a plasma containing fluorine. A metal gate forming method comprising etching using a plasma. 제 1 항에 있어서,The method of claim 1, 상기 클로린을 포함한 가스로서는 Cl2, CCl4, BCl3, SiCl4, HCl, CHXClY중 어느하나를 사용하는 것을 특징으로 하는 금속게이트 형성방법.As the gas containing chlorine, any one of Cl 2 , CCl 4 , BCl 3 , SiCl 4 , HCl, CH X Cl Y is used. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연층은 RIE(Reactive ion etch)장비를 사용하여 식각하는 것을 특징으로 하는 금속게이트 형성방법.And the second insulating layer is etched using reactive ion etch (RIE). 제 1 항에 있어서,The method of claim 1, 상기 금속층, 확산방지층은 MERIE(Magnetically enhanced RIE)장비를 사용하여 식각하는 것을 특징으로 하는 금속게이트 형성방법.The metal layer and the diffusion barrier layer is a metal gate forming method characterized in that the etching using MERIE (Magnetically enhanced RIE) equipment. 제 1 항에 있어서,The method of claim 1, 상기 측벽보호막의 두께는 클로린을 포함한 플라즈마 식각에 따른 시간에 의해 결정되는 것을 특징으로 하는 금속게이트 형성방법.The thickness of the sidewall protective layer is determined by the time according to the plasma etching including chlorine metal gate forming method. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘층은 고밀도 식각장비(HDP :High density plasma)를 이용하여 식각하는 것을 특징으로 하는 금속게이트 형성방법.Wherein the polysilicon layer is etched using a high density plasma (HDP). 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘층은 Cl2와 O2가스를 포함한 혼합플라즈마내에서 식각하는 것을 포함함을 특징으로 하는 금속게이트 형성방법.The polysilicon layer is a metal gate forming method comprising etching in a mixed plasma containing Cl 2 and O 2 gas. 제 8 항에 있어서,The method of claim 8, 상기 Cl2와 O2가스를 포함한 혼합플라즈마 식각시 O의 유량을 20sccm이하로 하거나 또는 전체유량의 8∼40%범위로 유지하고 바이어스 파워는 250W이하로 유지하는 것을 특징으로 하는 금속게이트 형성방법.When the mixed plasma etching containing the Cl 2 and O 2 gas, the flow rate of O is maintained at 20sccm or less or 8 to 40% of the total flow rate and the bias power is 250W or less characterized in that the metal gate formation method. 제 1 항에 있어서,The method of claim 1, 상기 금속은 텅스텐, 텅스텐나이트라이드, 티타늄나이트라이드중 어느하나를 사용하는 것을 특징으로 하는 금속게이트 형성방법.The metal is a metal gate forming method using any one of tungsten, tungsten nitride, titanium nitride. 제 1 항에 있어서,The method of claim 1, 상기 확산방지층은 티타늄나이트라이드(TiN), 텅스텐실리콘나이트라이드(WSiN)중 어느하나를 사용하는 것을 특징으로 하는 금속게이트 형성방법.The diffusion barrier layer is any one of titanium nitride (TiN), tungsten silicon nitride (WSiN) using a metal gate forming method.
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