KR100259069B1 - Method for etching multilayer film of semiconductor device - Google Patents

Method for etching multilayer film of semiconductor device Download PDF

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KR100259069B1
KR100259069B1 KR1019970074387A KR19970074387A KR100259069B1 KR 100259069 B1 KR100259069 B1 KR 100259069B1 KR 1019970074387 A KR1019970074387 A KR 1019970074387A KR 19970074387 A KR19970074387 A KR 19970074387A KR 100259069 B1 KR100259069 B1 KR 100259069B1
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etching
chamber
layer
gas
range
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KR1019970074387A
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KR19990054558A (en
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하재희
지승헌
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Abstract

PURPOSE: A method of etching a multi-level layer of a semiconductor device is provided to increase the representation of the etching process and provide a method of etching a multi-level layer of a semiconductor device having a vertical profile. CONSTITUTION: The semiconductor substrate on which a first insulation layer, semiconductor layer, diffusion barrier layer and metal layer are successively deposited is put into a first chamber to which the etching gas mixed with the fluorine etching gas excluding carbon, oxygen gas and nitrogen gas is injected to etch the metal layer and the diffusion barrier layer and moreover to etch the substrate to a predetermined depth. The semiconductor substrate is put into a second chamber to which the etching gas mixed with the chlorine gas and oxygen is injected to overetch the semiconductor device.

Description

반도체 소자의 다층막 식각방법Multi-layer Etching Method of Semiconductor Device

본 발명은 반도체 소자의 다층막 식각방법에 대한 것으로 특히, 식각 프로파일이 안정적인 반도체 소자의 다층막 식각방법에 관한 것이다.The present invention relates to a method for etching a multilayer film of a semiconductor device, and more particularly, to a method for etching a multilayer film of a semiconductor device having a stable etching profile.

반도체 소자가 고집적화 되면서 고속의 LSI의 필요성이 더욱커지고 있다. 이를 만족시키기 위해 저항이 낮은 금속게이트에 대한 관심이 커지고 있다. 이중 특히 폴리실리콘층상에 텅스텐(W)이나 몰리부덴(Mo)이나 실리사이드 중에 하나가 증착된 저저항 금속게이트에 대한 연구가 활발히 진행중이다.As semiconductor devices are highly integrated, the need for high-speed LSI is increasing. In order to satisfy this, there is a growing interest in low-resistance metal gates. In particular, research is being actively conducted on low-resistance metal gates in which one of tungsten (W), molybdenum (Mo) or silicide is deposited on a polysilicon layer.

첨부 도면을 참조하여 종래 반도체 소자의 다층막 식각방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of etching a multilayer film of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 1c는 종래 반도체 소자의 다층막 식각방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of etching a multilayer film of a conventional semiconductor device.

종래 반도체 소자의 다층막 식각방법은 도 1a에 도시한 바와 같이 반도체 기판(1)에 실리콘산화막(2)과 폴리실리콘층(3)을 차례로 증착한다. 그리고 폴리실리콘층(3)상에 티타늄 나이트라이드(TiN)나 텅스텐 실리콘 나이트라이드(WSiN)와 같은 물질을 증착하여 확산방지막(4)을 형성한다. 이후에 확산방지막(4)상에 텅스텐이나 몰리부덴(Mo)을 증착하여 금속층(5)을 형성한다. 또는 확산방지막(4)과 금속층(5)을 증착하지 않고 직접 금속실리사이드를 증착할 수 도 있다. 그리고 금속층(5)상에 질화막이나 산화막을 증착하여 하드마스크층(6)을 형성한다. 하드마스크층(6)상에 감광막(7)을 도포한 후에 노광 및 현상공정으로 소정부분을 선택적으로 패터닝한다.In the multilayer film etching method of the conventional semiconductor device, as shown in FIG. 1A, the silicon oxide film 2 and the polysilicon layer 3 are sequentially deposited on the semiconductor substrate 1. The diffusion barrier layer 4 is formed by depositing a material such as titanium nitride (TiN) or tungsten silicon nitride (WSiN) on the polysilicon layer 3. Thereafter, tungsten or molybdenum (Mo) is deposited on the diffusion barrier 4 to form the metal layer 5. Alternatively, the metal silicide may be directly deposited without depositing the diffusion barrier 4 and the metal layer 5. Then, a nitride film or an oxide film is deposited on the metal layer 5 to form the hard mask layer 6. After applying the photosensitive film 7 on the hard mask layer 6, predetermined portions are selectively patterned by exposure and development processes.

도 1b에 도시한 바와 같이 패터닝된 감광막(7)을 마스크로 이용하여 하드마스크층(6)을 상기 금속층(5)이 드러나도록 이방성 식각한 후에 감광막(7)을 제거한다.As shown in FIG. 1B, the photoresist layer 7 is removed after anisotropic etching of the hard mask layer 6 to expose the metal layer 5 using the patterned photoresist layer 7 as a mask.

도 1c에 도시한 바와 같이 식각된 하드마스크층(6)을 마스크로 이용하여 먼저 플로린가스, SF6, NF3+HCl, HBr, Cl2, Br2, 그리고 CCl4를 서로 혼합한 가스로 금속층(5)과 확산방지막(4)과 폴리실리콘층(3)을 소정깊이로 이방성 식각한다. 이후에 SiCl4+인너가스(inert gas), N2, O2, 그리고 CO 혹은 HBr가스를 이용하여 폴리실리콘층(3)을 실리콘산화막(2)이 드러날때까지 식각한다. 이때 식각가스에 의해서 실리콘산화막(2)상에 식각잔여물(7)이 생길 수 있다.As shown in FIG. 1C, the metal layer is a gas obtained by mixing Florin gas, SF 6 , NF 3 + HCl, HBr, Cl 2 , Br 2 , and CCl 4 with each other using the etched hard mask layer 6 as a mask. (5), the diffusion barrier film 4 and the polysilicon layer 3 are anisotropically etched to a predetermined depth. Thereafter, the polysilicon layer 3 is etched using SiCl 4 + inner gas, N 2, O 2, and CO or HBr gas until the silicon oxide film 2 is exposed. At this time, the etching residue 7 may be generated on the silicon oxide film 2 by the etching gas.

상기와 같은 종래 반도체 소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.

첫째, 다층막을 식각하기 위해서 먼저 플로린계와, 클로린계와, 브로마인계 가스를 혼용해서 쓰기 때문에 챔버의 벽에 폴리머가 증착되므로 공정 재현성이 떨어지고 세정 주기가 짧다.First, in order to etch the multilayer film, first, a mixture of florin-based, chlorine-based, and bromine-based gases is used, so that polymers are deposited on the walls of the chamber, resulting in poor process reproducibility and short cleaning cycles.

둘째, 상부 금속층과 폴리실리콘층 사이에 언더컷을 방지하기 위하여 Br계가스를 사용하여 측벽 보호막을 형성하고 있으나 브로마이드 반응 프로덕트의 기상압력이 낮아서 식각된 표면에 식각잔여물이 남기 때문에 별도의 세정 공정이 요구된다.Second, sidewall protection layer is formed by using Br-based gas to prevent undercut between the upper metal layer and the polysilicon layer. Required.

본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 식각공정의 재현성을 높이고 수직프로파일을 갖는 반도체 소자의 다층막 식각방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a multilayer film etching method of a semiconductor device having a vertical profile and improving the reproducibility of the etching process to solve the above problems.

도 1a 내지 1c는 종래 반도체 소자의 다층막 식각방법을 나타낸 공정단면도1A through 1C are cross-sectional views illustrating a method of etching a multilayer film of a conventional semiconductor device.

도 2a 내지 2c는 본 발명 반도체 소자의 다층막 식각방법을 나타낸 공정단면도2A through 2C are cross-sectional views illustrating a method of etching a multilayer film of a semiconductor device according to the present invention.

도 3은 플로린 식각가스에 산소가스만 넣어 반도체 소자의 다층막을 식각하였을 때의 사진FIG. 3 is a photograph of when a multilayer film of a semiconductor device is etched by only putting oxygen gas into a fluorine etching gas

도 4는 본 발명에 따라 반도체 소자의 다층막을 식각하였을 때의 사진4 is a photograph when the multilayer film of the semiconductor device is etched according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21: 반도체 기판 22: 실리콘산화막21: semiconductor substrate 22: silicon oxide film

23: 폴리실리콘층 24: 확산방지막23: polysilicon layer 24: diffusion barrier

25: 금속층 26: 하드마스크층25: metal layer 26: hard mask layer

27: 감광막27: photosensitive film

상기와 같은 목적을 달성하기 위한 본 발명 반도체 소자의 다층막 식각방법은 제 1 절연막과 반도체층과 확산방지막과 금속층이 차례로 증착되어 있는 반도체 기판에 있어서, 상기와 같이 다층막이 형성된 상기 반도체기판을 제 1 챔버에 넣은 후 카본을 함유하지 않은 프로린 식각가스와 산소가스와 질소가스를 혼합한 식각가스를 주입하여 상기 금속층과 상기 확산방지막을 식각한 후에 상기 반도체층을 소정깊이까지 식각하는 단계, 상기와 같이 소정깊이 식각된 반도체층이 있는 상기 반도체기판을 제 2 챔버에 넣은 후 클로린 가스와 산소가스를 혼합한 식각가스를 주입하여 상기 반도체층을 과도식각하는 단계를 포함하는 것을 특징으로 한다.The multilayer film etching method of the semiconductor device of the present invention for achieving the above object is a semiconductor substrate in which a first insulating film, a semiconductor layer, a diffusion barrier film and a metal layer are sequentially deposited, the first semiconductor substrate having a multilayer film as described above Injecting the carbon-containing proline etching gas, the etching gas containing oxygen gas and nitrogen gas, and etching the metal layer and the diffusion barrier layer, and then etching the semiconductor layer to a predetermined depth. And inserting the semiconductor substrate having the semiconductor layer etched into a predetermined depth into the second chamber, and injecting an etching gas mixed with chlorine gas and oxygen gas to overetch the semiconductor layer.

첨부 도면을 참조하여 본 발명 반도체 소자의 다층막 식각방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of etching a multilayer film of a semiconductor device of the present invention will be described.

도 2a 내지 2c는 본 발명 반도체 소자의 다층막 식각방법을 나타낸 공정단면도이고, 도 3은 플로린 식각가스에 산소가스만 넣어 반도체 소자의 다층막을 식각하였을 때의 사진이며, 도 4는 본 발명에 따라 반도체 소자의 다층막을 식각하였을 때의 사진이다.2A to 2C are cross-sectional views illustrating a method of etching a multilayer film of a semiconductor device according to the present invention, and FIG. 3 is a photograph when the multilayer film of a semiconductor device is etched by adding only oxygen gas to a fluorine etching gas, and FIG. It is a photograph when the multilayer film of an element is etched.

반도체 소자의 다층막 식각방법은 도 2a에 도시한 바와 같이 반도체 기판(21)에 실리콘산화막(22)과 폴리실리콘층(23)을 차례로 적층한다. 그리고 폴리실리콘층(23)상에 티타늄 나이트라이드(TiN)나 WSiN와 같은 물질을 증착하여 확산방지막(24)을 형성한다. 이후에 확산방지막(24)상에 텅스텐이나 몰리부덴(Mo)을 증착하여 금속층(25)을 형성한다. 여기에서 상기 확산방지막(24)과 금속층(25)을 증착하는 대신에 직접 금속실리사이드를 증착하여도 된다. 그리고 금속층(25)상에 질화막이나 산화막을 증착하여 하드마스크층(26)을 형성한다. 이후에 하드마스크층(26)상에 감광막(27)을 도포한 후 노광 및 현상공정으로 소정부분을 선택적으로 패터닝한다.In the multilayer film etching method of the semiconductor device, as illustrated in FIG. 2A, the silicon oxide film 22 and the polysilicon layer 23 are sequentially stacked on the semiconductor substrate 21. The diffusion barrier layer 24 is formed by depositing a material such as titanium nitride (TiN) or WSiN on the polysilicon layer 23. Thereafter, tungsten or molybdenum (Mo) is deposited on the diffusion barrier 24 to form the metal layer 25. Instead of depositing the diffusion barrier 24 and the metal layer 25, metal silicide may be deposited directly. The hard mask layer 26 is formed by depositing a nitride film or an oxide film on the metal layer 25. Thereafter, the photoresist 27 is coated on the hard mask layer 26, and then predetermined portions are selectively patterned by an exposure and development process.

도 2b에 도시한 바와 같이 패터닝된 감광막(27)을 마스크로 이용하여 하드마스크층(26)을 상기 금속층(25)이 드러나도록 이방성 식각한 후에 감광막(27)을 제거한다.As shown in FIG. 2B, the photoresist layer 27 is removed after anisotropic etching of the hard mask layer 26 to expose the metal layer 25 using the patterned photoresist layer 27 as a mask.

도 2c에 도시한 바와 같이 식각된 하드마스크층(26)을 마스크로 이용하여 먼저 플로린 식각가스 챔버에 폴리머 생성의 원인이 되는 카본(carbon)을 함유하지 않은 플로린가스와, SF6와, NF3+O2+N2혼합가스를 주입하여 금속층(25)과 확산방지막(24)과 폴리실리콘층(23)을 이방성 식각한다. 이때 폴리실리콘층(23)은 소정깊이 까지만 식각되도록 한다. 이때 산소가스(O2)는 총유량의 10∼30% 범위가 되도록 주입하고, 질소가스(N2)는 총유량의 40∼80% 범위가 되도록 주입한다. 그리고 이때 반도체 기판(21)의 온도는 -20℃∼60℃의 범위가 되도록 진행하며, 소오스파워는 300∼1000Watt 범위가 되도록 하고, 바이어스 파워는 30∼200Watt 범위가 되도록 하며 챔버의 압력은 2∼10m Torr가 되도록 한다. 이때 플로린 식각가스 챔버는 헬리콘(Helicon)이나 헬리칼(Helical)이나 티씨피(Transformer Coupled Plasma:TCP)나 이씨알(Electron Cyclotron Resonance:ECR)과 같은 고밀도 식각장비를 사용한다.Using the etched hard mask layer 26 as a mask as shown in FIG. 2C, first, a florin gas containing no carbon, which causes polymer formation, in the florin etching gas chamber, SF 6 , and NF 3 is used. + O 2 + N 2 mixed gas is injected to anisotropically etch the metal layer 25, the diffusion barrier 24, and the polysilicon layer 23. At this time, the polysilicon layer 23 is etched only up to a predetermined depth. At this time, oxygen gas (O 2 ) is injected to be in the range of 10 to 30% of the total flow rate, nitrogen gas (N 2 ) is injected to be in the range of 40 to 80% of the total flow rate. At this time, the temperature of the semiconductor substrate 21 proceeds to be in the range of -20 ° C to 60 ° C, the source power is in the range of 300 to 1000 Watts, the bias power is in the range of 30 to 200 Watts, and the chamber pressure is 2 to 10m Torr At this time, the Florin etching gas chamber uses high density etching equipment such as Helicon, Helical, Transformer Coupled Plasma (TCP), or Electron Cyclotron Resonance (ECR).

다음에 클로린 식각가스 챔버에서 Cl2+O2가스를 10:1에서 2.5:1의 혼합비를 갖도록 주입하여 식각되지 않은 폴리실리콘층(23)을 오버식각한다.Next, in the chlorine etching gas chamber, Cl 2 + O 2 gas is injected to have a mixing ratio of 10: 1 to 2.5: 1 to overetch the unetched polysilicon layer 23.

여기서 플로린 식각가스 챔버에 주입되는 산소가스(O2)는 폴리실리콘층(23)의 측면에 쉽게 보호막을 형성하여 폴리실리콘층(23)의 측면이 식각되는 것을 방지하는 역할을 하고, N2가스는 금속층(25)의 측벽에 보호막을 형성하여 금속층(25)의 측면이 과도식각되는 것을 방지하는 역할을 한다.Here, the oxygen gas (O 2 ) injected into the florin etching gas chamber serves to prevent the side surface of the polysilicon layer 23 from being etched by easily forming a protective film on the side of the polysilicon layer 23, and the N 2 gas. The protective layer is formed on the sidewall of the metal layer 25 to prevent the side surface of the metal layer 25 from being excessively etched.

그리고 클로린 식각가스 챔버에서 Cl2+O2와 같은 식각가스를 이용하여 폴리실리콘층(23)을 식각할 때는 하부의 실리콘산화막(22)과 200:1이상의 선택비를 갖고 수직하게 폴리실리콘층(23)을 식각할 수 있다.In the chlorine etching gas chamber, when the polysilicon layer 23 is etched by using an etching gas such as Cl 2 + O 2 , the polysilicon layer perpendicularly has a selectivity of 200: 1 or more with the lower silicon oxide layer 22. 23) can be etched.

플로린 식각가스 챔버에 플로린가스와 산소가스만을 주입하여 다층막을 식각하였을 경우에는 도 3에 도시한 바와 같이 폴리실리콘층(23)까지 수직하게 식각되지 못하고 폴리실리콘층(23)이 언더에치되는 현상이 나타난다.When the multilayer film is etched by injecting only florin gas and oxygen gas into the fluorine etching gas chamber, as shown in FIG. 3, the polysilicon layer 23 is underetched without being vertically etched up to the polysilicon layer 23. Appears.

그리고 본 발명과 같이 플로린 식각가스 챔버와 클로린 식각가스 챔버를 통하여 다층막을 식각할 경우에 도 4에 도시한 바와 같이 폴리실리콘층(23)까지 수직한 프로파일을 갖고 식각됨을 알 수 있다.In addition, when the multilayer film is etched through the fluorine etching gas chamber and the chlorine etching gas chamber as in the present invention, as shown in FIG. 4, the polysilicon layer 23 has a vertical profile to be etched.

상기와 같은 본 발명 반도체 소자의 다층막 식각방법은 다음과 같은 효과가 있다.The multilayer film etching method of the semiconductor device of the present invention as described above has the following effects.

첫째, 식각장비를 오염시키는 가장 큰 원인인 폴리머 생성을 주도하는 카본을 포함한 플로린 가스를 사용하지 않으므로 식각 챔버의 오염을 줄이고, 공정재현성 및 세정 주기를 개선시킬 수 있다.First, it is possible to reduce the contamination of the etching chamber and improve the process reproducibility and the cleaning cycle since it does not use the florin gas containing carbon which leads the polymer generation, which is the biggest cause of contamination of the etching equipment.

둘째, 플로린 가스와 클로린 식각가스가 혼용되어 식각되지 않으므로 혼용가스에 의한 챔버의 오염없이 공정을 진행할 수있다.Second, since the florin gas and the chlorine etching gas are not mixed and etched, the process can be performed without contamination of the chamber by the mixed gas.

셋째, 브로마인 가스를 전혀 사용하지 않으므로 식각잔여물이 발생하는 것을 방지할 수 있다.Third, since no bromine gas is used, it is possible to prevent the etching residues from occurring.

Claims (10)

제 1 절연막과 반도체층과 확산방지막과 금속층이 차례로 증착되어 있는 반도체 기판에 있어서,In a semiconductor substrate on which a first insulating film, a semiconductor layer, a diffusion barrier film, and a metal layer are sequentially deposited, 상기와 같이 다층막이 형성된 상기 반도체기판을 제 1 챔버에 넣은 후 카본을 함유하지 않은 프로린 식각가스와 산소가스와 질소가스를 혼합한 식각가스를 주입하여 상기 금속층과 상기 확산방지막을 식각한 후에 상기 반도체층을 소정깊이까지 식각하는 단계,After the semiconductor substrate having the multilayered film formed as described above is inserted into the first chamber, an etching gas containing a carbon-containing proline etching gas and an oxygen gas and a nitrogen gas is injected to etch the metal layer and the diffusion barrier layer, and then the semiconductor layer is etched. Etching the layer to a predetermined depth, 상기와 같이 소정깊이 식각된 반도체층이 있는 상기 반도체기판을 제 2 챔버에 넣은 후 클로린 가스와 산소가스를 혼합한 식각가스를 주입하여 상기 반도체층을 과도식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.And inserting the semiconductor substrate having the semiconductor layer etched into a predetermined depth as described above into a second chamber, and injecting an etching gas containing chlorine gas and oxygen gas to overetch the semiconductor layer. Multi-layer film etching method of the device. 제 1 항에 있어서, 상기 금속층은 텅스텐이나 몰리부덴(Mo)이나 금속실리사이드중 하나를 포함하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the metal layer comprises one of tungsten, molybdenum (Mo), and a metal silicide. 제 1 항에 있어서, 상기 제 1 챔버에 주입된 산소의 유량은 총유량의 10∼30% 범위가 되는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the flow rate of the oxygen injected into the first chamber is in a range of 10 to 30% of the total flow rate. 제 1 항에 있어서, 상기 제 1 챔버에 주입된 질소의 유량은 총유량의 40∼80% 범위가 되는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the flow rate of nitrogen injected into the first chamber is in the range of 40 to 80% of the total flow rate. 제 1 항에 있어서, 상기 제 1 챔버의 반도체 기판의 온도를 -20℃∼60℃범위가 되도록 하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the temperature of the semiconductor substrate in the first chamber is set in the range of -20 ° C to 60 ° C. 제 1 항에 있어서, 상기 제 1 챔버에서의 식각을 위한 소오스파워는 300∼1000Watt 범위에서 사용하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the source power for etching in the first chamber is used in the range of 300 to 1000 Watts. 제 1 항에 있어서, 상기 제 1 챔버와 제 2 챔버의 위한 바이어스 파워는 30∼200Watt 범위에서 사용하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the bias power for the first chamber and the second chamber is in the range of 30 to 200 Watts. 제 1 항에 있어서, 상기 제 1 챔버에서의 식각을 위한 압력은 2∼10m Torr 범위가 되도록 하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the pressure for etching in the first chamber is in a range of 2 to 10 m Torr. 제 1 항에 있어서, 상기 제 1 챔버는 헬리콘(Helicon)이나 헬리칼(Helical)이나 티씨피(Transformer Coupled Plasma:TCP)나 이씨알(Electron Cyclotron Resonance:ECR)과 같은 고밀도 식각장비를 사용하는 것을 특징으로 하는 반도체 소자의 다층막 식각방법.The method of claim 1, wherein the first chamber is a high density etching device such as Helicon (Helicon), Helical (Transformer Coupled Plasma: TCP), Electron Cyclotron Resonance (ECR) A multilayer film etching method of a semiconductor device, characterized in that. 제 1 항에 있어서, 제 2 챔버에서 두 번째 식각을 위한 Cl2:O2의 혼합비는 10:1에서 2.5:1의 범위가 되도록 하는 것을 특징으로 하는 다층막 식각방법.The method of claim 1, wherein the mixing ratio of Cl 2 : O 2 for the second etching in the second chamber is in a range of 10: 1 to 2.5: 1.
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