KR100548542B1 - Method of forming for semiconductor device - Google Patents
Method of forming for semiconductor device Download PDFInfo
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- KR100548542B1 KR100548542B1 KR1019990048672A KR19990048672A KR100548542B1 KR 100548542 B1 KR100548542 B1 KR 100548542B1 KR 1019990048672 A KR1019990048672 A KR 1019990048672A KR 19990048672 A KR19990048672 A KR 19990048672A KR 100548542 B1 KR100548542 B1 KR 100548542B1
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- titanium nitride
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 31
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000010937 tungsten Substances 0.000 claims abstract description 26
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 abstract description 10
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 LDD 산화공정시 배리어 금속막인 티타늄 질화막의 부피팽창을 방지하여 게이트 저항을 감소시킴과 동시에 게이트 라인 사이의 브리지를 방지할 수 있는 반도체 소자의 게이트 형성방법을 제공한다. The present invention provides a method for forming a gate of a semiconductor device that can prevent the volume expansion of the titanium nitride film, which is a barrier metal film during the LDD oxidation process, to reduce gate resistance and to prevent bridges between gate lines.
본 발명에 따라, 반도체 기판 상에 게이트 절연막, 배리어 금속막, 텅스텐막 및 하드 마스크층을 순차적으로 형성하고, 하드 마스크층 및 텅스텐막을 상기 배리어 금속막이 노출되도록 게이트 형태로 식각한다. 그런 다음, 노출된 배리어 금속막의 그의 측부가 언더컷 되도록 식각하여 상기 배리어 금속막과 텅스텐막으로 이루어진 게이트를 형성하고, 기판을 산화하여 상기 배리어 금속막의 측벽에 산화막을 형성한다. 본 실시예에서, 배리어 금속막은 티타늄 질화막이고, 티타늄 질화막의 식각은 Cl2를 함유한 개스를 이용하여 진행한다. 바람직하게, 소오스 파워와 바이어스 파워를 이용하여 Cl2 개스에 N2, O2 및 HBr과 같은 첨가개스를 첨가하여 진행한다. 여기서, 소오스 파워 : 바이어스 파워의 비율은 3 : 1 이상이고, Cl2 개스 : 첨가개스의 비율은 5 : 1 이상이다.According to the present invention, a gate insulating film, a barrier metal film, a tungsten film, and a hard mask layer are sequentially formed on a semiconductor substrate, and the hard mask layer and the tungsten film are etched in a gate form to expose the barrier metal film. Then, the side of the exposed barrier metal film is etched to undercut to form a gate made of the barrier metal film and the tungsten film, and the substrate is oxidized to form an oxide film on the sidewall of the barrier metal film. In this embodiment, the barrier metal film is a titanium nitride film, and the etching of the titanium nitride film proceeds using a gas containing Cl 2 . Preferably, proceed with addition of additional gases such as N 2 , O 2 and HBr to Cl 2 gas using source power and bias power. Here, the ratio of source power: bias power is 3: 1 or more, and the ratio of Cl 2 gas: added gas is 5:: 1 or more.
Description
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 : 반도체 기판 11 : 게이트 절연막10
12 : 티타늄 질화막 13 : 텅스텐막12
14 : 하드 마스크층 15 : 포토레지스트 패턴14
16 : 산화막16: oxide film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 텅스텐막을 이용한 반도체 소자의 게이트 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device using a tungsten film.
반도체 소자의 저전력화 및 고속화를 위하여, 게이트 물질로서 저저항 물질이 요구되고 있다. 이러한 저저항 물질로서 티타늄 또는 코발트 실리사이드와 같은 실리사이드 물질 및 텅스텐막이 사용된다. 이중 텅스텐막은 8 내지 10μΩ·㎝의 낮은 비저항을 갖는 장점이 있다.In order to reduce the power consumption and speed of the semiconductor device, a low resistance material is required as the gate material. As such a low resistance material, a silicide material such as titanium or cobalt silicide and a tungsten film are used. The double tungsten film has an advantage of having a low specific resistance of 8 to 10 mu Ω · cm.
한편, 상기한 텅스텐막을 이용하는 경우에는 확산방지를 위하여 게이트 절연막과 텅스텐막 사이에 배리어 금속막으로서 티타늄 질화막(TiN)과 같은 금속 질화막을 개재하여 형성한다. On the other hand, in the case of using the above-mentioned tungsten film, a barrier metal film is formed between the gate insulating film and the tungsten film via a metal nitride film such as titanium nitride film (TiN) to prevent diffusion.
그러나, 상기한 티타늄 질화막을 개재하여 텅스텐막으로 게이트를 형성한 후 LDD 산화공정을 진행하는 경우, 티타늄 질화막의 높은 산화속도로 인하여 부피팽창이 야기되어 게이트 저항이 증가될 뿐만 아니라 게이트 라인 사이에서 브리지가 유발됨으로써, 소자의 신뢰성 및 수율이 현저하게 저하된다. However, when the LDD oxidation process is performed after the gate is formed of a tungsten film through the titanium nitride film, the volume resistance is caused by the high oxidation rate of the titanium nitride film, thereby increasing the gate resistance and bridging between the gate lines. Is caused to significantly lower the reliability and yield of the device.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, LDD 산화공정시 배리어 금속막인 티타늄 질화막의 부피팽창을 방지하여 게이트 저항을 감소시킴과 동시에 게이트 라인 사이의 브리지를 방지할 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다. Accordingly, the present invention is to solve the above-mentioned problems, the semiconductor which can prevent the volume expansion of the titanium nitride film, which is a barrier metal film during the LDD oxidation process to reduce the gate resistance and at the same time prevent the bridge between the gate lines It is an object of the present invention to provide a method for forming a gate of a device.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 게이트 형성방법은 반도체 기판 상에 게이트 절연막, 티타늄 질화막, 텅스텐막 및 하드 마스크층을 순차적으로 형성하는 단계; 상기 하드 마스크층 및 텅스텐막을 상기 티타늄 질화막이 노출되도록 게이트 형태로 식각하는 단계; 상기 노출된 티타늄 질화막을 Cl2를 함유한 개스를 이용한 등방성 건식방법으로 상기 텅스텐막에 대해 언더컷 되도록 식각하여 상기 티타늄 질화막과 텅스텐막으로 이루어진 게이트를 형성하는 단계; 및, 상기 텅스텐막에 대해 언더컷된 상기 티타늄 질화막의 측면을 산화하여 산화막을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of forming a gate of a semiconductor device, the method including: sequentially forming a gate insulating film, a titanium nitride film, a tungsten film, and a hard mask layer on a semiconductor substrate; Etching the hard mask layer and the tungsten layer in a gate form to expose the titanium nitride layer; Etching the exposed titanium nitride film to undercut the tungsten film by an isotropic dry method using a gas containing Cl 2 to form a gate including the titanium nitride film and the tungsten film; And oxidizing a side surface of the titanium nitride film undercut with respect to the tungsten film to form an oxide film.
본 실시예에서, 티타늄 질화막의 식각은 소오스 파워와 바이어스 파워를 이용하여 Cl2 개스에 N2, O2 및 HBr과 같은 첨가개스를 더 첨가하여 진행한다. 여기서, 소오스 파워 : 바이어스 파워의 비율은 3 : 1 이상이고, Cl2 개스 : 첨가개스의 비율은 5 : 1 이상이다.In this embodiment, the titanium nitride film is etched by adding additional gases such as N 2 , O 2 and HBr to the Cl 2 gas by using the source power and the bias power. Here, the ratio of source power: bias power is 3: 1 or more, and the ratio of Cl 2 gas: added gas is 5:: 1 or more.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다. 1A to 1D are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(10) 상에 게이트 절연막(11), 배리어 금속막으로서의 티타늄 질화막(12), 텅스텐막(13) 및 하드 마스크층(14)을 순차적으로 형성한다. 여기서, 게이트 절연막(11)은 SiO2막 또는 Al2O3막, Ta2O
5막 및 BST막과 같은 고유전율을 갖는 절연막으로 형성한다. 또한, 텅스텐막은 500Å 이상, 바람직하게 1,000 내지 1,500Å의 두께로 형성하고, 티타늄 질화막(12)은 500Å 이하, 바람직하게 100 내지 300Å의 두께로 형성한다. 그런 다음, 절연막(14) 상에 포토리소그라피로 게이트 형태의 포토레지스트 패턴(15)을 형성한다. Referring to FIG. 1A, a gate
도 1b를 참조하면, 포토레지스트 패턴(15)을 식각 마스크로하여, 하드 마스크층(14) 및 텅스텐막(13)을 티타늄 질화막(12)의 표면이 노출되도록 식각한다. 그런 다음, 도 1c에 도시된 바와 같이, Cl2를 함유한 개스를 이용한 식각으로 티타늄 질화막(12)을 그의 측부가 언더컷(undercut)되도록 식각하여 티타늄 질화막(12)과 텅스텐막(13)으로 이루어진 게이트를 형성한다. 바람직하게, 소오스 파워와 바이어스 파워를 이용하여 Cl2 개스에 N2, O2 및 HBr과 같은 개스를 첨가하여 진행한다. 이때, 소오스 파워 : 바이어스 파워의 비율은 3 : 1 이상이고, Cl2 개스 : 첨가개스의 비율은 5 : 1 이상이다.Referring to FIG. 1B, the
도 1d를 참조하면, 공지된 방법으로 포토레지스트 패턴(15)을 제거하고, LDD 산화공정을 진행하여 티타늄 질화막(12)의 측벽에 산화막(16)을 형성한다. 이때, 티타늄 질화막(12)에 발생된 언더컷에 의해, 티타늄 질화막(12)의 부피팽창이 방지된다.Referring to FIG. 1D, the
상기한 본 발명에 의하면, 티타늄 질화막과 텅스텐막의 적층막으로 이루어진 게이트의 형성시, 티타늄 질화막에 언더컷을 형성함으로써, LDD 산화공정시 높은 산화속도에 의해 발생되는 티타늄 질화막의 부피팽창이 효과적으로 방지된다. 이에 따라, 게이트 저항이 감소됨과 동시에 게이트 라인 사이의 브리지 발생이 방지됨으로써, 결국 소자의 신뢰성 및 수율이 향상된다. According to the present invention described above, by forming an undercut in the titanium nitride film during the formation of the gate formed of the laminated film of the titanium nitride film and the tungsten film, the volume expansion of the titanium nitride film caused by the high oxidation rate during the LDD oxidation process is effectively prevented. As a result, the gate resistance is reduced and the occurrence of bridges between the gate lines is prevented, thereby improving the reliability and yield of the device.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.
In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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| KR100583098B1 (en) * | 1999-12-30 | 2006-05-24 | 주식회사 하이닉스반도체 | Method for forming gate in semiconductor device |
| KR100979232B1 (en) * | 2003-07-15 | 2010-08-31 | 매그나칩 반도체 유한회사 | The method for forming capacitor in semiconductor device |
| KR20050011092A (en) * | 2003-07-21 | 2005-01-29 | 매그나칩 반도체 유한회사 | Method for manufacturing t-shaped transistor gate |
| KR100580050B1 (en) * | 2004-12-29 | 2006-05-12 | 동부일렉트로닉스 주식회사 | Method for fabricating the poly silicon gate of semiconductor device |
| KR100654360B1 (en) | 2005-10-27 | 2006-12-08 | 삼성전자주식회사 | Semiconductor integrated circuit device and fabrication method for the same |
| KR101900042B1 (en) | 2012-05-10 | 2018-09-18 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100207472B1 (en) * | 1996-06-07 | 1999-07-15 | 윤종용 | Semiconductor device for gate electrode having & manufacturing method of the same |
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1999
- 1999-11-04 KR KR1019990048672A patent/KR100548542B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100207472B1 (en) * | 1996-06-07 | 1999-07-15 | 윤종용 | Semiconductor device for gate electrode having & manufacturing method of the same |
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| KR20010045401A (en) | 2001-06-05 |
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