KR100393974B1 - Forming Method for Dual Damascene - Google Patents
Forming Method for Dual Damascene Download PDFInfo
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- KR100393974B1 KR100393974B1 KR10-2001-0001814A KR20010001814A KR100393974B1 KR 100393974 B1 KR100393974 B1 KR 100393974B1 KR 20010001814 A KR20010001814 A KR 20010001814A KR 100393974 B1 KR100393974 B1 KR 100393974B1
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- forming
- via hole
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000009977 dual effect Effects 0.000 title abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims description 21
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 239000003989 dielectric material Substances 0.000 description 27
- 239000011368 organic material Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910010272 inorganic material Inorganic materials 0.000 description 4
- 239000011147 inorganic material Substances 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- XSNQEMWVLMRPFR-UHFFFAOYSA-N silver nitride Chemical compound [N-3].[Ag+].[Ag+].[Ag+] XSNQEMWVLMRPFR-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 듀얼 다마신 형성 방법을 제공하기 위한 것으로, 배선층을 형성하는 단계; 상기 배선층 상에 제1절연막을 형성하는 단계; 상기 제1절연막 상에 제2절연막을 형성하는 단계; 상기 제2절연막 상에 상기 배선층의 일부가 노출되도록 상기 제1 및 제2절연막을 식각하여 비아 홀을 형성하는 단계; 상기 제2절연막이 노출되도록 상기 비아 홀에 소정 높이로 제3절연막을 형성하는 단계; 상기 제3절연막을 포함한 상기 제2절연막 상부에 제4절연막을 형성하는 단계; 상기 제3절연막의 상부를 포함한 상기 제2절연막의 일부가 노출되도록 상기 제4절연막을 식각하여 트랜치를 형성하는 단계; 상기 제3절연막을 제거하고, 상기 비아 홀 및 트랜치에 상기 배선층과 콘택되도록 금속을 형성하는 단계를 포함하여 이루어지며, 상기 형성된 비아 홀에 유기 절연막으로 제3절연막을 형성하고 나이트라이드막 등의 하드마스크를 이용하지 않고 트랜치를 형성함으로써 트랜치의 스트리에이션을 방지할 수 있고, 비아 홀의 CD(Critical Demension) 조절이 가능하다.The present invention is to provide a dual damascene formation method, forming a wiring layer; Forming a first insulating film on the wiring layer; Forming a second insulating film on the first insulating film; Forming a via hole by etching the first and second insulating layers so that a portion of the wiring layer is exposed on the second insulating layer; Forming a third insulating film at a predetermined height in the via hole to expose the second insulating film; Forming a fourth insulating layer on the second insulating layer including the third insulating layer; Forming a trench by etching the fourth insulating layer to expose a portion of the second insulating layer including an upper portion of the third insulating layer; Removing the third insulating layer and forming a metal to contact the wiring layer in the via hole and the trench; forming a third insulating layer using an organic insulating layer in the formed via hole, and forming a hard By forming the trench without using a mask, it is possible to prevent the trench saturation and to control the CD (Critical Demension) of the via hole.
Description
본 발명은 듀얼 다마신(dual damascene) 형성 방법에 관한 것으로, 특히, 비아 홀을 먼저 형성하여 비아 홀 및 트랜치의 스트리에이션 등의 손상이 방지되고 형상이 보존된 듀얼 다마신 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual damascene formation method, and more particularly, to a method for forming a dual damascene in which via holes are first formed to prevent damage of via holes and trenches, and the shape is preserved.
고집적화 되어 가는 소자에 있어서, 메탈 라인 보다 이점이 많은 구리 라인을 사용하는데, 구리 라인은 식각에 의한 형성이 불리하므로 듀얼 다마신 공정을 이용하여 구리를 증착한 다음 증착한 구리를 CMP공정을 적용하여 트랜치 부위에 구리 라인을 형성할 수 있다.Highly integrated devices use copper lines that have more advantages than metal lines. Since copper lines are disadvantageous due to etching, copper is deposited using the dual damascene process and then the deposited copper is applied by CMP process. Copper lines may be formed in the trench region.
도1a 및 도1f는 종래 기술에 따른 듀얼 다마신 공정단면도이다.1A and 1F are cross-sectional views of a dual damascene process according to the prior art.
도1a에 도시한 바와 같이, 배선층(1) 위에 무기물로 제1 저유전물질(2)을 형성하고, 상기 제1 저유전물질(2) 위에 나이트라이드막(3)을 형성한 후, 포토레지스트(4)를 이용하여 도1b에 도시한 바와 같이, 상기 나이트라이트막(3)에 홀 식각을 형성한다.As shown in FIG. 1A, a first low dielectric material 2 is formed of an inorganic material on the wiring layer 1, and a nitride film 3 is formed on the first low dielectric material 2. Using (4), as shown in FIG. 1B, hole etching is formed in the night light film 3.
이어 도1c에 도시한 바와 같이, 무기물로 제2 저유전물질(5)을 증착하고, 상기 제2 저유전물질(5) 위에 하드마스크로 나이트라이드막(6)을 증착한다.Subsequently, as illustrated in FIG. 1C, a second low dielectric material 5 is deposited using an inorganic material, and a nitride film 6 is deposited on the second low dielectric material 5 using a hard mask.
그 후에 도1d에 도시한 바와 같이 포토레지스트로 형성된 트랜치 마스크(7)를 이용하여 도1e에 도시한 바와 같이, 제2 저유전물질(5)까지 식각을 진행하여 트랜치(A)를 형성한다.Thereafter, as illustrated in FIG. 1D, the trench A is formed by etching to the second low dielectric material 5 using the trench mask 7 formed of photoresist as shown in FIG. 1D.
이때 트랜치 마스크(7)는 거의 제거가 되고, 나이트라이드막(6) 및 나이트라이드막(3)을 마스크로 이용하여 도1f에 도시한 바와 같이, 제1 저유전물질(2)을 식각하여 비아 홀(B)을 형성한다.At this time, the trench mask 7 is almost removed, and the first low dielectric material 2 is etched by using the nitride film 6 and the nitride film 3 as a mask as shown in FIG. 1F. The hole B is formed.
이때 비아 홀(B) 형성을 위한 식각 진행시 나이트라이드막(3) 손실을 감안하여 나이트라이드막(3)을 두껍게 증착해야 한다.In this case, the nitride film 3 should be thickly deposited in consideration of the loss of the nitride film 3 during the etching process for forming the via hole B.
그리고, 나이트라이드막(3)이 부식(erosion)될 경우 비아 홀(B)의 CD(Critical Demension)를 정확히 제어할 수 없으며, 비아 홀(B)의 하부 패턴이 평탄하지 않아 와인 글레스처럼 하부 패턴이 둥글게 형성 될 수가 있다.In addition, when the nitride layer 3 is eroded, the CD (Critical Demension) of the via hole (B) cannot be accurately controlled, and the lower pattern of the via hole (B) is not flat, so that the lower pattern is like a wine glass. This can be rounded.
그리고 나이트라이드막(3, 5) 대 저유전물질(2, 4)의 식각 선택비가 높게 유지되어야만 나이트라이드막(3)을 베리어로 사용할 수가 있다.In addition, the nitride film 3 may be used as a barrier only when the etching selectivity of the nitride films 3 and 5 to the low dielectric materials 2 and 4 is maintained high.
또한 트랜치(A) 및 비아 홀(B) 형성을 위한 식각 진행시에 나이트나이드막(5, 3)의 침식으로 트랜치(A) 부위 및 비아 홀(B)에 줄무늬(striation)가 발생할 수 있다.Further, when etching is performed to form the trench A and the via hole B, streaks may occur in the trench A portion and the via hole B due to the erosion of the nitride layers 5 and 3.
따라서 본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로서,금속 배선층 위에 비아 홀을 먼저 형성하고 상기 비아 홀에 유기물로 절연막을 형성한 후, 트랜치 형성을 위한 절연막을 상부에 형성하여 트랜치를 형성함으로써 비아 홀의 CD(Critical Demension)의 제어가 가능하고, 미리 형성된 비아 홀의 형상을 보존하며 비아 홀 및 트랜치의 스트리에이션등의 손상을 방지하는 듀얼 다마신 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention has been made to solve the above problems, first forming a via hole on the metal wiring layer and then forming an insulating film with an organic material in the via hole, and then forming an trench for forming a trench on top The purpose of the present invention is to provide a dual damascene formation method capable of controlling the CD (Critical Demension) of the via hole, preserving the shape of the pre-formed via hole, and preventing damage to via holes and trench saturation.
즉, 비아 홀을 미리 형성시키고 비아 홀을 유기물로 채워 비아 홀을 보호하고 있고, 하드 마스크를 이용하지 않기 때문에 종래의 나이트라이드 등의 하드 마스크를 이용하여 비아 홀 및 트랜치 형성을 위한 식각 진행시 발생하는 상기 하드 마스크의 부식을 방지하여 트랜치 및 비아 홀에 스트리에이션 등의 손상을 방지하는데 그 목적이 있다.That is, the via hole is formed in advance and the via hole is filled with an organic material to protect the via hole, and since the hard mask is not used, it is generated during the etching process for forming the via hole and the trench using a conventional hard mask such as nitride. The purpose of the present invention is to prevent corrosion of the hard mask to prevent damage to the trenches and via holes.
도1a 내지 도1f는 종래 기술에 따른 듀얼 다마신 공정단면도.1A-1F are cross-sectional views of a dual damascene process in accordance with the prior art.
도2a 내지 도2k는 본 발명에 다른 듀얼 다마신 공정단면도.Figures 2a to 2k is a cross-sectional view of a dual damascene process according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 배선층 12 : 제1 저유전물질11 wiring layer 12 first low dielectric material
13 : 나이트라이드막 14 : 포토레지스트13: nitride film 14: photoresist
15 : 저유전물질 16 : 제2 저유전물질15: low dielectric material 16: the second low dielectric material
17 : 포토레지스트 18 : 금속17 photoresist 18 metal
상기와 같은 목적을 달성하기 위한 본 발명에 따른 듀얼 다마신 형성 방법의 특징은 배선층을 형성하는 단계; 상기 배선층 상에 제1절연막을 형성하는 단계; 상기 제1절연막 상에 상기 제 1 절연막과 식각선택비가 다른 제2절연막을 형성하는 단계; 상기 제2절연막 상에 상기 배선층의 일부가 노출되도록 상기 제1 및 제2절연막을 식각하여 비아 홀을 형성하는 단계; 상기 제 2절연막이 노출되도록 상기 비아 홀에 소정 높이로 유기절연막을 형성하는 단계; 상기 유기절연막을 포함한 상기 제2절연막 상부에 제3절연막을 형성하는 단계; 상기 유기절연막의 상부를 포함한 상기 제2절연막의 일부가 노출되도록 상기 제3절연막을 식각하여 상기 비아홀보다 넓은 폭을 갖는 트랜치를 형성하는 단계; 상기 유기절연막을 제거하고, 상기 비아 홀 및 트랜치에 상기 배선층과 콘택되도록 금속을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.상기 제1 및 제3절연막은 무기 절연막으로 형성되고, 상기 제2절연막은 나이트라이드막을 포함하고, 상기 유기절연막은 카본 폴리머(Carbon Polymer)계인 것을 특징으로 한다.상기 유기절연막의 제거는 02계 가스 분위기에서 이루어진다.Features of the dual damascene formation method according to the present invention for achieving the above object comprises the steps of forming a wiring layer; Forming a first insulating film on the wiring layer; Forming a second insulating film on the first insulating film, the second insulating film having a different etching selectivity from the first insulating film; Forming a via hole by etching the first and second insulating layers so that a portion of the wiring layer is exposed on the second insulating layer; Forming an organic insulating film at a predetermined height in the via hole to expose the second insulating film; Forming a third insulating film on the second insulating film including the organic insulating film; Etching the third insulating layer to expose a portion of the second insulating layer including an upper portion of the organic insulating layer to form a trench having a width wider than the via hole; And removing the organic insulating layer and forming a metal in contact with the wiring layer in the via hole and the trench. The first and third insulating layers are formed of an inorganic insulating layer and the second insulating layer. Silver nitride film, and the organic insulating film is characterized in that the carbon polymer (Carbon Polymer). Removal of the organic insulating film is carried out in a 0 2 type gas atmosphere.
본 발명의 특징에 따른 작용은 비아 홀 및 트랜치를 형성하는 듀얼 다마신 형성 공정에 있어서, 금속 배선층 위에 비아 홀을 형성하기 위한 제1절연막을 형성하고, 상기 제1절연막 상에 상기 제1절연막과 높은 식각 선택비를 갖는 제2절연막을 형성하여 비아 홀을 형성하고, 상기 비아 홀에 유기물로 제3절연막을 형성한 후, 트랜치 형성을 위한 제4절연막을 상부에 형성하여 트랜치를 형성하기 때문에 트랜치 식각을 진행을 할 때 상기 유기물에 의해 비아 홀의 CD(Critical Demension)가 조절이 가능하고, 나이트라이트막 등의 하드마스크를 이용하지 않고 트랜치를 형성하기 때문에 트랜치 형성을 위한 식각시 스트리에이션이 발생하지 않는다.According to an aspect of the present invention, in the dual damascene forming process of forming a via hole and a trench, a first insulating layer for forming a via hole is formed on a metal wiring layer, and the first insulating layer is formed on the first insulating layer. A trench is formed by forming a second insulating film having a high etching selectivity, forming a via hole, forming a third insulating film with an organic material in the via hole, and forming a trench by forming a fourth insulating film on the top to form a trench. When etching, the CD (Critical Demension) of the via hole can be controlled by the organic material, and since the trench is formed without using a hard mask such as a night light layer, the striation does not occur during the trench formation. Do not.
본 발명의 다른 목적, 특성 및 잇점들은 첨부한 도면을 참조한 실시예들의상세한 설명을 통해 명백해질 것이다.Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.
본 발명에 따른 듀얼 다마신 형성 방법의 바람직한 실시예에 대하여 첨부한 도면을 참조하여 설명하면 다음과 같다.A preferred embodiment of the dual damascene formation method according to the present invention will be described with reference to the accompanying drawings.
먼저, 도2a에 도시한 바와 같이, 배선층(11) 위에 듀얼 다마신의 비아 홀을 형성하기 위한 무기물(Inorganic)로 제1 저유전물질(12)을 증착한다.First, as shown in FIG. 2A, the first low dielectric material 12 is deposited on the wiring layer 11 by using an inorganic material for forming a via hole of dual damascene.
상기 배선층(11)은 구리 합금, 구리를 제외한 금속, 상기 금속의 합금 등으로 이루어진다.The wiring layer 11 is made of a copper alloy, a metal other than copper, an alloy of the metal, and the like.
이어 도2b에 도시한 바와 같이 나이트라이드막(13)을 증착한 후 도2c에 도시한 바와 같이, 포토레지스트(14)를 이용하여 서브 메탈과 구리 라인 등으로 구성된 배선층(11)이 오픈될 때까지 식각을 진행하여 비아 홀(via hole : C)을 형성한다.Subsequently, after the nitride film 13 is deposited as shown in FIG. 2B, as shown in FIG. 2C, when the wiring layer 11 composed of submetals and copper lines is opened using the photoresist 14. Etching is performed to form a via hole (C).
이어 포토레지스트(14)를 제거하고 도2d에 도시한 바와 같이 유기물로 저유전물질(15)을 증착한다. 상기 유기물은 카본 폴리머(Carbon Polymer) 등으로 구성되어 있는 물질을 사용하여 증착한다.Then, the photoresist 14 is removed and a low dielectric material 15 is deposited with an organic material as shown in FIG. 2D. The organic material is deposited using a material composed of carbon polymer or the like.
이어 도2e에 도시한 바와 같이, 나이트라이드막(13)이 노출되도록 상기 저유전물질(15)을 에치 백(etch back)한다. 물론 저유전물질(15)과 나이트라이드막(13)과의 높은 셀렉티버티(selectivity)를 보여주는 카본/폴로린(Fluorine) 율이 높은 가스 물질을 사용하여 식각을 진행한다.As shown in FIG. 2E, the low dielectric material 15 is etched back to expose the nitride film 13. Of course, etching is performed using a gaseous material having a high carbon / polorine ratio showing high selectivity between the low dielectric material 15 and the nitride film 13.
상기와 같은 저유전물질(15)의 에치 백(etch back) 진행 시 나이트라이드막(13)은 상기 제1 저유전물질(12)을 보호한다.When the low dielectric material 15 is etched back, the nitride layer 13 protects the first low dielectric material 12.
이어 도2f에 도시한 바와 같이, 옥사이드 트랜치(oxide trench)를 형성하기위해 무기물로 제2 저유전물질(16)을 증착한다.Next, as shown in FIG. 2F, a second low dielectric material 16 is deposited with an inorganic material to form an oxide trench.
도2g에 도시한 바와 같이 포토레지스트(17)로 트랜치 마스크(옥사이드 라인 마스크)를 형성하여 도2h에 도시한 바와 같이, 제2 저유전물질(16)을 식각하여 트랜치(D)를 형성한다.As shown in FIG. 2G, a trench mask (oxide line mask) is formed of the photoresist 17, and as shown in FIG. 2H, the second low dielectric material 16 is etched to form a trench D.
옥사이드 트랜치(D) 형성을 위한 식각 진행시 비아 홀(C)에 채워져 있는 저유전물질(15)이 노출되도록 상기 제2 저유전물질(16)을 식각한다.The second low dielectric material 16 is etched so that the low dielectric material 15 filled in the via hole C is exposed during the etching process for forming the oxide trench D.
저유전물질(15)이 노출되도록 오버 식각을 진행하여도 나이트라이드막(13)이 있기 때문에 제1 저유전물질(12)은 식각되지 않으며, 또한 저유전물질(15)이 비아 홀(C)의 대부분을 채우고 있으므로, 비아 홀(C) 형상은 안전하게 유지된다.Even when the over-etching is performed to expose the low dielectric material 15, since the nitride layer 13 is present, the first low dielectric material 12 is not etched, and the low dielectric material 15 is formed through the via hole C. Since the majority of the gaps are filled, the via hole C shape is kept secure.
즉, 나이트라이드막(13)은 상기 저유전물질(15)의 에치 백(etch back) 진행 시와, 상기 옥사이드 라인 형성을 위한 제2 저유전물질(16)의 식각 진행시 제1 저유전물질(13)을 보호하며, 듀얼 다마신 형상(profile)을 보호한다.That is, the nitride layer 13 may be formed by etching the first low dielectric material 15 and performing etching of the second low dielectric material 16 to form the oxide line. (13) and protect the dual damascene profile.
도2i에 도시한 바와 같이, 02베이스를 이용하여 상기 포토레지스트 등의 트랜치 마스크(17)를 제거하고 상기 02베이스를 이용하여 비아 홀(C)에 채워져 있는 저유전물질(15)이 카본 성분을 함유하기 때문에 상기 트랜치 마스크(17)를 제거시킬 때 상기 저유전물질(15)도 O2와 결합되어 제거된다.As shown in Fig. 2i, using a 02 base removing the trench mask 17, such as the photoresist, and low dielectric materials (15) filled in the via-holes (C) by using the 02 base carbon The low dielectric material 15 is also combined with O 2 and removed when the trench mask 17 is removed because of the components.
이어 도2j 및 도2k에 도시한 바와 같이 구리 등의 금속(18)으로 배선층(11)과 콘택되도록 증착하고 CMP(화학적 기계적 연마) 공정을 수행한다.Subsequently, as shown in FIGS. 2J and 2K, a metal 18 such as copper is deposited to be in contact with the wiring layer 11, and a CMP (chemical mechanical polishing) process is performed.
이상에서 설명한 바와 같은 본 발명에 따른 듀얼 다마신 형성 방법에는 다음과 같은 효과가 있다.The dual damascene formation method according to the present invention as described above has the following effects.
저유전율을 갖는 유기물을 식각하여 비아 홀 내부에 유기물을 채우고 트랜치 식각을 진행하기 때문에 상기 유기물에 의해 비아 홀 형상을 보호할 수 있다.Since the organic material having a low dielectric constant is etched to fill the organic material in the via hole and the trench is etched, the via hole shape may be protected by the organic material.
또한 상기 트랜치 식각시 하드 마스크를 이용하지 않기 때문에 하드 마스크의 부식으로 인해 발생하는 트랜치 및 비아 홀의 스트리에이션 등의 발생을 방지할 수 있고, 비아 홀의 CD 조절 불량도 방지할 수 있다.In addition, since the hard mask is not used when the trench is etched, it is possible to prevent the formation of trenches and saturation of the via holes, etc., which are caused by corrosion of the hard mask, and to prevent CD control of the via holes.
그리고, 나이트라이드막을 하드 마스크로 이용하지 않으므로 나이트라이드막의 두께의 손상이 적으므로 두께가 얇아도 되는 이점이 있다.In addition, since the nitride film is not used as a hard mask, the thickness of the nitride film is small, and thus, the thickness may be thin.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 이탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
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| CN109037040B (en) * | 2018-07-13 | 2021-02-02 | 上海华力集成电路制造有限公司 | Method for improving process window of dual damascene etching sub-groove |
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| KR20000029195A (en) * | 1998-10-21 | 2000-05-25 | 나카네 히사시 | A filling-up material and method of forming a wiring by using the same |
| KR20000077104A (en) * | 1999-04-29 | 2000-12-26 | 윌리엄 비. 켐플러 | Yield improvement of dual damascene fabrication through oxide filling |
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